path: root/arch/x86/kernel/cpu/cpu_debug.c

/*
 * CPU x86 architecture debug code
 *
 * Copyright(C) 2009 Jaswinder Singh Rajput
 *
 * For licencing details see kernel-base/COPYING
 */

#include <linux/interrupt.h>
#include <linux/compiler.h>
#include <linux/seq_file.h>
#include <linux/debugfs.h>
#include <linux/kprobes.h>
#include <linux/uaccess.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/percpu.h>
#include <linux/signal.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/smp.h>

#include <asm/cpu_debug.h>
#include <asm/paravirt.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/apic.h>
#include <asm/desc.h>

static DEFINE_PER_CPU(struct cpu_cpuX_base, cpu_arr[CPU_REG_ALL_BIT]);
static DEFINE_PER_CPU(struct cpu_private *, priv_arr[MAX_CPU_FILES]);
static DEFINE_PER_CPU(unsigned, cpu_modelflag);
static DEFINE_PER_CPU(int, cpu_priv_count);
static DEFINE_PER_CPU(unsigned, cpu_model);

static DEFINE_MUTEX(cpu_debug_lock);

static struct dentry *cpu_debugfs_dir;

static struct cpu_debug_base cpu_base[] = {
	{ "mc",		CPU_MC,		0	},
	{ "monitor",	CPU_MONITOR,	0	},
	{ "time",	CPU_TIME,	0	},
	{ "pmc",	CPU_PMC,	1	},
	{ "platform",	CPU_PLATFORM,	0	},
	{ "apic",	CPU_APIC,	0	},
	{ "poweron",	CPU_POWERON,	0	},
	{ "control",	CPU_CONTROL,	0	},
	{ "features",	CPU_FEATURES,	0	},
	{ "lastbranch",	CPU_LBRANCH,	0	},
	{ "bios",	CPU_BIOS,	0	},
	{ "freq",	CPU_FREQ,	0	},
	{ "mtrr",	CPU_MTRR,	0	},
	{ "perf",	CPU_PERF,	0	},
	{ "cache",	CPU_CACHE,	0	},
	{ "sysenter",	CPU_SYSENTER,	0	},
	{ "therm",	CPU_THERM,	0	},
	{ "misc",	CPU_MISC,	0	},
	{ "debug",	CPU_DEBUG,	0	},
	{ "pat",	CPU_PAT,	0	},
	{ "vmx",	CPU_VMX,	0	},
	{ "call",	CPU_CALL,	0	},
	{ "base",	CPU_BASE,	0	},
	{ "ver",	CPU_VER,	0	},
	{ "conf",	CPU_CONF,	0	},
	{ "smm",	CPU_SMM,	0	},
	{ "svm",	CPU_SVM,	0	},
	{ "osvm",	CPU_OSVM,	0	},
	{ "tss",	CPU_TSS,	0	},
	{ "cr",		CPU_CR,		0	},
	{ "dt",		CPU_DT,		0	},
	{ "registers",	CPU_REG_ALL,	0	},
};

static struct cpu_file_base cpu_file[] = {
	{ "index",	CPU_REG_ALL,	0	},
	{ "value",	CPU_REG_ALL,	1	},
};

/* Intel Registers Range */
static struct cpu_debug_range cpu_intel_range[] = {
	{ 0x00000000, 0x00000001, CPU_MC,	CPU_INTEL_ALL		},
	{ 0x00000006, 0x00000007, CPU_MONITOR,	CPU_CX_AT_XE		},
	{ 0x00000010, 0x00000010, CPU_TIME,	CPU_INTEL_ALL		},
	{ 0x00000011, 0x00000013, CPU_PMC,	CPU_INTEL_PENTIUM	},
	{ 0x00000017, 0x00000017, CPU_PLATFORM,	CPU_PX_CX_AT_XE		},
	{ 0x0000001B, 0x0000001B, CPU_APIC,	CPU_P6_CX_AT_XE		},

	{ 0x0000002A, 0x0000002A, CPU_POWERON,	CPU_PX_CX_AT_XE		},
	{ 0x0000002B, 0x0000002B, CPU_POWERON,	CPU_INTEL_XEON		},
	{ 0x0000002C, 0x0000002C, CPU_FREQ,	CPU_INTEL_XEON		},
	{ 0x0000003A, 0x0000003A, CPU_CONTROL,	CPU_CX_AT_XE		},

	{ 0x00000040, 0x00000043, CPU_LBRANCH,	CPU_PM_CX_AT_XE		},
	{ 0x00000044, 0x00000047, CPU_LBRANCH,	CPU_PM_CO_AT		},
	{ 0x00000060, 0x00000063, CPU_LBRANCH,	CPU_C2_AT		},
	{ 0x00000064, 0x00000067, CPU_LBRANCH,	CPU_INTEL_ATOM		},

	{ 0x00000079, 0x00000079, CPU_BIOS,	CPU_P6_CX_AT_XE		},
	{ 0x00000088, 0x0000008A, CPU_CACHE,	CPU_INTEL_P6		},
	{ 0x0000008B, 0x0000008B, CPU_BIOS,	CPU_P6_CX_AT_XE		},
	{ 0x0000009B, 0x0000009B, CPU_MONITOR,	CPU_INTEL_XEON		},

	{ 0x000000C1, 0x000000C2, CPU_PMC,	CPU_P6_CX_AT		},
	{ 0x000000CD, 0x000000CD, CPU_FREQ,	CPU_CX_AT		},
	{ 0x000000E7, 0x000000E8, CPU_PERF,	CPU_CX_AT		},
	{ 0x000000FE, 0x000000FE, CPU_MTRR,	CPU_P6_CX_XE		},

	{ 0x00000116, 0x00000116, CPU_CACHE,	CPU_INTEL_P6		},
	{ 0x00000118, 0x00000118, CPU_CACHE,	CPU_INTEL_P6		},
	{ 0x00000119, 0x00000119, CPU_CACHE,</