/* $Id: pci_psycho.c,v 1.33 2002/02/01 00:58:33 davem Exp $
* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
*
* Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
* Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
* Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <asm/pbm.h>
#include <asm/iommu.h>
#include <asm/irq.h>
#include <asm/starfire.h>
#include "pci_impl.h"
#include "iommu_common.h"
/* All PSYCHO registers are 64-bits. The following accessor
* routines are how they are accessed. The REG parameter
* is a physical address.
*/
#define psycho_read(__reg) \
({ u64 __ret; \
__asm__ __volatile__("ldxa [%1] %2, %0" \
: "=r" (__ret) \
: "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
: "memory"); \
__ret; \
})
#define psycho_write(__reg, __val) \
__asm__ __volatile__("stxa %0, [%1] %2" \
: /* no outputs */ \
: "r" (__val), "r" (__reg), \
"i" (ASI_PHYS_BYPASS_EC_E) \
: "memory")
/* Misc. PSYCHO PCI controller register offsets and definitions. */
#define PSYCHO_CONTROL 0x0010UL
#define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
#define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
#define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
#define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
#define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
#define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
#define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
#define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
#define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
#define PSYCHO_PCIA_CTRL 0x2000UL
#define PSYCHO_PCIB_CTRL 0x4000UL
#define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
#define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
#define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
#define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
#define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
#define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
#define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
#define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
#define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
/* U2P Programmer's Manual, page 13-55, configuration space
* address format:
*
* 32 24 23 16 15 11 10 8 7 2 1 0
* ---------------------------------------------------------
* |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
* ---------------------------------------------------------
*/
#define PSYCHO_CONFIG_BASE(PBM) \
((PBM)->c