path: root/arch/ppc/syslib/mv64x60_win.c

/*
 * Tables with info on how to manipulate the 32 & 64 bit windows on the
 * various types of Marvell bridge chips.
 *
 * Author: Mark A. Greer <mgreer@mvista.com>
 *
 * 2004 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/mv643xx.h>

#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/delay.h>
#include <asm/mv64x60.h>


/*
 *****************************************************************************
 *
 *	Tables describing how to set up windows on each type of bridge
 *
 *****************************************************************************
 */
struct mv64x60_32bit_window
	gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT] __initdata = {
	/* CPU->MEM Windows */
	[MV64x60_CPU2MEM_0_WIN] = {
		.base_reg		= MV64x60_CPU2MEM_0_BASE,
		.size_reg		= MV64x60_CPU2MEM_0_SIZE,
		.base_bits		= 12,
		.size_bits		= 12,
		.get_from_field		= mv64x60_shift_left,
		.map_to_field		= mv64x60_shift_right,
		.extra			= 0 },
	[MV64x60_CPU2MEM_1_WIN] = {
		.base_reg		= MV64x60_CPU2MEM_1_BASE,
		.size_reg		= MV64x60_CPU2MEM_1_SIZE,
		.base_bits		= 12,
		.size_bits		= 12,
		.get_from_field		= mv64x60_shift_left,
		.map_to_field		= mv64x60_shift_right,
		.extra			= 0 },
	[MV64x60_CPU2MEM_2_WIN] = {
		.base_reg		= MV64x60_CPU2MEM_2_BASE,
		.size_reg		= MV64x60_CPU2MEM_2_SIZE,
		.base_bits		= 12,
		.size_bits		= 12,
		.get_from_field		= mv64x60_shift_left,
		.map_to_field		= mv64x60_shift_right,
		.extra			= 0 },
	[MV64x60_CPU2MEM_3_WIN] = {
		.base_reg		= MV64x60_CPU2MEM_3_BASE,
		.size_reg		= MV64x60_CPU2MEM_3_SIZE,
		.base_bits		= 12,
		.size_bits		= 12,
		.get_from_field		= mv64x60_shift_left,
		.map_to_field		= mv64x60_shift_right,
		.extra			= 0 },
	/* CPU->Device Windows */
	[MV64x60_CPU2DEV_0_WIN] = {
		.base_reg		= MV64x60_CPU2DEV_0_BASE,
		.size_reg		= MV64x60_CPU2DEV_0_SIZE,
		.base_bits		= 12,
		.size_bits		= 12,
		.get_from_field		= mv64x60_shift_left,
		.map_to_field		= mv64x60_shift_right,
		.extra			= 0 },
	[MV64x60_CPU2DEV_1_WIN] = {
		.base_reg		= MV64x60_CPU2DEV_1_BASE,
		.size_reg		= MV64x60_CPU2DEV_1_SIZE,
		.base_bits		= 12,
		.size_bits		= 12,
		.get_from_field		= mv64x60_shift_left,
		.map_to_field		= mv64x60_shift_right,
		.extra			= 0 },
	[MV64x60_CPU2DEV_2_WIN] = {
		.base_reg		= MV64x60_CPU2DEV_2_BASE,
		.size_reg		= MV64x60_CPU2DEV_2_SIZE,
		.base_bits		= 12,
		.size_bits		= 12,
		.get_from_field		= mv64x60_shift_left,
		.map_to_field		= mv64x60_shift_right,
		.extra			= 0 },
	[MV64x60_CPU2DEV_3_WIN] = {
		.base_reg		= MV64x60_CPU2DEV_3_BASE,
		.size_reg		= MV64x60_CPU2DEV_3_SIZE,
		.base_bits		= 12,
		.size_bits		= 12,
		.get_from_field		= mv64x60_shift_left,
		.map_to_field		= mv64x60_shift_right,
		.