path: root/arch/ppc/boot/simple/rw4/ppc_40x.h

/*----------------------------------------------------------------------------+
|       This source code has been made available to you by IBM on an AS-IS
|       basis.  Anyone receiving this source is licensed under IBM
|       copyrights to use it in any way he or she deems fit, including
|       copying it, modifying it, compiling it, and redistributing it either
|       with or without modifications.  No license under IBM patents or
|       patent applications is to be implied by the copyright license.
|
|       Any user of this software should understand that IBM cannot provide
|       technical support for this software and will not be responsible for
|       any consequences resulting from the use of this software.
|
|       Any person who transfers this source code or any derivative work
|       must include the IBM copyright notice, this paragraph, and the
|       preceding two paragraphs in the transferred software.
|
|       COPYRIGHT   I B M   CORPORATION 1997
|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
| Author:    Tony J. Cerreto
| Component: Assembler include file.
| File:      ppc_40x.h
| Purpose:   Include file containing PPC DCR defines.
|
| Changes:
| Date       Author  Comment
| ---------  ------  --------------------------------------------------------
| 01-Mar-00  tjc     Created
+----------------------------------------------------------------------------*/
/* added by linguohui*/
#define MW
/*----------------------------------------------------------------------------+
| PPC Special purpose registers Numbers
+----------------------------------------------------------------------------*/
#define ccr0            0x3b3               /* core configuration reg        */
#define ctr             0x009               /* count register                */
#define ctrreg          0x009               /* count register                */
#define dbcr0           0x3f2               /* debug control register 0      */
#define dbcr1           0x3bd               /* debug control register 1      */
#define dbsr            0x3f0               /* debug status register         */
#define dccr            0x3fa               /* data cache control reg.       */
#define dcwr            0x3ba               /* data cache write-thru reg     */
#define dear            0x3d5               /* data exception address reg    */
#define esr             0x3d4               /* exception syndrome register   */
#define evpr            0x3d6               /* exception vector prefix reg   */
#define iccr            0x3fb               /* instruction cache cntrl re    */
#define icdbdr          0x3d3               /* instr cache dbug data reg     */
#define lrreg           0x008               /* link register                 */
#define pid             0x3b1               /* process id reg                */
#define pit             0x3db               /* programmable interval time    */
#define pvr             0x11f               /* processor version register    */
#define sgr             0x3b9               /* storage guarded reg           */
#define sler            0x3bb               /* storage little endian reg     */
#define sprg0           0x110               /* special general purpose 0     */
#define sprg1           0x111               /* special general purpose 1     */
#define sprg2           0x112               /* special general purpose 2     */
#define sprg3           0x113               /* special general purpose 3     */
#define sprg4           0x114               /* special general purpose 4     */
#define sprg5           0x115               /* special general purpose 5     */
#define sprg6           0x116               /* special general purpose 6     */
#define sprg7           0x117               /* special general purpose 7     */
#define srr0            0x01a               /* save/restore register 0       */
#define srr1            0x01b               /* save/restore register 1       */
#define srr2            0x3de               /* save/restore register 2       */
#define srr3            0x3df               /* save/restore register 3       */
#define tbhi            0x11D
#define tblo            0x11C
#define tcr             0x3da               /* timer control register        */
#define tsr             0x3d8               /* timer status register         */
#define xerreg          0x001               /* fixed point exception         */
#define xer             0x001               /* fixed point exception         */
#define zpr             0x3b0               /* zone protection reg           */

/*----------------------------------------------------------------------------+
| Decompression Controller
+----------------------------------------------------------------------------*/
#define kiar            0x014               /* Decompression cntl addr reg   */
#define kidr            0x015               /* Decompression cntl data reg   */
#define kitor0          0x00                /* index table origin Reg 0      */
#define kitor1          0x01                /* index table origin Reg 1      */
#define kitor2          0x02                /* index table origin Reg 2      */
#define kitor3          0x03                /* index table origin Reg 3      */
#define kaddr0          0x04                /* addr decode Definition Reg 0  */
#define kaddr1          0x05                /* addr decode Definition Reg 1  */
#define kconf           0x40                /* Decompression cntl config reg */
#define kid             0x41                /* Decompression cntl id reg     */
#define kver            0x42                /* Decompression cntl ver number */
#define kpear           0x50                /* bus error addr reg (PLB)      */
#define kbear           0x51                /* bus error addr reg (DCP-EBC)  */
#define kesr0           0x52                /* bus error status reg 0        */

/*----------------------------------------------------------------------------+
| Romeo Specific Device Control Register Numbers.
+----------------------------------------------------------------------------*/
#ifndef VESTA
#define cdbcr           0x3d7                   /* cache debug cntrl reg     */

#define a_latcnt        0x1a9                   /* PLB Latency count         */
#define a_tgval         0x1ac                   /* tone generation value     */
#define a_plb_pr        0x1bf                   /* PLB priority              */

#define cic_sel1        0x031                   /* select register 1         */
#define cic_sel2        0x032                   /* select register 2         */

#define clkgcrst        0x122                   /* chip reset register */

#define cp_cpmsr        0x100                   /*rstatus register           */
#define cp_cpmer        0x101                   /* enable register           */

#define dcp_kiar        0x190                   /* indirect address register */
#define dcp_kidr        0x191                   /* indirect data register    */

#define hsmc_mcgr       0x1c0                   /* HSMC global register      */
#define hsmc_mcbesr     0x1c1                   /* bus error status register */
#define hsmc_mcbear     0x1c2                   /* bus error address register*/
#define hsmc_mcbr0      0x1c4                   /* SDRAM sub-ctrl bank reg 0 */
#define hsmc_mccr0      0x1c5                   /* SDRAM sub-ctrl ctrl reg 0 */
#define hsmc_mcbr1      0x1c7                   /* SDRAM sub-ctrl bank reg 1 */
#define hsmc_mccr1      0x1c8                   /* SDRAM sub-ctrl ctrl reg 1 */
#define hsmc_sysr       0x1d1                   /* system register           */
#define hsmc_data       0x1d2                   /* data register             */
#define hsmc_mccrr      0x1d3                   /* refresh register          */

#define ocm_pbar        0x1E0                   /* base address register     */

#define plb0_pacr0      0x057                   /* PLB arbiter control reg   */
#define plb1_pacr1      0x067                   /* PLB arbiter control reg   */

#define v_displb        0x157                   /* set left border of display*/
#define v_disptb        0x158                   /* top border of display     */
#define v_osd_la        0x159                   /* first link address for OSD*/
#define v_ptsdlta       0x15E                   /* PTS delta register        */
#define v_v0base        0x16C                   /* base mem add for VBI-0    */
#define v_v1base        0x16D                   /* base mem add for VBI-1    */
#define v_osbase        0x16E                   /* base mem add for OSD data */
#endif

/*----------------------------------------------------------------------------+
| Vesta Device Control Register Numbers.
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
| Cross bar switch.
+----------------------------------------------------------------------------*/
#define cbs0_cr         0x010               /* CBS configuration register    */

/*----------------------------------------------------------------------------+
| DCR external master (DCRX).
+----------------------------------------------------------------------------*/
#define dcrx0_icr       0x020               /* internal control register     */
#define dcrx0_isr       0x021               /* internal status register      */
#define dcrx0_ecr       0x022               /* external control register     */
#define dcrx0_esr       0x023               /* external status register      */
#define dcrx0_tar       0x024               /* target address register       */
#define dcrx0_tdr       0x025               /* target data register          */
#define dcrx0_igr       0x026               /* interrupt generation register */
#define dcrx0_bcr       0x027               /* buffer control register       */

/*----------------------------------------------------------------------------+
| Chip interconnect configuration.
+----------------------------------------------------------------------------*/
#define cic0_cr         0x030               /* CIC control register          */
#define cic0_vcr        0x033               /* video macro control reg       */
#define cic0_sel3       0x035               /* select register 3             */

/*----------------------------------------------------------------------------+
| Chip interconnect configuration.
+----------------------------------------------------------------------------*/
#define sgpo0_sgpO      0x036               /* simplified GPIO output        */
#define sgpo0_gpod      0x037               /* simplified GPIO open drain    */
#define sgpo0_gptc      0x038               /* simplified GPIO tristate cntl */
#define sgpo0_gpi       0x039               /* simplified GPIO input         */

/*----------------------------------------------------------------------------+
| Universal interrupt controller.
+----------------------------------------------------------------------------*/
#define uic0_sr         0x040               /* status register               */
#define uic0_srs        0x041               /* status register set           */
#define uic0_er         0x042               /* enable register               */
#define uic0_cr         0x043               /* critical register             */
#define uic0_pr         0x044               /* parity register               */
#define uic0_tr         0x045               /* triggering register           */
#define uic0_msr        0x046               /* masked status register        */
#define uic0_vr         0x047               /* vector register               */
#define uic0_vcr        0x048               /* enable config register        */

/*----------------------------------------------------------------------------+
| PLB 0 and 1.
+----------------------------------------------------------------------------*/
#define pb0_pesr        0x054               /* PLB error status reg 0        */
#define pb0_pesrs       0x055               /* PLB error status reg 0 set    */
#define pb0_pear        0x056               /* PLB error address reg         */

#define pb1_pesr        0x064               /* PLB error status reg 1        */
#define pb1_pesrs       0x065               /* PLB error status reg 1 set    */
#define pb1_pear        0x066               /* PLB error address reg         */

/*----------------------------------------------------------------------------+
| EBIU DCR registers.
+----------------------------------------------------------------------------*/
#define ebiu0_brcrh0    0x070               /* bus region register 0 high    */
#define ebiu0_brcrh1    0x071               /* bus region register 1 high    */
#define ebiu0_brcrh2    0x072               /* bus region register 2 high    */
#define ebiu0_brcrh3    0x073               /* bus region register 3 high    */
#define ebiu0_brcrh4    0x074               /* bus region register 4 high    */
#define ebiu0_brcrh5    0x075               /* bus region register 5 high    */
#define ebiu0_brcrh6    0x076               /* bus region register 6 high    */
#define ebiu0_brcrh7    0x077               /* bus region register 7 high    */
#define ebiu0_brcr0     0x080               /* bus region register 0         */
#define ebiu0_brcr1     0x081               /* bus region register 1         */
#define ebiu0_brcr2     0x082               /* bus region register 2         */
#define ebiu0_brcr3     0x083               /* bus region register 3         */
#define ebiu0_brcr4     0x084               /* bus region register 4         */
#define ebiu0_brcr5     0x085               /* bus region register 5         */
#define ebiu0_brcr6     0x086               /* bus region register 6         */
#define ebiu0_brcr7     0x087               /* bus region register 7         */
#define ebiu0_bear      0x090               /* bus error address register    */
#define ebiu0_besr      0x091               /* bus error syndrome reg        */
#define ebiu0_besr0s    0x093               /* bus error syndrome reg        */
#define ebiu0_biucr     0x09a               /* bus interface control reg     */

/*----------------------------------------------------------------------------+
| OPB bridge.
+----------------------------------------------------------------------------*/
#define opbw0_gesr      0x0b0               /* error status reg              */
#define opbw0_gesrs     0x0b1               /* error status reg              */
#define opbw0_gear      0x0b2               /* error address reg             */

/*----------------------------------------------------------------------------+
| DMA.
+----------------------------------------------------------------------------*/
#define dma0_cr0        0x0c0               /* DMA channel control reg 0     */
#define dma0_ct0        0x0c1               /* DMA count register 0          */
#define dma0_da0        0x0c2               /* DMA destination addr reg 0    */
#define dma0_sa0        0x0c3               /* DMA source addr register 0    */
#define dma0_cc0        0x0c4               /* DMA chained count 0           */
#define dma0_cr1        0x0c8               /* DMA channel control reg 1     */
#define dma0_ct1        0x0c9               /* DMA count register 1          */
#define dma0_da1        0x0ca               /* DMA destination addr reg 1    */
#define dma0_sa1        0x0cb               /* DMA source addr register 1    */
#define dma0_cc1        0x0cc               /* DMA chained count 1           */
#define dma0_cr2        0x0d0               /* DMA channel control reg 2     */
#define dma0_ct2        0x0d1               /* DMA count register 2          */
#define dma0_da2        0x0d2               /* DMA destination addr reg 2    */
#define dma0_sa2        0x0d3               /* DMA source addr register 2    */
#define dma0_cc2        0x0d4               /* DMA chained count 2           */
#define dma0_cr3        0x0d8               /* DMA channel control reg 3     */
#define dma0_ct3        0x0d9               /* DMA count register 3          */
#define dma0_da3        0x0da               /* DMA destination addr reg 3    */
#define dma0_sa3        0x0db               /* DMA source addr register 3    */
#define dma0_cc3        0x0dc               /* DMA chained count 3           */
#define dma0_sr         0x0e0               /* DMA status register           */
#define dma0_srs        0x0e1               /* DMA status register           */
#define dma0_s1         0x031               /* DMA select1 register          */
#define dma0_s2         0x032               /* DMA select2 register          */

/*---------------------------------------------------------------------------+
| Clock and power management.
+----------------------------------------------------------------------------*/
#define cpm0_fr         0x102               /* force register                */

/*----------------------------------------------------------------------------+
| Serial Clock Control.
+----------------------------------------------------------------------------*/
#define ser0_ccr        0x120               /* serial clock control register */

/*----------------------------------------------------------------------------+
| Audio Clock Control.
+----------------------------------------------------------------------------*/
#define aud0_apcr       0x121               /* audio clock ctrl register     */

/*----------------------------------------------------------------------------+
| DENC.
+----------------------------------------------------------------------------*/
#define denc0_idr       0x130               /* DENC ID register              */
#define denc0_cr1       0x131               /* control register 1            */
#define denc0_rr1       0x132               /* microvision 1 (reserved 1)    */
#define denc0_cr2       0x133               /* control register 2            */
#define denc0_rr2       0x134               /* microvision 2 (reserved 2)    */
#define denc0_rr3       0x135               /* microvision 3 (reserved 3)    */
#define denc0_rr4       0x136               /* microvision 4 (reserved 4)    */
#define denc0_rr5       0x137               /* microvision 5 (reserved 5)    */
#define denc0_ccdr      0x138               /* closed caption data           */
#define denc0_cccr      0x139               /* closed caption control        */
#define denc0_trr       0x13A               /* teletext request register     */
#define denc0_tosr      0x13B               /* teletext odd field line se    */
#define denc0_tesr      0x13C               /* teletext even field line s    */
#define denc0_rlsr      0x13D               /* RGB rhift left register       */
#define denc0_vlsr      0x13E               /* video level shift register    */
#define denc0_vsr       0x13F               /* video scaling register        */

/*----------------------------------------------------------------------------+
| Video decoder.  Suspect 0x179, 0x169, 0x16a, 0x152 (rc).
+----------------------------------------------------------------------------*/
#define vid0_ccntl      0x140               /* control decoder operation     */
#define vid0_cmode      0x141               /* video operational mode        */
#define vid0_sstc0      0x142               /* STC high order bits 31:0      */
#define vid0_sstc1      0x143               /* STC low order bit 32          */
#define vid0_spts0      0x144               /* PTS high order bits 31:0      */
#define vid0_spts1      0x145               /* PTS low order bit 32          */
#define vid0_fifo       0x146               /* FIFO data port                */
#define vid0_fifos      0x147               /* FIFO status                   */
#define vid0_cmd        0x148               /* send command to decoder       */
#define vid0_cmdd       0x149               /* port for command params       */
#define vid0_cmdst      0x14A               /* command status                */
#define vid0_cmdad      0x14B               /* command address               */
#define vid0_procia     0x14C               /* instruction store             */
#define vid0_procid     0x14D               /* data port for I_Store         */
#define vid0_osdm       0x151               /* OSD mode control              */
#define vid0_hosti      0x152               /* base interrupt register       */
#define vid0_mask       0x153               /* interrupt mask register       */
#define vid0_dispm      0x154               /* operational mode for Disp     */
#define vid0_dispd      0x155               /* setting for 'Sync' delay      */
#define vid0_vbctl      0x156               /* VBI                           */
#define vid0_ttxctl     0x157               /* teletext control              */
#define vid0_disptb     0x158               /* display left/top border       */
#define vid0_osdgla     0x159               /* Graphics plane link addr      */
#define vid0_osdila     0x15A               /* Image plane link addr         */
#define vid0_rbthr      0x15B               /* rate buffer threshold         */
#define vid0_osdcla     0x15C               /* Cursor link addr              */
#define vid0_stcca      0x15D               /* STC common address            */
#define vid0_ptsctl     0x15F               /* PTS Control                   */
#define vid0_wprot      0x165               /* write protect for I_Store     */
#define vid0_vcqa       0x167               /* video clip queued block Ad    */
#define vid0_vcql       0x168               /* video clip queued block Le    */
#define vid0_blksz      0x169               /* block size bytes for copy op  */