path: root/arch/powerpc/sysdev/ipic.c

/*
 * arch/powerpc/sysdev/ipic.c
 *
 * IPIC routines implementations.
 *
 * Copyright 2005 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/stddef.h>
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/sysdev.h>
#include <linux/device.h>
#include <linux/bootmem.h>
#include <linux/spinlock.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/ipic.h>

#include "ipic.h"

static struct ipic * primary_ipic;
static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
static DEFINE_SPINLOCK(ipic_lock);

static struct ipic_info ipic_info[] = {
	[1] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_C,
		.force	= IPIC_SIFCR_H,
		.bit	= 16,
		.prio_mask = 0,
	},
	[2] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_C,
		.force	= IPIC_SIFCR_H,
		.bit	= 17,
		.prio_mask = 1,
	},
	[3] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_C,
		.force	= IPIC_SIFCR_H,
		.bit	= 18,
		.prio_mask = 2,
	},
	[4] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_C,
		.force	= IPIC_SIFCR_H,
		.bit	= 19,
		.prio_mask = 3,
	},
	[5] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_C,
		.force	= IPIC_SIFCR_H,
		.bit	= 20,
		.prio_mask = 4,
	},
	[6] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_C,
		.force	= IPIC_SIFCR_H,
		.bit	= 21,
		.prio_mask = 5,
	},
	[7] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_C,
		.force	= IPIC_SIFCR_H,
		.bit	= 22,
		.prio_mask = 6,
	},
	[8] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_C,
		.force	= IPIC_SIFCR_H,
		.bit	= 23,
		.prio_mask = 7,
	},
	[9] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_D,
		.force	= IPIC_SIFCR_H,
		.bit	= 24,
		.prio_mask = 0,
	},
	[10] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_D,
		.force	= IPIC_SIFCR_H,
		.bit	= 25,
		.prio_mask = 1,
	},
	[11] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_D,
		.force	= IPIC_SIFCR_H,
		.bit	= 26,
		.prio_mask = 2,
	},
	[12] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_D,
		.force	= IPIC_SIFCR_H,
		.bit	= 27,
		.prio_mask = 3,
	},
	[13] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_D,
		.force	= IPIC_SIFCR_H,
		.bit	= 28,
		.prio_mask = 4,
	},
	[14] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_D,
		.force	= IPIC_SIFCR_H,
		.bit	= 29,
		.prio_mask = 5,
	},
	[15] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_D,
		.force	= IPIC_SIFCR_H,
		.bit	= 30,
		.prio_mask = 6,
	},
	[16] = {
		.mask	= IPIC_SIMSR_H,
		.prio	= IPIC_SIPRR_D,
		.force	= IPIC_SIFCR_H,
		.bit	= 31,
		.prio_mask = 7,
	},
	[17] = {
		.ack	= IPIC_SEPNR,
		.mask	= IPIC_SEMSR,
		.prio	= IPIC_SMPRR_A,
		.force	= IPIC_SEFCR,
		.bit	= 1,
		.prio_mask = 5,
	},
	[18] = {
		.ack	=