1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
|
/*****************************************************************************/
/*
* head.S -- common startup code for ColdFire CPUs.
*
* (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>.
*/
/*****************************************************************************/
#include <linux/sys.h>
#include <linux/linkage.h>
#include <asm/asm-offsets.h>
#include <asm/coldfire.h>
#include <asm/mcfcache.h>
#include <asm/mcfsim.h>
/*****************************************************************************/
/*
* If we don't have a fixed memory size, then lets build in code
* to auto detect the DRAM size. Obviously this is the prefered
* method, and should work for most boards. It won't work for those
* that do not have their RAM starting at address 0, and it only
* works on SDRAM (not boards fitted with SRAM).
*/
#if CONFIG_RAMSIZE != 0
.macro GET_MEM_SIZE
movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */
.endm
#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
defined(CONFIG_M5249) || defined(CONFIG_M527x) || \
defined(CONFIG_M528x) || defined(CONFIG_M5307) || \
defined(CONFIG_M5407)
/*
* Not all these devices have exactly the same DRAM controller,
* but the DCMR register is virtually identical - give or take
* a couple of bits. The only exception is the 5272 devices, their
* DRAM controller is quite different.
*/
.macro GET_MEM_SIZE
movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */
btst #0,%d0 /* check if region enabled */
beq 1f
andl #0xfffc0000,%d0
beq 1f
addl #0x00040000,%d0 /* convert mask to size */
1:
movel MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
btst #0,%d1 /* check if region enabled */
beq 2f
andl #0xfffc0000, %d1
beq 2f
addl #0x00040000,%d1
addl %d1,%d0 /* total mem size in d0 */
2:
.endm
#elif defined(CONFIG_M5272)
.macro GET_MEM_SIZE
movel MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
andil #0xfffff000,%d0 /* mask out chip select options */
negl %d0 /* negate bits */
.endm
#else
#error "ERROR: I don't know how to probe your boards memory size?"
#endif
/*****************************************************************************/
/*
* Boards and platforms can do specific early hardware setup if
* they need to. Most don't need this, define away if not required.
*/
#ifndef PLATFORM_SETUP
#define PLATFORM_SETUP
#endif
/*****************************************************************************/
.global _start
.global _rambase
.global _ramvec
.global _ramstart
.global _ramend
/*****************************************************************************/
.data
/*
* During startup we store away the RAM setup. These are not in the
* bss, since their values are determined and written before the bss
* has been cleared.
*/
_rambase:
.long 0
_ramvec:
.long 0
_ramstart:
.long 0
_ramend:
.long 0
/*****************************************************************************/
.text
/*
* This is the codes first entry point. This is where it all
* begins...
*/
_start:
nop /* filler */
movew #0x2700, %sr /* no interrupts */
/*
* Do any platform or board specific setup now. Most boards
* don't need anything. Those exceptions are define this in
* their board specific includes.
*/
PLATFORM_SETUP
/*
* Create basic memory configuration. Set VBR accordingly,
* and size memory.
*/
movel #CONFIG_VECTORBASE,%a7
movec %a7,%VBR /* set vectors addr */
movel %a7,_ramvec
movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */
movel %a7,_rambase
GET_MEM_SIZE /* macro code determines size */
addl %a7,%d0
movel %d0,_ramend /* set end ram addr */
/*
* Now that we know what the memory is, lets enable cache
* and get things moving. This is Coldfire CPU specific.
*/
CACHE_ENABLE /* enable CPU cache */
#ifdef CONFIG_ROMFS_FS
/*
* Move ROM filesystem above bss :-)
*/
lea _sbss,%a0 /* get start of bss */
lea _ebss,%a1 /* set up destination */
movel %a0,%a2 /* copy of bss start */
movel 8(%a0),%d0 /* get size of ROMFS */
addql #8,%d0 /* allow for rounding */
andl #0xfffffffc, %d0 /* whole words */
addl %d0,%a0 /* copy from end */
addl %d0,%a1 /* copy from end */
movel %a1,_ramstart /* set start of ram */
_copy_romfs:
movel -(%a0),%d0 /* copy dword */
movel %d0,-(%a1)
cmpl %a0,%a2 /* check if at end */
bne _copy_romfs
#else /* CONFIG_ROMFS_FS */
lea _ebss,%a1
movel %a1,_ramstart
#endif /* CONFIG_ROMFS_FS */
/*
* Zero out the bss region.
*/
lea _sbss,%a0 /* get start of bss */
lea _ebss,%a1 /* get end of bss */
clrl %d0 /* set value */
_clear_bss:
movel %d0,(%a0)+ /* clear each word */
cmpl %a0,%a1 /* check if at end */
bne _clear_bss
/*
* Load the current task pointer and stack.
*/
lea init_thread_union,%a0
lea THREAD_SIZE(%a0),%sp
/*
* Assember start up done, start code proper.
*/
jsr start_kernel /* start Linux kernel */
_exit:
jmp _exit /* should never get here */
/*****************************************************************************/
|
