path: root/arch/arm/mach-mx5/clock-mx51.c

/*
 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/clkdev.h>
#include <asm/div64.h>

#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/clock.h>

#include "crm_regs.h"

/* External clock values passed-in by the board code */
static unsigned long external_high_reference, external_low_reference;
static unsigned long oscillator_reference, ckih2_reference;

static struct clk osc_clk;
static struct clk pll1_main_clk;
static struct clk pll1_sw_clk;
static struct clk pll2_sw_clk;
static struct clk pll3_sw_clk;
static struct clk lp_apm_clk;
static struct clk periph_apm_clk;
static struct clk ahb_clk;
static struct clk ipg_clk;
static struct clk usboh3_clk;

#define MAX_DPLL_WAIT_TRIES	1000 /* 1000 * udelay(1) = 1ms */

/* calculate best pre and post dividers to get the required divider */
static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
	u32 max_pre, u32 max_post)
{
	if (div >= max_pre * max_post) {
		*pre = max_pre;
		*post = max_post;
	} else if (div >= max_pre) {
		u32 min_pre, temp_pre, old_err, err;
		min_pre = DIV_ROUND_UP(div, max_post);
		old_err = max_pre;
		for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
			err = div % temp_pre;
			if (err == 0) {
				*pre = temp_pre;
				break;
			}
			err = temp_pre - err;
			if (err < old_err) {
				old_err = err;
				*pre = temp_pre;
			}
		}
		*post = DIV_ROUND_UP(div, *pre);
	} else {
		*pre = div;
		*post = 1;
	}
}

static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
{
	u32 reg = __raw_readl(clk->enable_reg);

	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
	reg |= mode << clk->enable_shift;

	__raw_writel(reg, clk->enable_reg);
}

static int _clk_ccgr_enable(struct clk *clk)
{
	_clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
	return 0;
}

static void _clk_ccgr_disable(struct clk *clk)
{
	_clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
}

static int _clk_ccgr_enable_inrun(struct clk *clk)
{
	_clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
	return 0;
}

static void _clk_ccgr_disable_inwait(struct clk *clk)
{
	_clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
}

/*
 * For the 4-to-1 muxed input clock
 */
static inline u32 _get_mux(struct clk *parent, struct clk *m0,
			   struct clk *m1, struct clk *m2, struct clk *m3)
{
	if (parent == m0)
		return 0;
	else if (parent == m1)
		return 1;
	else if (parent == m2)
		return 2