1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
|
/*
* linux/arch/arm/mach-integrator/core.c
*
* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/export.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/memblock.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/amba/bus.h>
#include <linux/amba/serial.h>
#include <linux/io.h>
#include <linux/stat.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/mach-types.h>
#include <asm/mach/time.h>
#include <asm/pgtable.h>
#include "cm.h"
#include "common.h"
static DEFINE_RAW_SPINLOCK(cm_lock);
static void __iomem *cm_base;
/**
* cm_get - get the value from the CM_CTRL register
*/
u32 cm_get(void)
{
return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET);
}
/**
* cm_control - update the CM_CTRL register.
* @mask: bits to change
* @set: bits to set
*/
void cm_control(u32 mask, u32 set)
{
unsigned long flags;
u32 val;
raw_spin_lock_irqsave(&cm_lock, flags);
val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask;
writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET);
raw_spin_unlock_irqrestore(&cm_lock, flags);
}
static const char *integrator_arch_str(u32 id)
{
switch ((id >> 16) & 0xff) {
case 0x00:
return "ASB little-endian";
case 0x01:
return "AHB little-endian";
case 0x03:
return "AHB-Lite system bus, bi-endian";
case 0x04:
return "AHB";
case 0x08:
return "AHB system bus, ASB processor bus";
default:
return "Unknown";
}
}
static const char *integrator_fpga_str(u32 id)
{
switch ((id >> 12) & 0xf) {
case 0x01:
return "XC4062";
case 0x02:
return "XC4085";
case 0x03:
return "XVC600";
case 0x04:
return "EPM7256AE (Altera PLD)";
default:
return "Unknown";
}
}
void cm_clear_irqs(void)
{
/* disable core module IRQs */
writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET +
IRQ_ENABLE_CLEAR);
}
static const struct of_device_id cm_match[] = {
{ .compatible = "arm,core-module-integrator"},
{ },
};
void cm_init(void)
{
struct device_node *cm = of_find_matching_node(NULL, cm_match);
u32 val;
if (!cm) {
pr_crit("no core module node found in device tree\n");
return;
}
cm_base = of_iomap(cm, 0);
if (!cm_base) {
pr_crit("could not remap core module\n");
return;
}
cm_clear_irqs();
val = readl(cm_base + INTEGRATOR_HDR_ID_OFFSET);
pr_info("Detected ARM core module:\n");
pr_info(" Manufacturer: %02x\n", (val >> 24));
pr_info(" Architecture: %s\n", integrator_arch_str(val));
pr_info(" FPGA: %s\n", integrator_fpga_str(val));
pr_info(" Build: %02x\n", (val >> 4) & 0xFF);
pr_info(" Rev: %c\n", ('A' + (val & 0x03)));
}
/*
* We need to stop things allocating the low memory; ideally we need a
* better implementation of GFP_DMA which does not assume that DMA-able
* memory starts at zero.
*/
void __init integrator_reserve(void)
{
memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
}
/*
* To reset, we hit the on-board reset register in the system FPGA
*/
void integrator_restart(enum reboot_mode mode, const char *cmd)
{
cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
}
static u32 integrator_id;
static ssize_t intcp_get_manf(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return sprintf(buf, "%02x\n", integrator_id >> 24);
}
static struct device_attribute intcp_manf_attr =
__ATTR(manufacturer, S_IRUGO, intcp_get_manf, NULL);
static ssize_t intcp_get_arch(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return sprintf(buf, "%s\n", integrator_arch_str(integrator_id));
}
static struct device_attribute intcp_arch_attr =
__ATTR(architecture, S_IRUGO, intcp_get_arch, NULL);
static ssize_t intcp_get_fpga(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return sprintf(buf, "%s\n", integrator_fpga_str(integrator_id));
}
static struct device_attribute intcp_fpga_attr =
__ATTR(fpga, S_IRUGO, intcp_get_fpga, NULL);
static ssize_t intcp_get_build(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return sprintf(buf, "%02x\n", (integrator_id >> 4) & 0xFF);
}
static struct device_attribute intcp_build_attr =
__ATTR(build, S_IRUGO, intcp_get_build, NULL);
void integrator_init_sysfs(struct device *parent, u32 id)
{
integrator_id = id;
device_create_file(parent, &intcp_manf_attr);
device_create_file(parent, &intcp_arch_attr);
device_create_file(parent, &intcp_fpga_attr);
device_create_file(parent, &intcp_build_attr);
}
|
