/*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Clock support for EXYNOS5 SoCs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pm.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
#include "common.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos5_clock_save[] = {
/* will be implemented */
};
#endif
static struct clk exynos5_clk_sclk_dptxphy = {
.name = "sclk_dptx",
};
static struct clk exynos5_clk_sclk_hdmi24m = {
.name = "sclk_hdmi24m",
.rate = 24000000,
};
static struct clk exynos5_clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.rate = 27000000,
};
static struct clk exynos5_clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
};
static struct clk exynos5_clk_sclk_usbphy = {
.name = "sclk_usbphy",
.rate = 48000000,
};
static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
}
static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
}
static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
}
static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
}
static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
}
static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
}
static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
}
static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
}
static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK<