path: root/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h

/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/

#ifndef CHIPC_DEF_H
#define CHIPC_DEF_H

/* ---- Include Files ----------------------------------------------------- */

#include <csp/stdint.h>
#include <csp/errno.h>
#include <csp/reg.h>
#include <mach/csp/chipcHw_reg.h>

/* ---- Public Constants and Types ---------------------------------------- */

/* Set 1 to configure DDR/VPM phase alignment by HW */
#define chipcHw_DDR_HW_PHASE_ALIGN    0
#define chipcHw_VPM_HW_PHASE_ALIGN    0

typedef uint32_t chipcHw_freq;

/* Configurable miscellaneous clocks */
typedef enum {
	chipcHw_CLOCK_DDR,	/* DDR PHY Clock */
	chipcHw_CLOCK_ARM,	/* ARM Clock */
	chipcHw_CLOCK_ESW,	/* Ethernet Switch Clock */
	chipcHw_CLOCK_VPM,	/* VPM Clock */
	chipcHw_CLOCK_ESW125,	/* Ethernet MII Clock */
	chipcHw_CLOCK_UART,	/* UART Clock */
	chipcHw_CLOCK_SDIO0,	/* SDIO 0 Clock */
	chipcHw_CLOCK_SDIO1,	/* SDIO 1 Clock */
	chipcHw_CLOCK_SPI,	/* SPI Clock */
	chipcHw_CLOCK_ETM,	/* ARM ETM Clock */

	chipcHw_CLOCK_BUS,	/* BUS Clock */
	chipcHw_CLOCK_OTP,	/* OTP Clock */
	chipcHw_CLOCK_I2C,	/* I2C Host Clock */
	chipcHw_CLOCK_I2S0,	/* I2S 0 Host Clock */
	chipcHw_CLOCK_RTBUS,	/* DDR PHY Configuration Clock */
	chipcHw_CLOCK_APM100,	/* APM100 Clock */
	chipcHw_CLOCK_TSC,	/* Touch screen Clock */
	chipcHw_CLOCK_LED,	/* LED Clock */

	chipcHw_CLOCK_USB,	/* USB Clock */
	chipcHw_CLOCK_LCD,	/* LCD CLock */
	chipcHw_CLOCK_APM,	/* APM Clock */

	chipcHw_CLOCK_I2S1,	/* I2S 1 Host Clock */
} chipcHw_CLOCK_e;

/* System booting strap options */
typedef enum {
	chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
	chipcHw_BOOT_DEVICE_SERIAL_FLASH =
	    chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
	chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
	    chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
	chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
	    chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
	chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
	    chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
} chipcHw_BOOT_DEVICE_e;

/* System booting modes */
typedef enum {
	chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
	chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
	chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
	chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
} chipcHw_BOOT_MODE_e;

/* NAND Flash page size strap options */
typedef enum {
	chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
	chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
	chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
	chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
} chipcHw_NAND_PAGESIZE_e;

/* GPIO Pin function */
typedef enum {
	chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
	chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
	chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
	chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
	chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
	chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
	chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
	chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
	chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
	chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
	chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
	chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
	chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
	chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
} chipcHw_GPIO_FUNCTION_e;

/* PIN Output slew rate */
typedef enum {
	chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
	chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
} chipcHw_PIN_SLEW_RATE_e;

/* PIN Current drive strength */
typedef enum {
	chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
	chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
	chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
	chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
	chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
	chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
} chipcHw_PIN_CURRENT_STRENGTH_e;

/* PIN Pull up register settings */
typedef enum {
	chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
	chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
	chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
} chipcHw_PIN_PULL_e;

/* PIN input type settings */
typedef enum {
	chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
	chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
} chipcHw_PIN_INPUTTYPE_e;

/* Allow/Disalow the support of spread spectrum  */
typedef enum {
	chipcHw_SPREAD_SPECTRUM_DISALLOW,	/* Spread spectrum support is not allowed */
	chipcHw_SPREAD_SPECTRUM_ALLOW	/* Spread spectrum support is allowed */
} chipcHw_SPREAD_SPECTRUM_e;

typedef