path: root/arch/arm/boot/dts/omap4.dtsi

/*
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,omap4430", "ti,omap4";
	interrupt-parent = <&gic>;

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&L2>;
			reg = <0x0>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */
		};
		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
	};

	gic: interrupt-controller@48241000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48241000 0x1000>,
		      <0x48240100 0x0100>;
	};

	L2: l2-cache-controller@48242000 {
		compatible = "arm,pl310-cache";
		reg = <0x48242000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	local-timer@48240600 {
		compatible = "arm,cortex-a9-twd-timer";
		clocks = <&mpu_periphclk>;
		reg = <0x48240600 0x20>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	/*
	 * The soc node represents the soc top level view. It is used for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap4-mpu";
			ti,hwmods = "mpu";
		};

		dsp {
			compatible = "ti,omap3-c64";
			ti,hwmods = "dsp";
		};

		iva {
			compatible = "ti,ivahd";
			ti,hwmods = "iva";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP4 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since it will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
		reg = <0x44000000 0x1000>,
		      <0x44800000 0x2000>,
		      <0x45000000 0x1000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

		cm1: cm1@4a004000 {
			compatible = "ti,omap4-cm1";
			reg = <0x4a004000 0x2000>;

			cm1_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			cm1_clockdomains: clockdomains {
			};
		};

		prm: prm@4a306000 {
			compatible = "ti,omap4-prm";
			reg = <0x4a306000 0x3000>;

			prm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			prm_clockdomains: clockdomains {
			};
		};

		cm2: cm2@4a008000 {
			compatible = "ti,omap4-cm2";
			reg = <0x4a008000 0x3000>;

			cm2_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			cm2_clockdomains: clockdomains {
			};
		};

		scrm: scrm@4a30a000 {
			compatible = "ti,omap4-scrm";
			reg = <0x4a30a000 0x2000>;

			scrm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			scrm_clockdomains: clockdomains {
			};
		};

		counter32k: counter@4a304000 {
			compatible = "ti,omap-counter32k";
			reg = <0x4a304000 0x20>;
			ti,hwmods = "counter_32k";
		};

		omap4_pmx_core: pinmux@4a100040 {
			compatible = "ti,omap4-padconf", "pinctrl-single";