path: root/arch/arm/boot/dts/imx6sl.dtsi

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include "skeleton.dtsi"
#include "imx6sl-pinfunc.h"
#include <dt-bindings/clock/imx6sl-clock.h>

/ {
	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x0>;
			next-level-cache = <&L2>;
		};
	};

	intc: interrupt-controller@00a01000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-controller;
		reg = <0x00a01000 0x1000>,
		      <0x00a00100 0x100>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		osc {
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&intc>;
		ranges;

		L2: l2-cache@00a02000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a02000 0x1000>;
			interrupts = <0 92 0x04>;
			cache-unified;
			cache-level = <2>;
			arm,tag-latency = <4 2 3>;
			arm,data-latency = <4 2 3>;
		};

		pmu {
			compatible = "arm,cortex-a9-pmu";
			interrupts = <0 94 0x04>;
		};

		aips1: aips-bus@02000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02000000 0x100000>;
			ranges;

			spba: spba-bus@02000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02000000 0x40000>;
				ranges;

				spdif: spdif@02004000 {
					reg = <0x02004000 0x4000>;
					interrupts = <0 52 0x04>;
				};

				ecspi1: ecspi@02008000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
					reg = <0x02008000 0x4000>;
					interrupts = <0 31 0x04>;
					clocks = <&clks IMX6SL_CLK_ECSPI1>,
						 <&clks IMX6SL_CLK_ECSPI1>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi2: ecspi@0200c000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
					reg = <0x0200c000 0x4000>;
					interrupts = <0 32 0x04>;
					clocks = <&clks IMX6SL_CLK_ECSPI2>,
						 <&clks IMX6SL_CLK_ECSPI2>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi3: ecspi@02010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
					reg = <0x02010000 0x4000>;
					interrupts = <0 33 0x04>;
					clocks = <&clks IMX6SL_CLK_ECSPI3>,
						 <&clks IMX6SL_CLK_ECSPI3>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi4: ecspi@02014000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
					reg = <0x02014000 0x4000>;
					interrupts = <0 34 0x04>;
					clocks = <&clks IMX6SL_CLK_ECSPI4>,
						 <&clks IMX6SL_CLK_ECSPI4>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart5: serial@02018000 {
					compatible = "fsl,imx6sl-uart",
						   "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02018000 0x4000>;
					interrupts = <0 30 0x04>;
					clocks = <&clks IMX6SL_CLK_UART>,
						 <&clks IMX6SL_CLK_UART_SERIAL>;
					clock-names = "ipg", "per";
					dmas = <&sdma 33 4 0>, <&sdma