path: root/arch/arm/boot/dts/imx6q.dtsi

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			reg = <0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			reg = <2>;
			next-level-cache = <&L2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			reg = <3>;
			next-level-cache = <&L2>;
		};
	};

	intc: interrupt-controller@00a01000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-controller;
		reg = <0x00a01000 0x1000>,
		      <0x00a00100 0x100>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&intc>;
		ranges;

		dma-apbh@00110000 {
			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x00110000 0x2000>;
		};

		gpmi-nand@00112000 {
		       compatible = "fsl,imx6q-gpmi-nand";
		       #address-cells = <1>;
		       #size-cells = <1>;
		       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
		       reg-names = "gpmi-nand", "bch";
		       interrupts = <0 13 0x04>, <0 15 0x04>;
		       interrupt-names = "gpmi-dma", "bch";
		       fsl,gpmi-dma-channel = <0>;
		       status = "disabled";
		};

		timer@00a00600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x00a00600 0x20>;
			interrupts = <1 13 0xf01>;
		};

		L2: l2-cache@00a02000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a02000 0x1000>;
			interrupts = <0 92 0x04>;
			cache-unified;
			cache-level = <2>;
		};

		aips-bus@02000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02000000 0x100000>;
			ranges;

			spba-bus@02000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02000000 0x40000>;
				ranges;

				spdif@02004000 {
					reg = <0x02004000 0x4000>;
					interrupts = <0 52 0x04>;
				};

				ecspi@02008000 { /* eCSPI1 */
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02008000 0x4000>;
					interrupts = <0 31 0x04>;
					status = "disabled";
				};

				ecspi@0200c000 { /* eCSPI2 */
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x0200c000 0x4000>;
					interrupts = <0 32 0x04>;
					status = "disabled";
				};

				ecspi@02010000 { /* eCSPI3 */
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02010000 0x4000>;
					interrupts = <0 33 0x04>;
					status = "disabled";
				};

				ecspi@02014000 { /* eCSPI4 */
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02014000 0x4000>;
					interrupts = <0 34 0x04>;
					status = "disabled";
				};

				ecspi