From 70c14ff0e9f5e1f5456587b827620e636ba70a09 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Fri, 20 Jul 2007 02:07:26 +0100 Subject: [ARM] 4495/1: iop: combined watchdog timer driver for iop3xx and iop13xx In order for this driver to be shared across the iop architectures the iop3xx and iop13xx header files are modified to present a common interface for the iop_wdt driver. Details: * iop13xx supports disabling the timer while iop3xx does not. This requires a few 'compatibility' definitions in include/asm-arm/hardware/iop3xx.h to preclude adding #ifdef CONFIG_ARCH_IOP13XX blocks to the driver code. * The heartbeat interval is derived from the internal bus clock rate, so this this patch also exports the tick rate to the iop_wdt driver. Cc: Curt Bruns Cc: Peter Milne Signed-off-by: Dan Williams Acked-by: Wim Van Sebroeck Signed-off-by: Russell King --- include/asm-arm/arch-iop13xx/iop13xx.h | 43 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-iop13xx/system.h | 34 ++------------------------- include/asm-arm/hardware/iop3xx.h | 33 ++++++++++++++++++++++++++ 3 files changed, 78 insertions(+), 32 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index d4e4f828577..52b7fab7ef6 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -19,6 +19,39 @@ static inline int iop13xx_cpu_id(void) return id; } +/* WDTCR CP6 R7 Page 9 */ +static inline u32 read_wdtcr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); + return val; +} +static inline void write_wdtcr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); +} + +/* WDTSR CP6 R8 Page 9 */ +static inline u32 read_wdtsr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); + return val; +} +static inline void write_wdtsr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); +} + +/* RCSR - Reset Cause Status Register */ +static inline u32 read_rcsr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val)); + return val; +} + +extern unsigned long get_iop_tick_rate(void); #endif /* @@ -480,4 +513,14 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) #define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) + +/* Watchdog timer definitions */ +#define IOP_WDTCR_EN_ARM 0x1e1e1e1e +#define IOP_WDTCR_EN 0xe1e1e1e1 +#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f +#define IOP_WDTCR_DIS 0xf1f1f1f1 +#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */ +#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */ +#define IOP13XX_WDTCR_IB_RESET (1 << 0) + #endif /* _IOP13XX_HW_H_ */ diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h index 127827058e1..8575af8db78 100644 --- a/include/asm-arm/arch-iop13xx/system.h +++ b/include/asm-arm/arch-iop13xx/system.h @@ -13,43 +13,13 @@ static inline void arch_idle(void) cpu_do_idle(); } -/* WDTCR CP6 R7 Page 9 */ -static inline u32 read_wdtcr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); - return val; -} -static inline void write_wdtcr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); -} - -/* WDTSR CP6 R8 Page 9 */ -static inline u32 read_wdtsr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); - return val; -} -static inline void write_wdtsr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); -} - -#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e -#define IOP13XX_WDTCR_EN 0xe1e1e1e1 -#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f -#define IOP13XX_WDTCR_DIS 0xf1f1f1f1 -#define IOP13XX_WDTSR_WRITE_EN (1 << 31) -#define IOP13XX_WDTCR_IB_RESET (1 << 0) static inline void arch_reset(char mode) { /* * Reset the internal bus (warning both cores are reset) */ - write_wdtcr(IOP13XX_WDTCR_EN_ARM); - write_wdtcr(IOP13XX_WDTCR_EN); + write_wdtcr(IOP_WDTCR_EN_ARM); + write_wdtcr(IOP_WDTCR_EN); write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); write_wdtcr(0x1000); diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index 81ca5d3e2bf..fb90b421f31 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -194,6 +194,13 @@ extern int init_atu; #define IOP_TMR_PRIVILEGED 0x08 #define IOP_TMR_RATIO_1_1 0x00 +/* Watchdog timer definitions */ +#define IOP_WDTCR_EN_ARM 0x1e1e1e1e +#define IOP_WDTCR_EN 0xe1e1e1e1 +/* iop3xx does not support stopping the watchdog, so we just re-arm */ +#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM) +#define IOP_WDTCR_DIS (IOP_WDTCR_EN) + /* Application accelerator unit */ #define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800) #define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7) @@ -274,6 +281,32 @@ static inline void write_tisr(u32 val) asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); } +static inline u32 read_wdtcr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val)); + return val; +} +static inline void write_wdtcr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val)); +} + +extern unsigned long get_iop_tick_rate(void); + +/* only iop13xx has these registers, we define these to present a + * common register interface for the iop_wdt driver. + */ +#define IOP_RCSR_WDT (0) +static inline u32 read_rcsr(void) +{ + return 0; +} +static inline void write_wdtsr(u32 val) +{ + do { } while (0); +} + extern struct platform_device iop3xx_dma_0_channel; extern struct platform_device iop3xx_dma_1_channel; extern struct platform_device iop3xx_aau_channel; -- cgit v1.2.3-18-g5258