From 30bd3b56db37a2c2eb6d3bb14ce02156807c79ed Mon Sep 17 00:00:00 2001 From: Malcolm Priestley Date: Sun, 13 Feb 2011 20:12:15 -0300 Subject: [media] DM04/QQBOX Fix issue with firmware release and cold reset Fix issue where firmware does not release on cold reset. Also, default firmware never cold resets in multi tuner environment. Signed-off-by: Malcolm Priestley Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb/dvb-usb/lmedm04.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/media/dvb/dvb-usb/lmedm04.c b/drivers/media/dvb/dvb-usb/lmedm04.c index f2db01212ca..3c521db0a13 100644 --- a/drivers/media/dvb/dvb-usb/lmedm04.c +++ b/drivers/media/dvb/dvb-usb/lmedm04.c @@ -747,7 +747,7 @@ static int lme_firmware_switch(struct usb_device *udev, int cold) fw_lme = fw_s0194; ret = request_firmware(&fw, fw_lme, &udev->dev); if (ret == 0) { - cold = 0;/*lme2510-s0194 cannot cold reset*/ + cold = 0; break; } dvb_usb_lme2510_firmware = TUNER_LG; @@ -769,8 +769,10 @@ static int lme_firmware_switch(struct usb_device *udev, int cold) case TUNER_S7395: fw_lme = fw_c_s7395; ret = request_firmware(&fw, fw_lme, &udev->dev); - if (ret == 0) + if (ret == 0) { + cold = 0; break; + } dvb_usb_lme2510_firmware = TUNER_LG; case TUNER_LG: fw_lme = fw_c_lg; @@ -796,14 +798,14 @@ static int lme_firmware_switch(struct usb_device *udev, int cold) ret = lme2510_download_firmware(udev, fw); } + release_firmware(fw); + if (cold) { info("FRM Changing to %s firmware", fw_lme); lme_coldreset(udev); return -ENODEV; } - release_firmware(fw); - return ret; } @@ -1220,5 +1222,5 @@ module_exit(lme2510_module_exit); MODULE_AUTHOR("Malcolm Priestley "); MODULE_DESCRIPTION("LME2510(C) DVB-S USB2.0"); -MODULE_VERSION("1.80"); +MODULE_VERSION("1.81"); MODULE_LICENSE("GPL"); -- cgit v1.2.3-18-g5258 From e0df5417acf65cff05343b1fb83fb40344e155ea Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 28 Mar 2011 11:53:30 -0300 Subject: [media] xc5000: Improve it to work better with 6MHz-spaced channels Brazil uses 6MHz-spaced channels. So, the nyquist filter for DVB-C should be different, otherwise, inter-channel interference may badly affect the device, and signal may not be properly decoded. On my tests here, without this patch, sometimes channels are seen, but, most of the time, PID filter returns with timeout. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/xc5000.c | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/media/common/tuners/xc5000.c b/drivers/media/common/tuners/xc5000.c index 1e28f7dcb26..aa1b2e844d3 100644 --- a/drivers/media/common/tuners/xc5000.c +++ b/drivers/media/common/tuners/xc5000.c @@ -628,6 +628,15 @@ static void xc_debug_dump(struct xc5000_priv *priv) dprintk(1, "*** Quality (0:<8dB, 7:>56dB) = %d\n", quality); } +/* + * As defined on EN 300 429, the DVB-C roll-off factor is 0.15. + * So, the amount of the needed bandwith is given by: + * Bw = Symbol_rate * (1 + 0.15) + * As such, the maximum symbol rate supported by 6 MHz is given by: + * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds + */ +#define MAX_SYMBOL_RATE_6MHz 5217391 + static int xc5000_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) { @@ -688,21 +697,32 @@ static int xc5000_set_params(struct dvb_frontend *fe, } priv->rf_mode = XC_RF_MODE_AIR; } else if (fe->ops.info.type == FE_QAM) { - dprintk(1, "%s() QAM\n", __func__); switch (params->u.qam.modulation) { + case QAM_256: + case QAM_AUTO: case QAM_16: case QAM_32: case QAM_64: case QAM_128: - case QAM_256: - case QAM_AUTO: dprintk(1, "%s() QAM modulation\n", __func__); - priv->bandwidth = BANDWIDTH_8_MHZ; - priv->video_standard = DTV7_8; - priv->freq_hz = params->frequency - 2750000; priv->rf_mode = XC_RF_MODE_CABLE; + /* + * Using a 8MHz bandwidth sometimes fail + * with 6MHz-spaced channels, due to inter-carrier + * interference. So, use DTV6 firmware + */ + if (params->u.qam.symbol_rate <= MAX_SYMBOL_RATE_6MHz) { + priv->bandwidth = BANDWIDTH_6_MHZ; + priv->video_standard = DTV6; + priv->freq_hz = params->frequency - 1750000; + } else { + priv->bandwidth = BANDWIDTH_8_MHZ; + priv->video_standard = DTV7_8; + priv->freq_hz = params->frequency - 2750000; + } break; default: + dprintk(1, "%s() Unsupported QAM type\n", __func__); return -EINVAL; } } else { -- cgit v1.2.3-18-g5258 From abd34d8d6b213c792c1a06fd75488595c5fb6d3f Mon Sep 17 00:00:00 2001 From: Bjørn Mork Date: Mon, 21 Mar 2011 11:35:56 -0300 Subject: [media] use pci_dev->revision MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit pci_setup_device() has saved the PCI revision in the pci_dev struct since Linux 2.6.23. Use it. Cc: Auke Kok Signed-off-by: Bjørn Mork Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/saa7146_core.c | 7 +------ drivers/media/dvb/b2c2/flexcop-pci.c | 4 +--- drivers/media/dvb/bt8xx/bt878.c | 2 +- drivers/media/dvb/mantis/mantis_pci.c | 5 ++--- drivers/media/video/bt8xx/bttv-driver.c | 2 +- drivers/media/video/cx18/cx18-driver.c | 2 +- drivers/media/video/cx23885/cx23885-core.c | 2 +- drivers/media/video/cx88/cx88-mpeg.c | 2 +- drivers/media/video/cx88/cx88-video.c | 2 +- drivers/media/video/ivtv/ivtv-driver.c | 4 +--- drivers/media/video/saa7134/saa7134-core.c | 2 +- drivers/media/video/saa7164/saa7164-core.c | 2 +- drivers/media/video/zoran/zoran_card.c | 2 +- 13 files changed, 14 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/media/common/saa7146_core.c b/drivers/media/common/saa7146_core.c index 9f47e383c57..9af2140b57a 100644 --- a/drivers/media/common/saa7146_core.c +++ b/drivers/media/common/saa7146_core.c @@ -378,12 +378,7 @@ static int saa7146_init_one(struct pci_dev *pci, const struct pci_device_id *ent dev->pci = pci; /* get chip-revision; this is needed to enable bug-fixes */ - err = pci_read_config_dword(pci, PCI_CLASS_REVISION, &dev->revision); - if (err < 0) { - ERR(("pci_read_config_dword() failed.\n")); - goto err_disable; - } - dev->revision &= 0xf; + dev->revision = pci->revision; /* remap the memory from virtual to physical address */ diff --git a/drivers/media/dvb/b2c2/flexcop-pci.c b/drivers/media/dvb/b2c2/flexcop-pci.c index 03f96d6ca89..44f8fb5f17f 100644 --- a/drivers/media/dvb/b2c2/flexcop-pci.c +++ b/drivers/media/dvb/b2c2/flexcop-pci.c @@ -290,10 +290,8 @@ static void flexcop_pci_dma_exit(struct flexcop_pci *fc_pci) static int flexcop_pci_init(struct flexcop_pci *fc_pci) { int ret; - u8 card_rev; - pci_read_config_byte(fc_pci->pdev, PCI_CLASS_REVISION, &card_rev); - info("card revision %x", card_rev); + info("card revision %x", fc_pci->pdev->revision); if ((ret = pci_enable_device(fc_pci->pdev)) != 0) return ret; diff --git a/drivers/media/dvb/bt8xx/bt878.c b/drivers/media/dvb/bt8xx/bt878.c index 99d62094f90..b34fa95185e 100644 --- a/drivers/media/dvb/bt8xx/bt878.c +++ b/drivers/media/dvb/bt8xx/bt878.c @@ -460,7 +460,7 @@ static int __devinit bt878_probe(struct pci_dev *dev, goto fail0; } - pci_read_config_byte(dev, PCI_CLASS_REVISION, &bt->revision); + bt->revision = dev->revision; pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); diff --git a/drivers/media/dvb/mantis/mantis_pci.c b/drivers/media/dvb/mantis/mantis_pci.c index 10a432a79d0..371558af2d9 100644 --- a/drivers/media/dvb/mantis/mantis_pci.c +++ b/drivers/media/dvb/mantis/mantis_pci.c @@ -48,7 +48,7 @@ int __devinit mantis_pci_init(struct mantis_pci *mantis) { - u8 revision, latency; + u8 latency; struct mantis_hwconfig *config = mantis->hwconfig; struct pci_dev *pdev = mantis->pdev; int err, ret = 0; @@ -95,9 +95,8 @@ int __devinit mantis_pci_init(struct mantis_pci *mantis) } pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency); - pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision); mantis->latency = latency; - mantis->revision = revision; + mantis->revision = pdev->revision; dprintk(MANTIS_ERROR, 0, " Mantis Rev %d [%04x:%04x], ", mantis->revision, diff --git a/drivers/media/video/bt8xx/bttv-driver.c b/drivers/media/video/bt8xx/bttv-driver.c index 91399c94cd1..a97cf2750bd 100644 --- a/drivers/media/video/bt8xx/bttv-driver.c +++ b/drivers/media/video/bt8xx/bttv-driver.c @@ -4303,7 +4303,7 @@ static int __devinit bttv_probe(struct pci_dev *dev, goto fail0; } - pci_read_config_byte(dev, PCI_CLASS_REVISION, &btv->revision); + btv->revision = dev->revision; pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); printk(KERN_INFO "bttv%d: Bt%d (rev %d) at %s, ", bttv_num,btv->id, btv->revision, pci_name(dev)); diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c index 321c1b79794..841ea4ef620 100644 --- a/drivers/media/video/cx18/cx18-driver.c +++ b/drivers/media/video/cx18/cx18-driver.c @@ -818,7 +818,7 @@ static int cx18_setup_pci(struct cx18 *cx, struct pci_dev *pci_dev, cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config_word(pci_dev, PCI_COMMAND, cmd); - pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &cx->card_rev); + cx->card_rev = pci_dev->revision; pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &pci_latency); if (pci_latency < 64 && cx18_pci_latency) { diff --git a/drivers/media/video/cx23885/cx23885-core.c b/drivers/media/video/cx23885/cx23885-core.c index 9933810b4e3..64d9b2136ff 100644 --- a/drivers/media/video/cx23885/cx23885-core.c +++ b/drivers/media/video/cx23885/cx23885-core.c @@ -2045,7 +2045,7 @@ static int __devinit cx23885_initdev(struct pci_dev *pci_dev, } /* print pci info */ - pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); + dev->pci_rev = pci_dev->revision; pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, " "latency: %d, mmio: 0x%llx\n", dev->name, diff --git a/drivers/media/video/cx88/cx88-mpeg.c b/drivers/media/video/cx88/cx88-mpeg.c index addf9545e9b..9b500e691a5 100644 --- a/drivers/media/video/cx88/cx88-mpeg.c +++ b/drivers/media/video/cx88/cx88-mpeg.c @@ -474,7 +474,7 @@ static int cx8802_init_common(struct cx8802_dev *dev) return -EIO; } - pci_read_config_byte(dev->pci, PCI_CLASS_REVISION, &dev->pci_rev); + dev->pci_rev = dev->pci->revision; pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER, &dev->pci_lat); printk(KERN_INFO "%s/2: found at %s, rev: %d, irq: %d, " "latency: %d, mmio: 0x%llx\n", dev->core->name, diff --git a/drivers/media/video/cx88/cx88-video.c b/drivers/media/video/cx88/cx88-video.c index 287a41ee1c4..b1f734dccea 100644 --- a/drivers/media/video/cx88/cx88-video.c +++ b/drivers/media/video/cx88/cx88-video.c @@ -1832,7 +1832,7 @@ static int __devinit cx8800_initdev(struct pci_dev *pci_dev, dev->core = core; /* print pci info */ - pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); + dev->pci_rev = pci_dev->revision; pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, " "latency: %d, mmio: 0x%llx\n", core->name, diff --git a/drivers/media/video/ivtv/ivtv-driver.c b/drivers/media/video/ivtv/ivtv-driver.c index 39946420b30..a4e4dfdbc2f 100644 --- a/drivers/media/video/ivtv/ivtv-driver.c +++ b/drivers/media/video/ivtv/ivtv-driver.c @@ -810,7 +810,6 @@ static int ivtv_setup_pci(struct ivtv *itv, struct pci_dev *pdev, const struct pci_device_id *pci_id) { u16 cmd; - u8 card_rev; unsigned char pci_latency; IVTV_DEBUG_INFO("Enabling pci device\n"); @@ -857,7 +856,6 @@ static int ivtv_setup_pci(struct ivtv *itv, struct pci_dev *pdev, } IVTV_DEBUG_INFO("Bus Mastering Enabled.\n"); - pci_read_config_byte(pdev, PCI_CLASS_REVISION, &card_rev); pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency); if (pci_latency < 64 && ivtv_pci_latency) { @@ -874,7 +872,7 @@ static int ivtv_setup_pci(struct ivtv *itv, struct pci_dev *pdev, IVTV_DEBUG_INFO("%d (rev %d) at %02x:%02x.%x, " "irq: %d, latency: %d, memory: 0x%lx\n", - pdev->device, card_rev, pdev->bus->number, + pdev->device, pdev->revision, pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), pdev->irq, pci_latency, (unsigned long)itv->base_addr); diff --git a/drivers/media/video/saa7134/saa7134-core.c b/drivers/media/video/saa7134/saa7134-core.c index 41f836fc93e..f9be737ba6f 100644 --- a/drivers/media/video/saa7134/saa7134-core.c +++ b/drivers/media/video/saa7134/saa7134-core.c @@ -927,7 +927,7 @@ static int __devinit saa7134_initdev(struct pci_dev *pci_dev, } /* print pci info */ - pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); + dev->pci_rev = pci_dev->revision; pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); printk(KERN_INFO "%s: found at %s, rev: %d, irq: %d, " "latency: %d, mmio: 0x%llx\n", dev->name, diff --git a/drivers/media/video/saa7164/saa7164-core.c b/drivers/media/video/saa7164/saa7164-core.c index b813aec1e45..3b7d7b4e303 100644 --- a/drivers/media/video/saa7164/saa7164-core.c +++ b/drivers/media/video/saa7164/saa7164-core.c @@ -1247,7 +1247,7 @@ static int __devinit saa7164_initdev(struct pci_dev *pci_dev, } /* print pci info */ - pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); + dev->pci_rev = pci_dev->revision; pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, " "latency: %d, mmio: 0x%llx\n", dev->name, diff --git a/drivers/media/video/zoran/zoran_card.c b/drivers/media/video/zoran/zoran_card.c index 9f2bac51964..ba6878b2d66 100644 --- a/drivers/media/video/zoran/zoran_card.c +++ b/drivers/media/video/zoran/zoran_card.c @@ -1230,7 +1230,7 @@ static int __devinit zoran_probe(struct pci_dev *pdev, mutex_init(&zr->other_lock); if (pci_enable_device(pdev)) goto zr_unreg; - pci_read_config_byte(zr->pci_dev, PCI_CLASS_REVISION, &zr->revision); + zr->revision = zr->pci_dev->revision; dprintk(1, KERN_INFO -- cgit v1.2.3-18-g5258 From 0618ece01fdedcd3e775d9d43acc2c2a661a0c54 Mon Sep 17 00:00:00 2001 From: Bjørn Mork Date: Tue, 22 Mar 2011 10:22:17 -0300 Subject: [media] mantis: trivial module parameter documentation fix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The default for "verbose" is 0. Update description to match. Signed-off-by: Bjørn Mork Acked-by: Manu Abraham Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb/mantis/hopper_cards.c | 2 +- drivers/media/dvb/mantis/mantis_cards.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/media/dvb/mantis/hopper_cards.c b/drivers/media/dvb/mantis/hopper_cards.c index 70e73afefb3..1402062f2c8 100644 --- a/drivers/media/dvb/mantis/hopper_cards.c +++ b/drivers/media/dvb/mantis/hopper_cards.c @@ -44,7 +44,7 @@ static unsigned int verbose; module_param(verbose, int, 0644); -MODULE_PARM_DESC(verbose, "verbose startup messages, default is 1 (yes)"); +MODULE_PARM_DESC(verbose, "verbose startup messages, default is 0 (no)"); #define DRIVER_NAME "Hopper" diff --git a/drivers/media/dvb/mantis/mantis_cards.c b/drivers/media/dvb/mantis/mantis_cards.c index 40da225098c..05cbb9d9572 100644 --- a/drivers/media/dvb/mantis/mantis_cards.c +++ b/drivers/media/dvb/mantis/mantis_cards.c @@ -52,7 +52,7 @@ static unsigned int verbose; module_param(verbose, int, 0644); -MODULE_PARM_DESC(verbose, "verbose startup messages, default is 1 (yes)"); +MODULE_PARM_DESC(verbose, "verbose startup messages, default is 0 (no)"); static int devs; -- cgit v1.2.3-18-g5258 From 126f1e61887085aa2c2cfa7644aee8295a94e1f7 Mon Sep 17 00:00:00 2001 From: Ralph Metzler Date: Sat, 12 Mar 2011 23:44:33 -0500 Subject: drx: add initial drx-d driver These are the original drx-d sources, extracted from Ralph Metzler's GPL'd ngene driver. No modifications/cleanup have yet been made. In fact, no measures have been taken to see if the code even compiles. Signed-off-by Ralph Metzler Signed-off-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb/frontends/drxd.h | 57 + drivers/media/dvb/frontends/drxd_firm.c | 943 ++ drivers/media/dvb/frontends/drxd_firm.h | 120 + drivers/media/dvb/frontends/drxd_hard.c | 2831 +++++ drivers/media/dvb/frontends/drxd_map_firm.h | 14484 ++++++++++++++++++++++++++ drivers/media/dvb/frontends/drxd_micro.h | 1498 +++ 6 files changed, 19933 insertions(+) create mode 100644 drivers/media/dvb/frontends/drxd.h create mode 100644 drivers/media/dvb/frontends/drxd_firm.c create mode 100644 drivers/media/dvb/frontends/drxd_firm.h create mode 100644 drivers/media/dvb/frontends/drxd_hard.c create mode 100644 drivers/media/dvb/frontends/drxd_map_firm.h create mode 100644 drivers/media/dvb/frontends/drxd_micro.h (limited to 'drivers') diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h new file mode 100644 index 00000000000..9b11dc835c4 --- /dev/null +++ b/drivers/media/dvb/frontends/drxd.h @@ -0,0 +1,57 @@ +/* + * drxd.h: DRXD DVB-T demodulator driver + * + * Copyright (C) 2005-2007 Micronas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _DRXD_H_ +#define _DRXD_H_ + +#include +#include + +struct drxd_config +{ + u8 index; + + u8 pll_address; + u8 pll_type; +#define DRXD_PLL_NONE 0 +#define DRXD_PLL_DTT7520X 1 +#define DRXD_PLL_MT3X0823 2 + + u32 clock; + + u8 demod_address; + u8 demoda_address; + u8 demod_revision; + + u32 IF; + int (*pll_set) (void *priv, void *priv_params, + u8 pll_addr, u8 demoda_addr, s32 *off); + s16 (*osc_deviation) (void *priv, s16 dev, int flag); +}; + +extern +struct dvb_frontend *drxd_attach(const struct drxd_config *config, + void *priv, struct i2c_adapter *i2c, + struct device *dev); +extern int drxd_config_i2c(struct dvb_frontend *, int); +#endif diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c new file mode 100644 index 00000000000..b27e928b94c --- /dev/null +++ b/drivers/media/dvb/frontends/drxd_firm.c @@ -0,0 +1,943 @@ +/* + * drxd_firm.c : DRXD firmware tables + * + * Copyright (C) 2006-2007 Micronas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +/* TODO: generate this file with a script from a settings file */ + +/* Contains A2 firmware version: 1.4.2 + * Contains B1 firmware version: 3.3.33 + * Contains settings from driver 1.4.23 +*/ + +#include "drxd_firm.h" + +#define ADDRESS(x) ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF) +#define LENGTH(x) ((x) & 0xFF), (((x)>>8) & 0xFF) + +/* Is written via block write, must be little endian */ +#define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF) + +#define WRBLOCK(a,l) ADDRESS(a),LENGTH(l) +#define WR16(a,d) ADDRESS(a),LENGTH(1),DATA16(d) + +#define END_OF_TABLE 0xFF,0xFF,0xFF,0xFF + +/* HI firmware patches */ + +#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A +#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */ + +u8_t DRXD_InitAtomicRead[] = +{ + WRBLOCK(HI_TR_FUNC_ADDR,HI_TR_FUNC_SIZE), + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x60, 0x04, /* r0rami.dt -> ring.xba; */ + 0x61, 0x04, /* r0rami.dt -> ring.xad; */ + 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */ + 0x40, 0x00, /* (long immediate) */ + 0x64, 0x04, /* r0rami.dt -> ring.len; */ + 0x65, 0x04, /* r0rami.dt -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x38, 0x00, /* 0 -> jumps.ad; */ + END_OF_TABLE +}; + +/* Pins D0 and D1 of the parallel MPEG output can be used + to set the I2C address of a device. */ + +#define HI_RST_FUNC_ADDR ( HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE) +#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */ + +/* D0 Version */ +u8_t DRXD_HiI2cPatch_1[] = +{ + WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE), + 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */ + 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x24, 0x00, /* 0 -> ring.len; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ + 0x63, 0x00, /* &data+1 -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0x0F, 0x04, /* r0ram.dt -> and.op; */ + 0x1C, 0x06, /* reg0.dt -> and.tr; */ + 0xCF, 0x04, /* and.rs -> add.op; */ + 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ + 0xD0, 0x04, /* add.rs -> add.tr; */ + 0xC8, 0x04, /* add.rs -> reg0.dt; */ + 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ + 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ + + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + + /* Force quick and dirty reset */ + WR16(B_HI_CT_REG_COMM_STATE__A,0), + END_OF_TABLE +}; + +/* D0,D1 Version */ +u8_t DRXD_HiI2cPatch_3[] = +{ + WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE), + 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */ + 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x24, 0x00, /* 0 -> ring.len; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ + 0x63, 0x00, /* &data+1 -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0x0F, 0x04, /* r0ram.dt -> and.op; */ + 0x1C, 0x06, /* reg0.dt -> and.tr; */ + 0xCF, 0x04, /* and.rs -> add.op; */ + 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ + 0xD0, 0x04, /* add.rs -> add.tr; */ + 0xC8, 0x04, /* add.rs -> reg0.dt; */ + 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ + 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ + + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + + /* Force quick and dirty reset */ + WR16(B_HI_CT_REG_COMM_STATE__A,0), + END_OF_TABLE +}; + +u8_t DRXD_ResetCEFR[] = +{ + WRBLOCK(CE_REG_FR_TREAL00__A, 57), + 0x52,0x00, /* CE_REG_FR_TREAL00__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG00__A */ + 0x52,0x00, /* CE_REG_FR_TREAL01__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG01__A */ + 0x52,0x00, /* CE_REG_FR_TREAL02__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG02__A */ + 0x52,0x00, /* CE_REG_FR_TREAL03__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG03__A */ + 0x52,0x00, /* CE_REG_FR_TREAL04__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG04__A */ + 0x52,0x00, /* CE_REG_FR_TREAL05__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG05__A */ + 0x52,0x00, /* CE_REG_FR_TREAL06__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG06__A */ + 0x52,0x00, /* CE_REG_FR_TREAL07__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG07__A */ + 0x52,0x00, /* CE_REG_FR_TREAL08__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG08__A */ + 0x52,0x00, /* CE_REG_FR_TREAL09__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG09__A */ + 0x52,0x00, /* CE_REG_FR_TREAL10__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG10__A */ + 0x52,0x00, /* CE_REG_FR_TREAL11__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG11__A */ + + 0x52,0x00, /* CE_REG_FR_MID_TAP__A */ + + 0x0B,0x00, /* CE_REG_FR_SQS_G00__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G01__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G02__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G03__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G04__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G05__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G06__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G07__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G08__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G09__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G10__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G11__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G12__A */ + + 0xFF,0x01, /* CE_REG_FR_RIO_G00__A */ + 0x90,0x01, /* CE_REG_FR_RIO_G01__A */ + 0x0B,0x01, /* CE_REG_FR_RIO_G02__A */ + 0xC8,0x00, /* CE_REG_FR_RIO_G03__A */ + 0xA0,0x00, /* CE_REG_FR_RIO_G04__A */ + 0x85,0x00, /* CE_REG_FR_RIO_G05__A */ + 0x72,0x00, /* CE_REG_FR_RIO_G06__A */ + 0x64,0x00, /* CE_REG_FR_RIO_G07__A */ + 0x59,0x00, /* CE_REG_FR_RIO_G08__A */ + 0x50,0x00, /* CE_REG_FR_RIO_G09__A */ + 0x49,0x00, /* CE_REG_FR_RIO_G10__A */ + + 0x10,0x00, /* CE_REG_FR_MODE__A */ + 0x78,0x00, /* CE_REG_FR_SQS_TRH__A */ + 0x00,0x00, /* CE_REG_FR_RIO_GAIN__A */ + 0x00,0x02, /* CE_REG_FR_BYPASS__A */ + 0x0D,0x00, /* CE_REG_FR_PM_SET__A */ + 0x07,0x00, /* CE_REG_FR_ERR_SH__A */ + 0x04,0x00, /* CE_REG_FR_MAN_SH__A */ + 0x06,0x00, /* CE_REG_FR_TAP_SH__A */ + + END_OF_TABLE +}; + + +u8_t DRXD_InitFEA2_1[] = +{ + WRBLOCK(FE_AD_REG_PD__A , 3), + 0x00,0x00, /* FE_AD_REG_PD__A */ + 0x01,0x00, /* FE_AD_REG_INVEXT__A */ + 0x00,0x00, /* FE_AD_REG_CLKNEG__A */ + + WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A , 2), + 0x10,0x00, /* FE_AG_REG_DCE_AUR_CNT__A */ + 0x10,0x00, /* FE_AG_REG_DCE_RUR_CNT__A */ + + WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A , 2), + 0x0E,0x00, /* FE_AG_REG_ACE_AUR_CNT__A */ + 0x00,0x00, /* FE_AG_REG_ACE_RUR_CNT__A */ + + WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A , 5), + 0x04,0x00, /* FE_AG_REG_EGC_FLA_RGN__A */ + 0x1F,0x00, /* FE_AG_REG_EGC_SLO_RGN__A */ + 0x00,0x00, /* FE_AG_REG_EGC_JMP_PSN__A */ + 0x00,0x00, /* FE_AG_REG_EGC_FLA_INC__A */ + 0x00,0x00, /* FE_AG_REG_EGC_FLA_DEC__A */ + + WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A , 2), + 0xFF,0x01, /* FE_AG_REG_GC1_AGC_MAX__A */ + 0x00,0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */ + + WRBLOCK(FE_AG_REG_IND_WIN__A , 29), + 0x00,0x00, /* FE_AG_REG_IND_WIN__A */ + 0x05,0x00, /* FE_AG_REG_IND_THD_LOL__A */ + 0x0F,0x00, /* FE_AG_REG_IND_THD_HIL__A */ + 0x00,0x00, /* FE_AG_REG_IND_DEL__A don't care */ + 0x1E,0x00, /* FE_AG_REG_IND_PD1_WRI__A */ + 0x0C,0x00, /* FE_AG_REG_PDA_AUR_CNT__A */ + 0x00,0x00, /* FE_AG_REG_PDA_RUR_CNT__A */ + 0x00,0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */ + 0x00,0x00, /* FE_AG_REG_PDC_RUR_CNT__A */ + 0x01,0x00, /* FE_AG_REG_PDC_SET_LVL__A */ + 0x02,0x00, /* FE_AG_REG_PDC_FLA_RGN__A */ + 0x00,0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */ + 0xFF,0xFF, /* FE_AG_REG_PDC_FLA_STP__A */ + 0xFF,0xFF, /* FE_AG_REG_PDC_SLO_STP__A */ + 0x00,0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */ + 0x00,0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */ + 0x02,0x00, /* FE_AG_REG_PDC_MAX__A */ + 0x0C,0x00, /* FE_AG_REG_TGA_AUR_CNT__A */ + 0x00,0x00, /* FE_AG_REG_TGA_RUR_CNT__A */ + 0x00,0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */ + 0x00,0x00, /* FE_AG_REG_TGC_RUR_CNT__A */ + 0x22,0x00, /* FE_AG_REG_TGC_SET_LVL__A */ + 0x15,0x00, /* FE_AG_REG_TGC_FLA_RGN__A */ + 0x00,0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */ + 0x01,0x00, /* FE_AG_REG_TGC_FLA_STP__A */ + 0x0A,0x00, /* FE_AG_REG_TGC_SLO_STP__A */ + 0x00,0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */ + 0x10,0x00, /* FE_AG_REG_FGA_AUR_CNT__A */ + 0x10,0x00, /* FE_AG_REG_FGA_RUR_CNT__A */ + + WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A , 2), + 0x00,0x00, /* FE_AG_REG_BGC_FGC_WRI__A */ + 0x00,0x00, /* FE_AG_REG_BGC_CGC_WRI__A */ + + WRBLOCK(FE_FD_REG_SCL__A , 3), + 0x05,0x00, /* FE_FD_REG_SCL__A */ + 0x03,0x00, /* FE_FD_REG_MAX_LEV__A */ + 0x05,0x00, /* FE_FD_REG_NR__A */ + + WRBLOCK(FE_CF_REG_SCL__A , 5), + 0x16,0x00, /* FE_CF_REG_SCL__A */ + 0x04,0x00, /* FE_CF_REG_MAX_LEV__A */ + 0x06,0x00, /* FE_CF_REG_NR__A */ + 0x00,0x00, /* FE_CF_REG_IMP_VAL__A */ + 0x01,0x00, /* FE_CF_REG_MEAS_VAL__A */ + + WRBLOCK(FE_CU_REG_FRM_CNT_RST__A , 2), + 0x00,0x08, /* FE_CU_REG_FRM_CNT_RST__A */ + 0x00,0x00, /* FE_CU_REG_FRM_CNT_STR__A */ + + END_OF_TABLE +}; + + /* with PGA */ +/* WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0004), */ + /* without PGA */ +/* WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0001), */ +/* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/ +/* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ + +u8_t DRXD_InitFEA2_2[] = +{ + WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010), + WR16(FE_AG_REG_FGM_WRI__A , 48), + /* Activate measurement, activate scale */ + WR16(FE_FD_REG_MEAS_VAL__A , 0x0001), + + WR16(FE_CU_REG_COMM_EXEC__A, 0x0001), + WR16(FE_CF_REG_COMM_EXEC__A, 0x0001), + WR16(FE_IF_REG_COMM_EXEC__A, 0x0001), + WR16(FE_FD_REG_COMM_EXEC__A, 0x0001), + WR16(FE_FS_REG_COMM_EXEC__A, 0x0001), + WR16(FE_AD_REG_COMM_EXEC__A , 0x0001), + WR16(FE_AG_REG_COMM_EXEC__A , 0x0001), + WR16(FE_AG_REG_AG_MODE_LOP__A , 0x895E), + + END_OF_TABLE +}; + +u8_t DRXD_InitFEB1_1[] = +{ + WR16(B_FE_AD_REG_PD__A ,0x0000 ), + WR16(B_FE_AD_REG_CLKNEG__A ,0x0000 ), + WR16(B_FE_AG_REG_BGC_FGC_WRI__A ,0x0000 ), + WR16(B_FE_AG_REG_BGC_CGC_WRI__A ,0x0000 ), + WR16(B_FE_AG_REG_AG_MODE_LOP__A ,0x000a ), + WR16(B_FE_AG_REG_IND_PD1_WRI__A ,35 ), + WR16(B_FE_AG_REG_IND_WIN__A ,0 ), + WR16(B_FE_AG_REG_IND_THD_LOL__A ,8 ), + WR16(B_FE_AG_REG_IND_THD_HIL__A ,8 ), + WR16(B_FE_CF_REG_IMP_VAL__A ,1 ), + WR16(B_FE_AG_REG_EGC_FLA_RGN__A ,7 ), + END_OF_TABLE +}; + /* with PGA */ +/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */ + /* without PGA */ +/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , + B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/ +/* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005*/ +/* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ + +u8_t DRXD_InitFEB1_2[] = +{ + WR16(B_FE_COMM_EXEC__A ,0x0001 ), + + /* RF-AGC setup */ + WR16(B_FE_AG_REG_PDA_AUR_CNT__A , 0x0C ), + WR16(B_FE_AG_REG_PDC_SET_LVL__A , 0x01 ), + WR16(B_FE_AG_REG_PDC_FLA_RGN__A , 0x02 ), + WR16(B_FE_AG_REG_PDC_FLA_STP__A , 0xFFFF ), + WR16(B_FE_AG_REG_PDC_SLO_STP__A , 0xFFFF ), + WR16(B_FE_AG_REG_PDC_MAX__A , 0x02 ), + WR16(B_FE_AG_REG_TGA_AUR_CNT__A , 0x0C ), + WR16(B_FE_AG_REG_TGC_SET_LVL__A , 0x22 ), + WR16(B_FE_AG_REG_TGC_FLA_RGN__A , 0x15 ), + WR16(B_FE_AG_REG_TGC_FLA_STP__A , 0x01 ), + WR16(B_FE_AG_REG_TGC_SLO_STP__A , 0x0A ), + + WR16(B_FE_CU_REG_DIV_NFC_CLP__A , 0 ), + WR16(B_FE_CU_REG_CTR_NFC_OCR__A , 25000 ), + WR16(B_FE_CU_REG_CTR_NFC_ICR__A , 1 ), + END_OF_TABLE +}; + +u8_t DRXD_InitCPA2[] = +{ + WRBLOCK(CP_REG_BR_SPL_OFFSET__A , 2), + 0x07,0x00, /* CP_REG_BR_SPL_OFFSET__A */ + 0x0A,0x00, /* CP_REG_BR_STR_DEL__A */ + + WRBLOCK(CP_REG_RT_ANG_INC0__A , 4), + 0x00,0x00, /* CP_REG_RT_ANG_INC0__A */ + 0x00,0x00, /* CP_REG_RT_ANG_INC1__A */ + 0x03,0x00, /* CP_REG_RT_DETECT_ENA__A */ + 0x03,0x00, /* CP_REG_RT_DETECT_TRH__A */ + + WRBLOCK(CP_REG_AC_NEXP_OFFS__A , 5), + 0x32,0x00, /* CP_REG_AC_NEXP_OFFS__A */ + 0x62,0x00, /* CP_REG_AC_AVER_POW__A */ + 0x82,0x00, /* CP_REG_AC_MAX_POW__A */ + 0x26,0x00, /* CP_REG_AC_WEIGHT_MAN__A */ + 0x0F,0x00, /* CP_REG_AC_WEIGHT_EXP__A */ + + WRBLOCK(CP_REG_AC_AMP_MODE__A ,2), + 0x02,0x00, /* CP_REG_AC_AMP_MODE__A */ + 0x01,0x00, /* CP_REG_AC_AMP_FIX__A */ + + WR16(CP_REG_INTERVAL__A , 0x0005 ), + WR16(CP_REG_RT_EXP_MARG__A , 0x0004 ), + WR16(CP_REG_AC_ANG_MODE__A , 0x0003 ), + + WR16(CP_REG_COMM_EXEC__A , 0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_InitCPB1[] = +{ + WR16(B_CP_REG_BR_SPL_OFFSET__A ,0x0008 ), + WR16(B_CP_COMM_EXEC__A ,0x0001 ), + END_OF_TABLE +}; + + +u8_t DRXD_InitCEA2[] = +{ + WRBLOCK(CE_REG_AVG_POW__A , 4), + 0x62,0x00, /* CE_REG_AVG_POW__A */ + 0x78,0x00, /* CE_REG_MAX_POW__A */ + 0x62,0x00, /* CE_REG_ATT__A */ + 0x17,0x00, /* CE_REG_NRED__A */ + + WRBLOCK(CE_REG_NE_ERR_SELECT__A , 2), + 0x07,0x00, /* CE_REG_NE_ERR_SELECT__A */ + 0xEB,0xFF, /* CE_REG_NE_TD_CAL__A */ + + WRBLOCK(CE_REG_NE_MIXAVG__A , 2), + 0x06,0x00, /* CE_REG_NE_MIXAVG__A */ + 0x00,0x00, /* CE_REG_NE_NUPD_OFS__A */ + + WRBLOCK(CE_REG_PE_NEXP_OFFS__A , 2), + 0x00,0x00, /* CE_REG_PE_NEXP_OFFS__A */ + 0x00,0x00, /* CE_REG_PE_TIMESHIFT__A */ + + WRBLOCK(CE_REG_TP_A0_TAP_NEW__A , 3), + 0x00,0x01, /* CE_REG_TP_A0_TAP_NEW__A */ + 0x01,0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */ + 0x0E,0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */ + + WRBLOCK(CE_REG_TP_A1_TAP_NEW__A , 3), + 0x00,0x00, /* CE_REG_TP_A1_TAP_NEW__A */ + 0x01,0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */ + 0x0A,0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */ + + WRBLOCK(CE_REG_FI_SHT_INCR__A , 2), + 0x12,0x00, /* CE_REG_FI_SHT_INCR__A */ + 0x0C,0x00, /* CE_REG_FI_EXP_NORM__A */ + + WRBLOCK(CE_REG_IR_INPUTSEL__A , 3), + 0x00,0x00, /* CE_REG_IR_INPUTSEL__A */ + 0x00,0x00, /* CE_REG_IR_STARTPOS__A */ + 0xFF,0x00, /* CE_REG_IR_NEXP_THRES__A */ + + + WR16(CE_REG_TI_NEXP_OFFS__A ,0x0000), + + END_OF_TABLE +}; + +u8_t DRXD_InitCEB1[] = +{ + WR16(B_CE_REG_TI_PHN_ENABLE__A ,0x0001), + WR16(B_CE_REG_FR_PM_SET__A ,0x000D), + + END_OF_TABLE +}; + +u8_t DRXD_InitEQA2[] = +{ + WRBLOCK(EQ_REG_OT_QNT_THRES0__A , 4), + 0x1E,0x00, /* EQ_REG_OT_QNT_THRES0__A */ + 0x1F,0x00, /* EQ_REG_OT_QNT_THRES1__A */ + 0x06,0x00, /* EQ_REG_OT_CSI_STEP__A */ + 0x02,0x00, /* EQ_REG_OT_CSI_OFFSET__A */ + + WR16(EQ_REG_TD_REQ_SMB_CNT__A ,0x0200 ), + WR16(EQ_REG_IS_CLIP_EXP__A ,0x001F ), + WR16(EQ_REG_SN_OFFSET__A ,(u16_t)(-7) ), + WR16(EQ_REG_RC_SEL_CAR__A ,0x0002 ), + WR16(EQ_REG_COMM_EXEC__A ,0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_InitEQB1[] = +{ + WR16(B_EQ_REG_COMM_EXEC__A ,0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_ResetECRAM[] = +{ + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A , 0x0000 ), + WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), + END_OF_TABLE +}; + +u8_t DRXD_InitECA2[] = +{ + WRBLOCK( EC_SB_REG_CSI_HI__A , 6), + 0x1F,0x00, /* EC_SB_REG_CSI_HI__A */ + 0x1E,0x00, /* EC_SB_REG_CSI_LO__A */ + 0x01,0x00, /* EC_SB_REG_SMB_TGL__A */ + 0x7F,0x00, /* EC_SB_REG_SNR_HI__A */ + 0x7F,0x00, /* EC_SB_REG_SNR_MID__A */ + 0x7F,0x00, /* EC_SB_REG_SNR_LO__A */ + + WRBLOCK( EC_RS_REG_REQ_PCK_CNT__A , 2), + 0x00,0x10, /* EC_RS_REG_REQ_PCK_CNT__A */ + DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */ + + WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5), + 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ + 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ + 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ + 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ + 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ + + WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2), + 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ + 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ + + WRBLOCK( EC_OC_REG_RCN_MODE__A , 7), + 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */ + 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ + 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ + 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */ + 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */ + 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */ + 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ + + WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2), + 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ + 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ + + WR16(EC_SB_REG_CSI_OFS__A , 0x0001 ), + WR16(EC_VD_REG_FORCE__A , 0x0002 ), + WR16(EC_VD_REG_REQ_SMB_CNT__A , 0x0001 ), + WR16(EC_VD_REG_RLK_ENA__A , 0x0001 ), + WR16(EC_OD_REG_SYNC__A , 0x0664 ), + WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ), + WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ), + /* Output zero on monitorbus pads, power saving */ + WR16(EC_OC_REG_OCR_MON_UOS__A , + ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | + EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | + EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ), + WR16(EC_OC_REG_OCR_MON_WRI__A, + EC_OC_REG_OCR_MON_WRI_INIT ), + +/* CHK_ERROR(ResetECRAM(demod)); */ + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A , 0x0000 ), + WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), + + WR16(EC_SB_REG_COMM_EXEC__A , 0x0001 ), + WR16(EC_VD_REG_COMM_EXEC__A , 0x0001 ), + WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ), + WR16(EC_RS_REG_COMM_EXEC__A , 0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_InitECB1[] = +{ + WR16(B_EC_SB_REG_CSI_OFS0__A ,0x0001 ), + WR16(B_EC_SB_REG_CSI_OFS1__A ,0x0001 ), + WR16(B_EC_SB_REG_CSI_OFS2__A ,0x0001 ), + WR16(B_EC_SB_REG_CSI_LO__A ,0x000c ), + WR16(B_EC_SB_REG_CSI_HI__A ,0x0018 ), + WR16(B_EC_SB_REG_SNR_HI__A ,0x007f ), + WR16(B_EC_SB_REG_SNR_MID__A ,0x007f ), + WR16(B_EC_SB_REG_SNR_LO__A ,0x007f ), + + WR16(B_EC_OC_REG_DTO_CLKMODE__A ,0x0002 ), + WR16(B_EC_OC_REG_DTO_PER__A ,0x0006 ), + WR16(B_EC_OC_REG_DTO_BUR__A ,0x0001 ), + WR16(B_EC_OC_REG_RCR_CLKMODE__A ,0x0000 ), + WR16(B_EC_OC_REG_RCN_GAI_LVL__A ,0x000D ), + WR16(B_EC_OC_REG_OC_MPG_SIO__A ,0x0000 ), + + /* Needed because shadow registers do not have correct default value */ + WR16(B_EC_OC_REG_RCN_CST_LOP__A ,0x1000 ), + WR16(B_EC_OC_REG_RCN_CST_HIP__A ,0x0000 ), + WR16(B_EC_OC_REG_RCN_CRA_LOP__A ,0x0000 ), + WR16(B_EC_OC_REG_RCN_CRA_HIP__A ,0x00C0 ), + WR16(B_EC_OC_REG_RCN_CLP_LOP__A ,0x0000 ), + WR16(B_EC_OC_REG_RCN_CLP_HIP__A ,0x00C0 ), + WR16(B_EC_OC_REG_DTO_INC_LOP__A ,0x0000 ), + WR16(B_EC_OC_REG_DTO_INC_HIP__A ,0x00C0 ), + + WR16(B_EC_OD_REG_SYNC__A ,0x0664 ), + WR16(B_EC_RS_REG_REQ_PCK_CNT__A ,0x1000 ), + +/* CHK_ERROR(ResetECRAM(demod)); */ + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A , 0x0000 ), + WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), + + WR16(B_EC_SB_REG_COMM_EXEC__A , 0x0001 ), + WR16(B_EC_VD_REG_COMM_EXEC__A , 0x0001 ), + WR16(B_EC_OD_REG_COMM_EXEC__A , 0x0001 ), + WR16(B_EC_RS_REG_COMM_EXEC__A , 0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_ResetECA2[] = +{ + + WR16(EC_OC_REG_COMM_EXEC__A , 0x0000 ), + WR16(EC_OD_REG_COMM_EXEC__A , 0x0000 ), + + WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5), + 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ + 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ + 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ + 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ + 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ + + WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2), + 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ + 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ + + WRBLOCK( EC_OC_REG_RCN_MODE__A , 7), + 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */ + 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ + 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ + 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */ + 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */ + 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */ + 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ + + WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2), + 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ + 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ + + WR16(EC_OD_REG_SYNC__A , 0x0664 ), + WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ), + WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ), + /* Output zero on monitorbus pads, power saving */ + WR16(EC_OC_REG_OCR_MON_UOS__A , + ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | + EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | + EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ), + WR16(EC_OC_REG_OCR_MON_WRI__A, + EC_OC_REG_OCR_MON_WRI_INIT ), + +/* CHK_ERROR(ResetECRAM(demod)); */ + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A , 0x0000 ), + WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), + + WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_InitSC[] = +{ + WR16(SC_COMM_EXEC__A, 0 ), + WR16(SC_COMM_STATE__A, 0 ), + +#ifdef COMPILE_FOR_QT + WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100 ), +#endif + + /* SC is not started, this is done in SetChannels() */ + END_OF_TABLE +}; + +/* Diversity settings */ + +u8_t DRXD_InitDiversityFront[] = +{ + /* Start demod ********* RF in , diversity out *****************************/ + WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | + B_SC_RA_RAM_CONFIG_FREQSCAN__M ), + + WR16( B_SC_RA_RAM_LC_ABS_2K__A, 0x7), + WR16( B_SC_RA_RAM_LC_ABS_8K__A, 0x7), + WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ), + WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ), + WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ), + WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ), + + WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ), + WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ), + WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ), + WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ), + + WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7), + WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4), + WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7), + WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4), + WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500), + + WR16( B_CC_REG_DIVERSITY__A, 0x0001 ), + WR16( B_EC_OC_REG_OC_MODE_HIP__A, 0x0010 ), + WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | + B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | + B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ), + + + /* 0x2a ),*/ /* CE to PASS mux */ + + END_OF_TABLE +}; + +u8_t DRXD_InitDiversityEnd[] = +{ + /* End demod *********** combining RF in and diversity in, MPEG TS out *****/ + /* disable near/far; switch on timing slave mode */ + WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | + B_SC_RA_RAM_CONFIG_FREQSCAN__M | + B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M | + B_SC_RA_RAM_CONFIG_SLAVE__M | + B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M +/* MV from CtrlDiversity */ + ), +#ifdef DRXDDIV_SRMM_SLAVING + WR16( SC_RA_RAM_LC_ABS_2K__A, 0x3c7), + WR16( SC_RA_RAM_LC_ABS_8K__A, 0x3c7), +#else + WR16( SC_RA_RAM_LC_ABS_2K__A, 0x7), + WR16( SC_RA_RAM_LC_ABS_8K__A, 0x7), +#endif + + WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ), + WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ), + WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ), + WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ), + + WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ), + WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ), + WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ), + WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ), + + WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7), + WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4), + WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7), + WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4), + WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500), + + WR16( B_CC_REG_DIVERSITY__A, 0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_DisableDiversity[] = +{ + WR16( B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE), + WR16( B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE), + WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE ), + + WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE ), + + WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE), + WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE), + WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE), + WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE), + WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE), + + + WR16( B_CC_REG_DIVERSITY__A, 0x0000 ), + WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT ), /* combining disabled*/ + + END_OF_TABLE +}; + +u8_t DRXD_StartDiversityFront[] = +{ + /* Start demod, RF in and diversity out, no combining */ + WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ), + WR16( B_FE_AD_REG_FDB_IN__A, 0x0 ), + WR16( B_FE_AD_REG_INVEXT__A, 0x0 ), + WR16( B_EQ_REG_COMM_MB__A, 0x12 ), /* EQ to MB out */ + WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */ + B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | + B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ), + + WR16( SC_RA_RAM_ECHO_SHIFT_LIM__A, 2 ), + + END_OF_TABLE +}; + +u8_t DRXD_StartDiversityEnd[] = +{ + /* End demod, combining RF in and diversity in, MPEG TS out */ + WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ), /* disable impulse noise cruncher */ + WR16( B_FE_AD_REG_INVEXT__A, 0x0 ), /* clock inversion (for sohard board) */ + WR16( B_CP_REG_BR_STR_DEL__A, 10 ), /* apperently no mb delay matching is best */ + + WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */ + B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | + B_EQ_REG_RC_SEL_CAR_PASS_A_CC | + B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC ), + + END_OF_TABLE +}; + +u8_t DRXD_DiversityDelay8MHZ[] = +{ + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 1000 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 800 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4800 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 4000 - 50 ), + END_OF_TABLE +}; + +u8_t DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */ +{ + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 900 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 600 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4500 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 3500 - 50 ), + END_OF_TABLE +}; + +#include "drxd_micro.h" diff --git a/drivers/media/dvb/frontends/drxd_firm.h b/drivers/media/dvb/frontends/drxd_firm.h new file mode 100644 index 00000000000..fa704cbf766 --- /dev/null +++ b/drivers/media/dvb/frontends/drxd_firm.h @@ -0,0 +1,120 @@ +/* + * drxd_firm.h + * + * Copyright (C) 2006-2007 Micronas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _DRXD_FIRM_H_ +#define _DRXD_FIRM_H_ + +#include "drxd_map_firm.h" + +typedef unsigned char u8_t; +typedef unsigned short u16_t; +typedef unsigned long u32_t; + +#define VERSION_MAJOR 1 +#define VERSION_MINOR 4 +#define VERSION_PATCH 23 + +#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A + +#define DRXD_MAX_RETRIES (1000) +#define HI_I2C_DELAY 84 +#define HI_I2C_BRIDGE_DELAY 750 + +#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */ +#define EQ_TD_TPS_PWR_QPSK 0x016a +#define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195 +#define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195 +#define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E +#define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE +#define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F +#define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F +#define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8 +#define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D + +#define DRXD_DEF_AG_PWD_CONSUMER 0x000E +#define DRXD_DEF_AG_PWD_PRO 0x0000 +#define DRXD_DEF_AG_AGC_SIO 0x0000 + +#define DRXD_FE_CTRL_MAX 1023 + +#define DRXD_OSCDEV_DO_SCAN (16) + +#define DRXD_OSCDEV_DONT_SCAN (0) + +#define DRXD_OSCDEV_STEP (275) + +#define DRXD_SCAN_TIMEOUT (650) + + +#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) +#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) +#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) + +#define IRLEN_COARSE_8K (10) +#define IRLEN_FINE_8K (10) +#define IRLEN_COARSE_2K (7) +#define IRLEN_FINE_2K (9) +#define DIFF_INVALID (511) +#define DIFF_TARGET (4) +#define DIFF_MARGIN (1) + + +extern u8_t DRXD_InitAtomicRead[]; +extern u8_t DRXD_HiI2cPatch_1[]; +extern u8_t DRXD_HiI2cPatch_3[]; + +extern u8_t DRXD_InitSC[]; + +extern u8_t DRXD_ResetCEFR[]; +extern u8_t DRXD_InitFEA2_1[]; +extern u8_t DRXD_InitFEA2_2[]; +extern u8_t DRXD_InitCPA2[]; +extern u8_t DRXD_InitCEA2[]; +extern u8_t DRXD_InitEQA2[]; +extern u8_t DRXD_InitECA2[]; +extern u8_t DRXD_ResetECA2[]; +extern u8_t DRXD_ResetECRAM[]; + +extern u8_t DRXD_A2_microcode[]; +extern u32_t DRXD_A2_microcode_length; + +extern u8_t DRXD_InitFEB1_1[]; +extern u8_t DRXD_InitFEB1_2[]; +extern u8_t DRXD_InitCPB1[]; +extern u8_t DRXD_InitCEB1[]; +extern u8_t DRXD_InitEQB1[]; +extern u8_t DRXD_InitECB1[]; + +extern u8_t DRXD_InitDiversityFront[]; +extern u8_t DRXD_InitDiversityEnd[]; +extern u8_t DRXD_DisableDiversity[]; +extern u8_t DRXD_StartDiversityFront[]; +extern u8_t DRXD_StartDiversityEnd[]; + +extern u8_t DRXD_DiversityDelay8MHZ[]; +extern u8_t DRXD_DiversityDelay6MHZ[]; + +extern u8_t DRXD_B1_microcode[]; +extern u32_t DRXD_B1_microcode_length; + +#endif diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c new file mode 100644 index 00000000000..c4835b32e6d --- /dev/null +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -0,0 +1,2831 @@ +/* + * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1 + * + * Copyright (C) 2003-2007 Micronas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include