From 6c01ba445cecb2d8085cf0b5a6ddfb170ad22616 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 10 Nov 2011 18:45:52 -0800 Subject: ARM: mach-shmobile: R-Mobile A1 support. This adds preliminary support for the R8A7740 (R-Mobile A1) CPU Timer, serial, gic, clock are supported at this point. This patch is based on v0.1 manual Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- drivers/tty/serial/sh-sci.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h index e9bed038aa1..a1a2d364f92 100644 --- a/drivers/tty/serial/sh-sci.h +++ b/drivers/tty/serial/sh-sci.h @@ -17,7 +17,9 @@ defined(CONFIG_ARCH_SH73A0) || \ defined(CONFIG_ARCH_SH7367) || \ defined(CONFIG_ARCH_SH7377) || \ - defined(CONFIG_ARCH_SH7372) + defined(CONFIG_ARCH_SH7372) || \ + defined(CONFIG_ARCH_R8A7740) + # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) -- cgit v1.2.3-18-g5258 From 92554d97c6dcc448afd56f96bbe933998868be74 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 14 Dec 2011 01:00:37 +0900 Subject: sh: pfc: Add gpio_read_bit() for data register access Introduce gpio_read_bit() for data register read access and modify sh_gpio_get_value() to make use of the new function instead of gpio_read_reg(). The purpose of this change is to update the code to only use the gpio_read_reg() function for config register access. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/sh/pfc.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c index e7d127a9c1c..cfca0aaf982 100644 --- a/drivers/sh/pfc.c +++ b/drivers/sh/pfc.c @@ -135,6 +135,19 @@ static void gpio_write_raw_reg(void __iomem *mapped_reg, BUG(); } +static int gpio_read_bit(struct pinmux_data_reg *dr, + unsigned long in_pos) +{ + unsigned long pos; + + pos = dr->reg_width - (in_pos + 1); + + pr_debug("read_bit: addr = %lx, pos = %ld, " + "r_width = %ld\n", dr->reg, pos, dr->reg_width); + + return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; +} + static void gpio_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, unsigned long value) { @@ -644,7 +657,7 @@ static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio) if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) return -EINVAL; - return gpio_read_reg(dr->mapped_reg, dr->reg_width, 1, bit, dr->reg); + return gpio_read_bit(dr, bit); } static int sh_gpio_get(struct gpio_chip *chip, unsigned offset) -- cgit v1.2.3-18-g5258 From ad4a07ff8da7147b391f1ff0034f313a8b9da9e5 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 14 Dec 2011 01:00:46 +0900 Subject: sh: pfc: Convert index to field and value pair Update the way the PFC code is passing bitfield selection between configure register functions. Convert the code from using index only to bitfield number and selected value. First step towards future variable bitfield width support. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/sh/pfc.c | 45 ++++++++++++++++++--------------------------- 1 file changed, 18 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c index cfca0aaf982..41e7c8f63b1 100644 --- a/drivers/sh/pfc.c +++ b/drivers/sh/pfc.c @@ -287,7 +287,8 @@ static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio, } static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id, - struct pinmux_cfg_reg **crp, int *indexp, + struct pinmux_cfg_reg **crp, + int *fieldp, int *valuep, unsigned long **cntp) { struct pinmux_cfg_reg *config_reg; @@ -306,7 +307,8 @@ static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id, for (n = 0; n < (r_width / f_width) * (1 << f_width); n++) { if (config_reg->enum_ids[n] == enum_id) { *crp = config_reg; - *indexp = n; + *fieldp = n / (1 << f_width); + *valuep = n % (1 << f_width); *cntp = &config_reg->cnt[n / (1 << f_width)]; return 0; } @@ -349,36 +351,22 @@ static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio, static void write_config_reg(struct pinmux_info *gpioc, struct pinmux_cfg_reg *crp, - int index) + int field, int value) { - unsigned long ncomb, pos, value; - void __iomem *mapped_reg; - - ncomb = 1 << crp->field_width; - pos = index / ncomb; - value = index % ncomb; - - mapped_reg = pfc_phys_to_virt(gpioc, crp->reg); + void __iomem *mapped_reg = pfc_phys_to_virt(gpioc, crp->reg); gpio_write_reg(mapped_reg, crp->reg_width, crp->field_width, - pos, value, crp->reg); + field, value, crp->reg); } static int check_config_reg(struct pinmux_info *gpioc, struct pinmux_cfg_reg *crp, - int index) + int field, int value) { - unsigned long ncomb, pos, value; - void __iomem *mapped_reg; - - ncomb = 1 << crp->field_width; - pos = index / ncomb; - value = index % ncomb; - - mapped_reg = pfc_phys_to_virt(gpioc, crp->reg); + void __iomem *mapped_reg = pfc_phys_to_virt(gpioc, crp->reg); if (gpio_read_reg(mapped_reg, crp->reg_width, - crp->field_width, pos, crp->reg) == value) + crp->field_width, field, crp->reg) == value) return 0; return -1; @@ -392,7 +380,7 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio, struct pinmux_cfg_reg *cr = NULL; pinmux_enum_t enum_id; struct pinmux_range *range; - int in_range, pos, index; + int in_range, pos, field, value; unsigned long *cntp; switch (pinmux_type) { @@ -423,7 +411,8 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio, pos = 0; enum_id = 0; - index = 0; + field = 0; + value = 0; while (1) { pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id); if (pos <= 0) @@ -470,17 +459,19 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio, if (!in_range) continue; - if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0) + if (get_config_reg(gpioc, enum_id, &cr, + &field, &value, &cntp) != 0) goto out_err; switch (cfg_mode) { case GPIO_CFG_DRYRUN: - if (!*cntp || !check_config_reg(gpioc, cr, index)) + if (!*cntp || !check_config_reg(gpioc, cr, + field, value)) continue; break; case GPIO_CFG_REQ: - write_config_reg(gpioc, cr, index); + write_config_reg(gpioc, cr, field, value); *cntp = *cntp + 1; break; -- cgit v1.2.3-18-g5258 From 18925e118b3b4d55b45711218cd3c3c4360e5cd1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 14 Dec 2011 01:00:55 +0900 Subject: sh: pfc: Add config_reg_helper() function Add a helper function for shared config reg access calculations. This allows us to reduce the amount of duplicated code, and at the same time prepare for a common place for future variable bitwidth config reg support. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/sh/pfc.c | 76 ++++++++++++++++++++++++-------------------------------- 1 file changed, 32 insertions(+), 44 deletions(-) (limited to 'drivers') diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c index 41e7c8f63b1..5481d19518f 100644 --- a/drivers/sh/pfc.c +++ b/drivers/sh/pfc.c @@ -167,41 +167,52 @@ static void gpio_write_bit(struct pinmux_data_reg *dr, gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); } -static int gpio_read_reg(void __iomem *mapped_reg, unsigned long reg_width, - unsigned long field_width, unsigned long in_pos, - unsigned long reg) +static void config_reg_helper(struct pinmux_info *gpioc, + struct pinmux_cfg_reg *crp, + unsigned long in_pos, + void __iomem **mapped_regp, + unsigned long *maskp, + unsigned long *posp) { - unsigned long data, mask, pos; + *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg); - data = 0; - mask = (1 << field_width) - 1; - pos = reg_width - ((in_pos + 1) * field_width); + *maskp = (1 << crp->field_width) - 1; + *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); +} + +static int read_config_reg(struct pinmux_info *gpioc, + struct pinmux_cfg_reg *crp, + unsigned long field) +{ + void __iomem *mapped_reg; + unsigned long mask, pos; + + config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos); - pr_debug("read_reg: addr = %lx, pos = %ld, " + pr_debug("read_reg: addr = %lx, field = %ld, " "r_width = %ld, f_width = %ld\n", - reg, pos, reg_width, field_width); + crp->reg, field, crp->reg_width, crp->field_width); - data = gpio_read_raw_reg(mapped_reg, reg_width); - return (data >> pos) & mask; + return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask; } -static void gpio_write_reg(void __iomem *mapped_reg, unsigned long reg_width, - unsigned long field_width, unsigned long in_pos, - unsigned long value, unsigned long reg) +static void write_config_reg(struct pinmux_info *gpioc, + struct pinmux_cfg_reg *crp, + unsigned long field, unsigned long value) { + void __iomem *mapped_reg; unsigned long mask, pos; - mask = (1 << field_width) - 1; - pos = reg_width - ((in_pos + 1) * field_width); + config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos); - pr_debug("write_reg addr = %lx, value = %ld, pos = %ld, " + pr_debug("write_reg addr = %lx, value = %ld, field = %ld, " "r_width = %ld, f_width = %ld\n", - reg, value, pos, reg_width, field_width); + crp->reg, value, field, crp->reg_width, crp->field_width); mask = ~(mask << pos); value = value << pos; - switch (reg_width) { + switch (crp->reg_width) { case 8: iowrite8((ioread8(mapped_reg) & mask) | value, mapped_reg); break; @@ -349,29 +360,6 @@ static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio, return -1; } -static void write_config_reg(struct pinmux_info *gpioc, - struct pinmux_cfg_reg *crp, - int field, int value) -{ - void __iomem *mapped_reg = pfc_phys_to_virt(gpioc, crp->reg); - - gpio_write_reg(mapped_reg, crp->reg_width, crp->field_width, - field, value, crp->reg); -} - -static int check_config_reg(struct pinmux_info *gpioc, - struct pinmux_cfg_reg *crp, - int field, int value) -{ - void __iomem *mapped_reg = pfc_phys_to_virt(gpioc, crp->reg); - - if (gpio_read_reg(mapped_reg, crp->reg_width, - crp->field_width, field, crp->reg) == value) - return 0; - - return -1; -} - enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio, @@ -465,8 +453,8 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio, switch (cfg_mode) { case GPIO_CFG_DRYRUN: - if (!*cntp || !check_config_reg(gpioc, cr, - field, value)) + if (!*cntp || + (read_config_reg(gpioc, cr, field) != value)) continue; break; -- cgit v1.2.3-18-g5258 From f78a26f55b2438c439609fc90b473f7f08f5b697 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 14 Dec 2011 01:01:05 +0900 Subject: sh: pfc: Variable bitfield width config register support Add support for variable config reg hardware by adding the macro PINMUX_CFG_REG_VAR(). The width of each bitfield needs to be passed to the macro, and the correct space must be consumed by each bitfield in the enum table following the macro. Data registers still need to have fixed bitfields. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/sh/pfc.c | 44 +++++++++++++++++++++++++++++++++----------- 1 file changed, 33 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c index 5481d19518f..f975f4a3343 100644 --- a/drivers/sh/pfc.c +++ b/drivers/sh/pfc.c @@ -174,10 +174,19 @@ static void config_reg_helper(struct pinmux_info *gpioc, unsigned long *maskp, unsigned long *posp) { + int k; + *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg); - *maskp = (1 << crp->field_width) - 1; - *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); + if (crp->field_width) { + *maskp = (1 << crp->field_width) - 1; + *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); + } else { + *maskp = (1 << crp->var_field_width[in_pos]) - 1; + *posp = crp->reg_width; + for (k = 0; k <= in_pos; k++) + *posp -= crp->var_field_width[k]; + } } static int read_config_reg(struct pinmux_info *gpioc, @@ -303,8 +312,8 @@ static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id, unsigned long **cntp) { struct pinmux_cfg_reg *config_reg; - unsigned long r_width, f_width; - int k, n; + unsigned long r_width, f_width, curr_width, ncomb; + int k, m, n, pos, bit_pos; k = 0; while (1) { @@ -315,14 +324,27 @@ static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id, if (!r_width) break; - for (n = 0; n < (r_width / f_width) * (1 << f_width); n++) { - if (config_reg->enum_ids[n] == enum_id) { - *crp = config_reg; - *fieldp = n / (1 << f_width); - *valuep = n % (1 << f_width); - *cntp = &config_reg->cnt[n / (1 << f_width)]; - return 0; + + pos = 0; + m = 0; + for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { + if (f_width) + curr_width = f_width; + else + curr_width = config_reg->var_field_width[m]; + + ncomb = 1 << curr_width; + for (n = 0; n < ncomb; n++) { + if (config_reg->enum_ids[pos + n] == enum_id) { + *crp = config_reg; + *fieldp = m; + *valuep = n; + *cntp = &config_reg->cnt[m]; + return 0; + } } + pos += ncomb; + m++; } k++; } -- cgit v1.2.3-18-g5258 From e499ada829cf769ac6f16627cd9f09b855a7fd6d Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 14 Dec 2011 01:01:14 +0900 Subject: sh: pfc: Unlock register support Add PFC support for a 32-bit unlock register. Needed to drive the r8a7779 PFC that comes with a funky PMMR register. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/sh/pfc.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c index f975f4a3343..522c6c46d1b 100644 --- a/drivers/sh/pfc.c +++ b/drivers/sh/pfc.c @@ -210,7 +210,7 @@ static void write_config_reg(struct pinmux_info *gpioc, unsigned long field, unsigned long value) { void __iomem *mapped_reg; - unsigned long mask, pos; + unsigned long mask, pos, data; config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos); @@ -221,17 +221,15 @@ static void write_config_reg(struct pinmux_info *gpioc, mask = ~(mask << pos); value = value << pos; - switch (crp->reg_width) { - case 8: - iowrite8((ioread8(mapped_reg) & mask) | value, mapped_reg); - break; - case 16: - iowrite16((ioread16(mapped_reg) & mask) | value, mapped_reg); - break; - case 32: - iowrite32((ioread32(mapped_reg) & mask) | value, mapped_reg); - break; - } + data = gpio_read_raw_reg(mapped_reg, crp->reg_width); + data &= mask; + data |= value; + + if (gpioc->unlock_reg) + gpio_write_raw_reg(pfc_phys_to_virt(gpioc, gpioc->unlock_reg), + 32, ~data); + + gpio_write_raw_reg(mapped_reg, crp->reg_width, data); } static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio) -- cgit v1.2.3-18-g5258