From b5964708532f4713e9cfb1b8b1a6ac8544fc66af Mon Sep 17 00:00:00 2001 From: Mark Langsdorf Date: Mon, 28 Jan 2013 16:13:13 +0000 Subject: clk / highbank: Prevent glitches in non-bypass reset mode The highbank clock will glitch with the current code if the clock rate is reset without relocking the PLL. Program the PLL correctly to prevent glitches. Signed-off-by: Mark Langsdorf Signed-off-by: Rob Herring Acked-by: Mike Turquette Signed-off-by: Rafael J. Wysocki --- drivers/clk/clk-highbank.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c index 52fecadf004..3a0b723da2b 100644 --- a/drivers/clk/clk-highbank.c +++ b/drivers/clk/clk-highbank.c @@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate, reg |= HB_PLL_EXT_ENA; reg &= ~HB_PLL_EXT_BYPASS; } else { + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); reg &= ~HB_PLL_DIVQ_MASK; reg |= divq << HB_PLL_DIVQ_SHIFT; + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); } writel(reg, hbclk->reg); -- cgit v1.2.3-18-g5258 From 2a4bd9f0db24ba14c8b38777d77add2682233c79 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 5 Feb 2013 22:52:51 +0100 Subject: cpufreq: kirkwood: Add a cpufreq driver for Marvell Kirkwood SoCs The Marvell Kirkwood SoCs have simple cpufreq support in hardware. The CPU can either use the a high speed cpu clock, or the slower DDR clock. Add a driver to swap between these two clock sources. Signed-off-by: Andrew Lunn Acked-by: Jason Cooper Acked-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki --- drivers/clk/mvebu/clk-gating-ctrl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c index 8fa5408b6c7..ebf141d4374 100644 --- a/drivers/clk/mvebu/clk-gating-ctrl.c +++ b/drivers/clk/mvebu/clk-gating-ctrl.c @@ -193,6 +193,7 @@ static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = { { "runit", NULL, 7 }, { "xor0", NULL, 8 }, { "audio", NULL, 9 }, + { "powersave", "cpuclk", 11 }, { "sata0", NULL, 14 }, { "sata1", NULL, 15 }, { "xor1", NULL, 16 }, -- cgit v1.2.3-18-g5258