From d109167b9c1002770d194644d5580a1f3588f7fc Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 10 Jun 2010 15:11:13 +0200 Subject: ARM: imx: rename mach dir for mx21 and mx27 to mach-imx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Finally all imx code should end up there, start with mach-mx2. While touching all files rename some files to use a hyphen instead of an underscore. Signed-off-by: Uwe Kleine-König --- arch/arm/Makefile | 2 +- arch/arm/mach-imx/Kconfig | 116 +++ arch/arm/mach-imx/Makefile | 23 + arch/arm/mach-imx/Makefile.boot | 7 + arch/arm/mach-imx/clock-imx21.c | 1239 ++++++++++++++++++++++++++ arch/arm/mach-imx/clock-imx27.c | 763 ++++++++++++++++ arch/arm/mach-imx/cpu-imx27.c | 64 ++ arch/arm/mach-imx/devices.c | 503 +++++++++++ arch/arm/mach-imx/devices.h | 42 + arch/arm/mach-imx/eukrea_mbimx27-baseboard.c | 249 ++++++ arch/arm/mach-imx/mach-cpuimx27.c | 235 +++++ arch/arm/mach-imx/mach-imx27lite.c | 94 ++ arch/arm/mach-imx/mach-mx21ads.c | 328 +++++++ arch/arm/mach-imx/mach-mx27_3ds.c | 100 +++ arch/arm/mach-imx/mach-mx27ads.c | 373 ++++++++ arch/arm/mach-imx/mach-mxt_td60.c | 295 ++++++ arch/arm/mach-imx/mach-pca100.c | 396 ++++++++ arch/arm/mach-imx/mach-pcm038.c | 359 ++++++++ arch/arm/mach-imx/mm-imx21.c | 83 ++ arch/arm/mach-imx/mm-imx27.c | 83 ++ arch/arm/mach-imx/pcm970-baseboard.c | 233 +++++ arch/arm/mach-imx/serial.c | 141 +++ arch/arm/mach-mx2/Kconfig | 116 --- arch/arm/mach-mx2/Makefile | 23 - arch/arm/mach-mx2/Makefile.boot | 7 - arch/arm/mach-mx2/clock_imx21.c | 1239 -------------------------- arch/arm/mach-mx2/clock_imx27.c | 763 ---------------- arch/arm/mach-mx2/cpu_imx27.c | 64 -- arch/arm/mach-mx2/devices.c | 503 ----------- arch/arm/mach-mx2/devices.h | 42 - arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c | 249 ------ arch/arm/mach-mx2/mach-cpuimx27.c | 235 ----- arch/arm/mach-mx2/mach-imx27lite.c | 94 -- arch/arm/mach-mx2/mach-mx21ads.c | 328 ------- arch/arm/mach-mx2/mach-mx27_3ds.c | 100 --- arch/arm/mach-mx2/mach-mx27ads.c | 373 -------- arch/arm/mach-mx2/mach-mxt_td60.c | 295 ------ arch/arm/mach-mx2/mach-pca100.c | 396 -------- arch/arm/mach-mx2/mach-pcm038.c | 359 -------- arch/arm/mach-mx2/mm-imx21.c | 83 -- arch/arm/mach-mx2/mm-imx27.c | 83 -- arch/arm/mach-mx2/pcm970-baseboard.c | 233 ----- arch/arm/mach-mx2/serial.c | 141 --- arch/arm/plat-mxc/Kconfig | 2 +- 44 files changed, 5728 insertions(+), 5728 deletions(-) create mode 100644 arch/arm/mach-imx/Kconfig create mode 100644 arch/arm/mach-imx/Makefile create mode 100644 arch/arm/mach-imx/Makefile.boot create mode 100644 arch/arm/mach-imx/clock-imx21.c create mode 100644 arch/arm/mach-imx/clock-imx27.c create mode 100644 arch/arm/mach-imx/cpu-imx27.c create mode 100644 arch/arm/mach-imx/devices.c create mode 100644 arch/arm/mach-imx/devices.h create mode 100644 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c create mode 100644 arch/arm/mach-imx/mach-cpuimx27.c create mode 100644 arch/arm/mach-imx/mach-imx27lite.c create mode 100644 arch/arm/mach-imx/mach-mx21ads.c create mode 100644 arch/arm/mach-imx/mach-mx27_3ds.c create mode 100644 arch/arm/mach-imx/mach-mx27ads.c create mode 100644 arch/arm/mach-imx/mach-mxt_td60.c create mode 100644 arch/arm/mach-imx/mach-pca100.c create mode 100644 arch/arm/mach-imx/mach-pcm038.c create mode 100644 arch/arm/mach-imx/mm-imx21.c create mode 100644 arch/arm/mach-imx/mm-imx27.c create mode 100644 arch/arm/mach-imx/pcm970-baseboard.c create mode 100644 arch/arm/mach-imx/serial.c delete mode 100644 arch/arm/mach-mx2/Kconfig delete mode 100644 arch/arm/mach-mx2/Makefile delete mode 100644 arch/arm/mach-mx2/Makefile.boot delete mode 100644 arch/arm/mach-mx2/clock_imx21.c delete mode 100644 arch/arm/mach-mx2/clock_imx27.c delete mode 100644 arch/arm/mach-mx2/cpu_imx27.c delete mode 100644 arch/arm/mach-mx2/devices.c delete mode 100644 arch/arm/mach-mx2/devices.h delete mode 100644 arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c delete mode 100644 arch/arm/mach-mx2/mach-cpuimx27.c delete mode 100644 arch/arm/mach-mx2/mach-imx27lite.c delete mode 100644 arch/arm/mach-mx2/mach-mx21ads.c delete mode 100644 arch/arm/mach-mx2/mach-mx27_3ds.c delete mode 100644 arch/arm/mach-mx2/mach-mx27ads.c delete mode 100644 arch/arm/mach-mx2/mach-mxt_td60.c delete mode 100644 arch/arm/mach-mx2/mach-pca100.c delete mode 100644 arch/arm/mach-mx2/mach-pcm038.c delete mode 100644 arch/arm/mach-mx2/mm-imx21.c delete mode 100644 arch/arm/mach-mx2/mm-imx27.c delete mode 100644 arch/arm/mach-mx2/pcm970-baseboard.c delete mode 100644 arch/arm/mach-mx2/serial.c (limited to 'arch') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 64ba313724d..c60d604b2ef 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -146,7 +146,7 @@ machine-$(CONFIG_ARCH_MMP) := mmp machine-$(CONFIG_ARCH_MSM) := msm machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 machine-$(CONFIG_ARCH_MX1) := mx1 -machine-$(CONFIG_ARCH_MX2) := mx2 +machine-$(CONFIG_ARCH_MX2) := imx machine-$(CONFIG_ARCH_MX25) := mx25 machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX5) := mx5 diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig new file mode 100644 index 00000000000..742fd4e6dcb --- /dev/null +++ b/arch/arm/mach-imx/Kconfig @@ -0,0 +1,116 @@ +if ARCH_MX2 + +choice + prompt "CPUs:" + default MACH_MX21 + +config MACH_MX21 + bool "i.MX21 support" + select ARCH_MXC_AUDMUX_V1 + help + This enables support for Freescale's MX2 based i.MX21 processor. + +config MACH_MX27 + bool "i.MX27 support" + select ARCH_MXC_AUDMUX_V1 + help + This enables support for Freescale's MX2 based i.MX27 processor. + +endchoice + +comment "MX2 platforms:" + +config MACH_MX21ADS + bool "MX21ADS platform" + depends on MACH_MX21 + help + Include support for MX21ADS platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX27ADS + bool "MX27ADS platform" + depends on MACH_MX27 + help + Include support for MX27ADS platform. This includes specific + configurations for the board and its peripherals. + +config MACH_PCM038 + bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" + depends on MACH_MX27 + select MXC_ULPI if USB_ULPI + help + Include support for phyCORE-i.MX27 (aka pcm038) platform. This + includes specific configurations for the module and its peripherals. + +choice + prompt "Baseboard" + depends on MACH_PCM038 + default MACH_PCM970_BASEBOARD + +config MACH_PCM970_BASEBOARD + prompt "PHYTEC PCM970 development board" + bool + help + This adds board specific devices that can be found on Phytec's + PCM970 evaluation board. + +endchoice + +config MACH_CPUIMX27 + bool "Eukrea CPUIMX27 module" + depends on MACH_MX27 + help + Include support for Eukrea CPUIMX27 platform. This includes + specific configurations for the module and its peripherals. + +config MACH_EUKREA_CPUIMX27_USESDHC2 + bool "CPUIMX27 integrates SDHC2 module" + depends on MACH_CPUIMX27 + help + This adds support for the internal SDHC2 used on CPUIMX27 used + for wifi or eMMC. + +choice + prompt "Baseboard" + depends on MACH_CPUIMX27 + default MACH_EUKREA_MBIMX27_BASEBOARD + +config MACH_EUKREA_MBIMX27_BASEBOARD + prompt "Eukrea MBIMX27 development board" + bool + help + This adds board specific devices that can be found on Eukrea's + MBIMX27 evaluation board. + +endchoice + +config MACH_MX27_3DS + bool "MX27PDK platform" + depends on MACH_MX27 + help + Include support for MX27PDK platform. This includes specific + configurations for the board and its peripherals. + +config MACH_IMX27LITE + bool "LogicPD MX27 LITEKIT platform" + depends on MACH_MX27 + help + Include support for MX27 LITEKIT platform. This includes specific + configurations for the board and its peripherals. + +config MACH_PCA100 + bool "Phytec phyCARD-s (pca100)" + depends on MACH_MX27 + select MXC_ULPI if USB_ULPI + help + Include support for phyCARD-s (aka pca100) platform. This + includes specific configurations for the module and its peripherals. + +config MACH_MXT_TD60 + bool "Maxtrack i-MXT TD60" + depends on MACH_MX27 + help + Include support for i-MXT (aka td60) platform. This + includes specific configurations for the module and its peripherals. + +endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile new file mode 100644 index 00000000000..068f4937deb --- /dev/null +++ b/arch/arm/mach-imx/Makefile @@ -0,0 +1,23 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y := devices.o serial.o + +obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o + +obj-$(CONFIG_MACH_MX27) += cpu-imx27.o +obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o + +obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o +obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o +obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o +obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o +obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o +obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o +obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o +obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o +obj-$(CONFIG_MACH_PCA100) += mach-pca100.o +obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot new file mode 100644 index 00000000000..e867398a8fd --- /dev/null +++ b/arch/arm/mach-imx/Makefile.boot @@ -0,0 +1,7 @@ +zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000 +params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 +initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 + +zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000 +params_phys-$(CONFIG_MACH_MX27) := 0xA0000100 +initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000 diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c new file mode 100644 index 00000000000..bb419ef4d13 --- /dev/null +++ b/arch/arm/mach-imx/clock-imx21.c @@ -0,0 +1,1239 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off))) + +/* Register offsets */ +#define CCM_CSCR IO_ADDR_CCM(0x0) +#define CCM_MPCTL0 IO_ADDR_CCM(0x4) +#define CCM_MPCTL1 IO_ADDR_CCM(0x8) +#define CCM_SPCTL0 IO_ADDR_CCM(0xc) +#define CCM_SPCTL1 IO_ADDR_CCM(0x10) +#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) +#define CCM_PCDR0 IO_ADDR_CCM(0x18) +#define CCM_PCDR1 IO_ADDR_CCM(0x1c) +#define CCM_PCCR0 IO_ADDR_CCM(0x20) +#define CCM_PCCR1 IO_ADDR_CCM(0x24) +#define CCM_CCSR IO_ADDR_CCM(0x28) +#define CCM_PMCTL IO_ADDR_CCM(0x2c) +#define CCM_PMCOUNT IO_ADDR_CCM(0x30) +#define CCM_WKGDCTL IO_ADDR_CCM(0x34) + +#define CCM_CSCR_PRESC_OFFSET 29 +#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET) + +#define CCM_CSCR_USB_OFFSET 26 +#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET) +#define CCM_CSCR_SD_OFFSET 24 +#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET) +#define CCM_CSCR_SPLLRES (1 << 22) +#define CCM_CSCR_MPLLRES (1 << 21) +#define CCM_CSCR_SSI2_OFFSET 20 +#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET) +#define CCM_CSCR_SSI1_OFFSET 19 +#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET) +#define CCM_CSCR_FIR_OFFSET 18 +#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET) +#define CCM_CSCR_SP (1 << 17) +#define CCM_CSCR_MCU (1 << 16) +#define CCM_CSCR_BCLK_OFFSET 10 +#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET) +#define CCM_CSCR_IPDIV_OFFSET 9 +#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET) + +#define CCM_CSCR_OSC26MDIV (1 << 4) +#define CCM_CSCR_OSC26M (1 << 3) +#define CCM_CSCR_FPM (1 << 2) +#define CCM_CSCR_SPEN (1 << 1) +#define CCM_CSCR_MPEN 1 + +#define CCM_MPCTL0_CPLM (1 << 31) +#define CCM_MPCTL0_PD_OFFSET 26 +#define CCM_MPCTL0_PD_MASK (0xf << 26) +#define CCM_MPCTL0_MFD_OFFSET 16 +#define CCM_MPCTL0_MFD_MASK (0x3ff << 16) +#define CCM_MPCTL0_MFI_OFFSET 10 +#define CCM_MPCTL0_MFI_MASK (0xf << 10) +#define CCM_MPCTL0_MFN_OFFSET 0 +#define CCM_MPCTL0_MFN_MASK 0x3ff + +#define CCM_MPCTL1_LF (1 << 15) +#define CCM_MPCTL1_BRMO (1 << 6) + +#define CCM_SPCTL0_CPLM (1 << 31) +#define CCM_SPCTL0_PD_OFFSET 26 +#define CCM_SPCTL0_PD_MASK (0xf << 26) +#define CCM_SPCTL0_MFD_OFFSET 16 +#define CCM_SPCTL0_MFD_MASK (0x3ff << 16) +#define CCM_SPCTL0_MFI_OFFSET 10 +#define CCM_SPCTL0_MFI_MASK (0xf << 10) +#define CCM_SPCTL0_MFN_OFFSET 0 +#define CCM_SPCTL0_MFN_MASK 0x3ff + +#define CCM_SPCTL1_LF (1 << 15) +#define CCM_SPCTL1_BRMO (1 << 6) + +#define CCM_OSC26MCTL_PEAK_OFFSET 16 +#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16) +#define CCM_OSC26MCTL_AGC_OFFSET 8 +#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8) +#define CCM_OSC26MCTL_ANATEST_OFFSET 0 +#define CCM_OSC26MCTL_ANATEST_MASK 0x3f + +#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 +#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) +#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 +#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) +#define CCM_PCDR0_NFCDIV_OFFSET 12 +#define CCM_PCDR0_NFCDIV_MASK (0xf << 12) +#define CCM_PCDR0_48MDIV_OFFSET 5 +#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET) +#define CCM_PCDR0_FIRIDIV_OFFSET 0 +#define CCM_PCDR0_FIRIDIV_MASK 0x1f +#define CCM_PCDR1_PERDIV4_OFFSET 24 +#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) +#define CCM_PCDR1_PERDIV3_OFFSET 16 +#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16) +#define CCM_PCDR1_PERDIV2_OFFSET 8 +#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8) +#define CCM_PCDR1_PERDIV1_OFFSET 0 +#define CCM_PCDR1_PERDIV1_MASK 0x3f + +#define CCM_PCCR_HCLK_CSI_OFFSET 31 +#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_DMA_OFFSET 30 +#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_BROM_OFFSET 28 +#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_EMMA_OFFSET 27 +#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_LCDC_OFFSET 26 +#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_SLCDC_OFFSET 25 +#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_USBOTG_OFFSET 24 +#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_BMI_OFFSET 23 +#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK) +#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0 +#define CCM_PCCR_PERCLK4_OFFSET 22 +#define CCM_PCCR_PERCLK4_REG CCM_PCCR0 +#define CCM_PCCR_SLCDC_OFFSET 21 +#define CCM_PCCR_SLCDC_REG CCM_PCCR0 +#define CCM_PCCR_FIRI_BAUD_OFFSET 20 +#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK) +#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0 +#define CCM_PCCR_NFC_OFFSET 19 +#define CCM_PCCR_NFC_REG CCM_PCCR0 +#define CCM_PCCR_LCDC_OFFSET 18 +#define CCM_PCCR_LCDC_REG CCM_PCCR0 +#define CCM_PCCR_SSI1_BAUD_OFFSET 17 +#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0 +#define CCM_PCCR_SSI2_BAUD_OFFSET 16 +#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0 +#define CCM_PCCR_EMMA_OFFSET 15 +#define CCM_PCCR_EMMA_REG CCM_PCCR0 +#define CCM_PCCR_USBOTG_OFFSET 14 +#define CCM_PCCR_USBOTG_REG CCM_PCCR0 +#define CCM_PCCR_DMA_OFFSET 13 +#define CCM_PCCR_DMA_REG CCM_PCCR0 +#define CCM_PCCR_I2C1_OFFSET 12 +#define CCM_PCCR_I2C1_REG CCM_PCCR0 +#define CCM_PCCR_GPIO_OFFSET 11 +#define CCM_PCCR_GPIO_REG CCM_PCCR0 +#define CCM_PCCR_SDHC2_OFFSET 10 +#define CCM_PCCR_SDHC2_REG CCM_PCCR0 +#define CCM_PCCR_SDHC1_OFFSET 9 +#define CCM_PCCR_SDHC1_REG CCM_PCCR0 +#define CCM_PCCR_FIRI_OFFSET 8 +#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK) +#define CCM_PCCR_FIRI_REG CCM_PCCR0 +#define CCM_PCCR_SSI2_IPG_OFFSET 7 +#define CCM_PCCR_SSI2_REG CCM_PCCR0 +#define CCM_PCCR_SSI1_IPG_OFFSET 6 +#define CCM_PCCR_SSI1_REG CCM_PCCR0 +#define CCM_PCCR_CSPI2_OFFSET 5 +#define CCM_PCCR_CSPI2_REG CCM_PCCR0 +#define CCM_PCCR_CSPI1_OFFSET 4 +#define CCM_PCCR_CSPI1_REG CCM_PCCR0 +#define CCM_PCCR_UART4_OFFSET 3 +#define CCM_PCCR_UART4_REG CCM_PCCR0 +#define CCM_PCCR_UART3_OFFSET 2 +#define CCM_PCCR_UART3_REG CCM_PCCR0 +#define CCM_PCCR_UART2_OFFSET 1 +#define CCM_PCCR_UART2_REG CCM_PCCR0 +#define CCM_PCCR_UART1_OFFSET 0 +#define CCM_PCCR_UART1_REG CCM_PCCR0 + +#define CCM_PCCR_OWIRE_OFFSET 31 +#define CCM_PCCR_OWIRE_REG CCM_PCCR1 +#define CCM_PCCR_KPP_OFFSET 30 +#define CCM_PCCR_KPP_REG CCM_PCCR1 +#define CCM_PCCR_RTC_OFFSET 29 +#define CCM_PCCR_RTC_REG CCM_PCCR1 +#define CCM_PCCR_PWM_OFFSET 28 +#define CCM_PCCR_PWM_REG CCM_PCCR1 +#define CCM_PCCR_GPT3_OFFSET 27 +#define CCM_PCCR_GPT3_REG CCM_PCCR1 +#define CCM_PCCR_GPT2_OFFSET 26 +#define CCM_PCCR_GPT2_REG CCM_PCCR1 +#define CCM_PCCR_GPT1_OFFSET 25 +#define CCM_PCCR_GPT1_REG CCM_PCCR1 +#define CCM_PCCR_WDT_OFFSET 24 +#define CCM_PCCR_WDT_REG CCM_PCCR1 +#define CCM_PCCR_CSPI3_OFFSET 23 +#define CCM_PCCR_CSPI3_REG CCM_PCCR1 + +#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET) +#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET) +#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET) +#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET) +#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET) +#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET) +#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET) +#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET) +#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET) +#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET) +#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET) +#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET) +#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET) +#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET) +#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET) +#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET) +#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET) +#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET) +#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET) +#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET) +#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET) +#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET) +#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET) +#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET) +#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET) +#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET) +#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET) +#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET) +#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET) +#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET) +#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET) +#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET) +#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET) +#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET) +#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET) +#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET) +#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET) + +#define CCM_CCSR_32KSR (1 << 15) + +#define CCM_CCSR_CLKMODE1 (1 << 9) +#define CCM_CCSR_CLKMODE0 (1 << 8) + +#define CCM_CCSR_CLKOSEL_OFFSET 0 +#define CCM_CCSR_CLKOSEL_MASK 0x1f + +#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */ +#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ + +static int _clk_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static unsigned long _clk_generic_round_rate(struct clk *clk, + unsigned long rate, + u32 max_divisor) +{ + u32 div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (parent_rate % rate) + div++; + + if (div > max_divisor) + div = max_divisor; + + return parent_rate / div; +} + +static int _clk_spll_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(CCM_CSCR); + reg |= CCM_CSCR_SPEN; + __raw_writel(reg, CCM_CSCR); + + while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0) + ; + return 0; +} + +static void _clk_spll_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(CCM_CSCR); + reg &= ~CCM_CSCR_SPEN; + __raw_writel(reg, CCM_CSCR); +} + + +#define CSCR() (__raw_readl(CCM_CSCR)) +#define PCDR0() (__raw_readl(CCM_PCDR0)) +#define PCDR1() (__raw_readl(CCM_PCDR1)) + +static unsigned long _clk_perclkx_round_rate(struct clk *clk, + unsigned long rate) +{ + return _clk_generic_round_rate(clk, rate, 64); +} + +static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + if (clk->id < 0 || clk->id > 3) + return -EINVAL; + + div = parent_rate / rate; + if (div > 64 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + div--; + + reg = + __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK << + (clk->id << 3)); + reg |= div << (clk->id << 3); + __raw_writel(reg, CCM_PCDR1); + + return 0; +} + +static unsigned long _clk_usb_recalc(struct clk *clk) +{ + unsigned long usb_pdf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET; + + return parent_rate / (usb_pdf + 1U); +} + +static unsigned long _clk_usb_round_rate(struct clk *clk, + unsigned long rate) +{ + return _clk_generic_round_rate(clk, rate, 8); +} + +static int _clk_usb_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div > 8 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + div--; + + reg = CSCR() & ~CCM_CSCR_USB_MASK; + reg |= div << CCM_CSCR_USB_OFFSET; + __raw_writel(reg, CCM_CSCR); + + return 0; +} + +static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf) +{ + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ + + return 2UL * parent_rate / pdf; +} + +static unsigned long _clk_ssi1_recalc(struct clk *clk) +{ + return _clk_ssix_recalc(clk, + (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) + >> CCM_PCDR0_SSI1BAUDDIV_OFFSET); +} + +static unsigned long _clk_ssi2_recalc(struct clk *clk) +{ + return _clk_ssix_recalc(clk, + (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >> + CCM_PCDR0_SSI2BAUDDIV_OFFSET); +} + +static unsigned long _clk_nfc_recalc(struct clk *clk) +{ + unsigned long nfc_pdf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + nfc_pdf = (PCDR0() & CCM_PCDR0_NFCDIV_MASK) + >> CCM_PCDR0_NFCDIV_OFFSET; + + return parent_rate / (nfc_pdf + 1); +} + +static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) +{ + return clk->parent->round_rate(clk->parent, rate); +} + +static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) +{ + return clk->parent->set_rate(clk->parent, rate); +} + +static unsigned long external_high_reference; /* in Hz */ + +static unsigned long get_high_reference_clock_rate(struct clk *clk) +{ + return external_high_reference; +} + +/* + * the high frequency external clock reference + * Default case is 26MHz. + */ +static struct clk ckih_clk = { + .get_rate = get_high_reference_clock_rate, +}; + +static unsigned long external_low_reference; /* in Hz */ + +static unsigned long get_low_reference_clock_rate(struct clk *clk) +{ + return external_low_reference; +} + +/* + * the low frequency external clock reference + * Default case is 32.768kHz. + */ +static struct clk ckil_clk = { + .get_rate = get_low_reference_clock_rate, +}; + + +static unsigned long _clk_fpm_recalc(struct clk *clk) +{ + return clk_get_rate(clk->parent) * 512; +} + +/* Output of frequency pre multiplier */ +static struct clk fpm_clk = { + .parent = &ckil_clk, + .get_rate = _clk_fpm_recalc, +}; + +static unsigned long get_mpll_clk(struct clk *clk) +{ + uint32_t reg; + unsigned long ref_clk; + unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; + unsigned long long temp; + + ref_clk = clk_get_rate(clk->parent); + + reg = __raw_readl(CCM_MPCTL0); + pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET; + mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET; + mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET; + mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET; + + mfi = (mfi <= 5) ? 5 : mfi; + temp = 2LL * ref_clk * mfn; + do_div(temp, mfd + 1); + temp = 2LL * ref_clk * mfi + temp; + do_div(temp, pdf + 1); + + return (unsigned long)temp; +} + +static struct clk mpll_clk = { + .parent = &ckih_clk, + .get_rate = get_mpll_clk, +}; + +static unsigned long _clk_fclk_get_rate(struct clk *clk) +{ + unsigned long parent_rate; + u32 div; + + div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET; + parent_rate = clk_get_rate(clk->parent); + + return parent_rate / (div+1); +} + +static struct clk fclk_clk = { + .parent = &mpll_clk, + .get_rate = _clk_fclk_get_rate +}; + +static unsigned long get_spll_clk(struct clk *clk) +{ + uint32_t reg; + unsigned long ref_clk; + unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; + unsigned long long temp; + + ref_clk = clk_get_rate(clk->parent); + + reg = __raw_readl(CCM_SPCTL0); + pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET; + mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET; + mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET; + mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET; + + mfi = (mfi <= 5) ? 5 : mfi; + temp = 2LL * ref_clk * mfn; + do_div(temp, mfd + 1); + temp = 2LL * ref_clk * mfi + temp; + do_div(temp, pdf + 1); + + return (unsigned long)temp; +} + +static struct clk spll_clk = { + .parent = &ckih_clk, + .get_rate = get_spll_clk, + .enable = _clk_spll_enable, + .disable = _clk_spll_disable, +}; + +static unsigned long get_hclk_clk(struct clk *clk) +{ + unsigned long rate; + unsigned long bclk_pdf; + + bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK) + >> CCM_CSCR_BCLK_OFFSET; + + rate = clk_get_rate(clk->parent); + return rate / (bclk_pdf + 1); +} + +static struct clk hclk_clk = { + .parent = &fclk_clk, + .get_rate = get_hclk_clk, +}; + +static unsigned long get_ipg_clk(struct clk *clk) +{ + unsigned long rate; + unsigned long ipg_pdf; + + ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET; + + rate = clk_get_rate(clk->parent); + return rate / (ipg_pdf + 1); +} + +static struct clk ipg_clk = { + .parent = &hclk_clk, + .get_rate = get_ipg_clk, +}; + +static unsigned long _clk_perclkx_recalc(struct clk *clk) +{ + unsigned long perclk_pdf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + if (clk->id < 0 || clk->id > 3) + return 0; + + perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK; + + return parent_rate / (perclk_pdf + 1); +} + +static struct clk per_clk[] = { + { + .id = 0, + .parent = &mpll_clk, + .get_rate = _clk_perclkx_recalc, + }, { + .id = 1, + .parent = &mpll_clk, + .get_rate = _clk_perclkx_recalc, + }, { + .id = 2, + .parent = &mpll_clk, + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .get_rate = _clk_perclkx_recalc, + /* Enable/Disable done via lcd_clkc[1] */ + }, { + .id = 3, + .parent = &mpll_clk, + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .get_rate = _clk_perclkx_recalc, + /* Enable/Disable done via csi_clk[1] */ + }, +}; + +static struct clk uart_ipg_clk[]; + +static struct clk uart_clk[] = { + { + .id = 0, + .parent = &per_clk[0], + .secondary = &uart_ipg_clk[0], + }, { + .id = 1, + .parent = &per_clk[0], + .secondary = &uart_ipg_clk[1], + }, { + .id = 2, + .parent = &per_clk[0], + .secondary = &uart_ipg_clk[2], + }, { + .id = 3, + .parent = &per_clk[0], + .secondary = &uart_ipg_clk[3], + }, +}; + +static struct clk uart_ipg_clk[] = { + { + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_UART1_REG, + .enable_shift = CCM_PCCR_UART1_OFFSET, + .disable = _clk_disable, + }, { + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_UART2_REG, + .enable_shift = CCM_PCCR_UART2_OFFSET, + .disable = _clk_disable, + }, { + .id = 2, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_UART3_REG, + .enable_shift = CCM_PCCR_UART3_OFFSET, + .disable = _clk_disable, + }, { + .id = 3, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_UART4_REG, + .enable_shift = CCM_PCCR_UART4_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk gpt_ipg_clk[]; + +static struct clk gpt_clk[] = { + { + .id = 0, + .parent = &per_clk[0], + .secondary = &gpt_ipg_clk[0], + }, { + .id = 1, + .parent = &per_clk[0], + .secondary = &gpt_ipg_clk[1], + }, { + .id = 2, + .parent = &per_clk[0], + .secondary = &gpt_ipg_clk[2], + }, +}; + +static struct clk gpt_ipg_clk[] = { + { + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_GPT1_REG, + .enable_shift = CCM_PCCR_GPT1_OFFSET, + .disable = _clk_disable, + }, { + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_GPT2_REG, + .enable_shift = CCM_PCCR_GPT2_OFFSET, + .disable = _clk_disable, + }, { + .id = 2, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_GPT3_REG, + .enable_shift = CCM_PCCR_GPT3_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk pwm_clk[] = { + { + .parent = &per_clk[0], + .secondary = &pwm_clk[1], + }, { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_PWM_REG, + .enable_shift = CCM_PCCR_PWM_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk sdhc_ipg_clk[]; + +static struct clk sdhc_clk[] = { + { + .id = 0, + .parent = &per_clk[1], + .secondary = &sdhc_ipg_clk[0], + }, { + .id = 1, + .parent = &per_clk[1], + .secondary = &sdhc_ipg_clk[1], + }, +}; + +static struct clk sdhc_ipg_clk[] = { + { + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_SDHC1_REG, + .enable_shift = CCM_PCCR_SDHC1_OFFSET, + .disable = _clk_disable, + }, { + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_SDHC2_REG, + .enable_shift = CCM_PCCR_SDHC2_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk cspi_ipg_clk[]; + +static struct clk cspi_clk[] = { + { + .id = 0, + .parent = &per_clk[1], + .secondary = &cspi_ipg_clk[0], + }, { + .id = 1, + .parent = &per_clk[1], + .secondary = &cspi_ipg_clk[1], + }, { + .id = 2, + .parent = &per_clk[1], + .secondary = &cspi_ipg_clk[2], + }, +}; + +static struct clk cspi_ipg_clk[] = { + { + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_CSPI1_REG, + .enable_shift = CCM_PCCR_CSPI1_OFFSET, + .disable = _clk_disable, + }, { + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_CSPI2_REG, + .enable_shift = CCM_PCCR_CSPI2_OFFSET, + .disable = _clk_disable, + }, { + .id = 3, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_CSPI3_REG, + .enable_shift = CCM_PCCR_CSPI3_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk lcdc_clk[] = { + { + .parent = &per_clk[2], + .secondary = &lcdc_clk[1], + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, + }, { + .parent = &ipg_clk, + .secondary = &lcdc_clk[2], + .enable = _clk_enable, + .enable_reg = CCM_PCCR_LCDC_REG, + .enable_shift = CCM_PCCR_LCDC_OFFSET, + .disable = _clk_disable, + }, { + .parent = &hclk_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_HCLK_LCDC_REG, + .enable_shift = CCM_PCCR_HCLK_LCDC_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk csi_clk[] = { + { + .parent = &per_clk[3], + .secondary = &csi_clk[1], + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, + }, { + .parent = &hclk_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_HCLK_CSI_REG, + .enable_shift = CCM_PCCR_HCLK_CSI_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk usb_clk[] = { + { + .parent = &spll_clk, + .secondary = &usb_clk[1], + .get_rate = _clk_usb_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_USBOTG_REG, + .enable_shift = CCM_PCCR_USBOTG_OFFSET, + .disable = _clk_disable, + .round_rate = _clk_usb_round_rate, + .set_rate = _clk_usb_set_rate, + }, { + .parent = &hclk_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_HCLK_USBOTG_REG, + .enable_shift = CCM_PCCR_HCLK_USBOTG_OFFSET, + .disable = _clk_disable, + } +}; + +static struct clk ssi_ipg_clk[]; + +static struct clk ssi_clk[] = { + { + .id = 0, + .parent = &mpll_clk, + .secondary = &ssi_ipg_clk[0], + .get_rate = _clk_ssi1_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_SSI1_BAUD_REG, + .enable_shift = CCM_PCCR_SSI1_BAUD_OFFSET, + .disable = _clk_disable, + }, { + .id = 1, + .parent = &mpll_clk, + .secondary = &ssi_ipg_clk[1], + .get_rate = _clk_ssi2_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_SSI2_BAUD_REG, + .enable_shift = CCM_PCCR_SSI2_BAUD_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk ssi_ipg_clk[] = { + { + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_SSI1_REG, + .enable_shift = CCM_PCCR_SSI1_IPG_OFFSET, + .disable = _clk_disable, + }, { + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_SSI2_REG, + .enable_shift = CCM_PCCR_SSI2_IPG_OFFSET, + .disable = _clk_disable, + }, +}; + + +static struct clk nfc_clk = { + .parent = &fclk_clk, + .get_rate = _clk_nfc_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_NFC_REG, + .enable_shift = CCM_PCCR_NFC_OFFSET, + .disable = _clk_disable, +}; + +static struct clk dma_clk[] = { + { + .parent = &hclk_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_DMA_REG, + .enable_shift = CCM_PCCR_DMA_OFFSET, + .disable = _clk_disable, + .secondary = &dma_clk[1], + }, { + .enable = _clk_enable, + .enable_reg = CCM_PCCR_HCLK_DMA_REG, + .enable_shift = CCM_PCCR_HCLK_DMA_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk brom_clk = { + .parent = &hclk_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_HCLK_BROM_REG, + .enable_shift = CCM_PCCR_HCLK_BROM_OFFSET, + .disable = _clk_disable, +}; + +static struct clk emma_clk[] = { + { + .parent = &hclk_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_EMMA_REG, + .enable_shift = CCM_PCCR_EMMA_OFFSET, + .disable = _clk_disable, + .secondary = &emma_clk[1], + }, { + .enable = _clk_enable, + .enable_reg = CCM_PCCR_HCLK_EMMA_REG, + .enable_shift = CCM_PCCR_HCLK_EMMA_OFFSET, + .disable = _clk_disable, + } +}; + +static struct clk slcdc_clk[] = { + { + .parent = &hclk_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_SLCDC_REG, + .enable_shift = CCM_PCCR_SLCDC_OFFSET, + .disable = _clk_disable, + .secondary = &slcdc_clk[1], + }, { + .enable = _clk_enable, + .enable_reg = CCM_PCCR_HCLK_SLCDC_REG, + .enable_shift = CCM_PCCR_HCLK_SLCDC_OFFSET, + .disable = _clk_disable, + } +}; + +static struct clk wdog_clk = { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_WDT_REG, + .enable_shift = CCM_PCCR_WDT_OFFSET, + .disable = _clk_disable, +}; + +static struct clk gpio_clk = { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_GPIO_REG, + .enable_shift = CCM_PCCR_GPIO_OFFSET, + .disable = _clk_disable, +}; + +static struct clk i2c_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_I2C1_REG, + .enable_shift = CCM_PCCR_I2C1_OFFSET, + .disable = _clk_disable, +}; + +static struct clk kpp_clk = { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_KPP_REG, + .enable_shift = CCM_PCCR_KPP_OFFSET, + .disable = _clk_disable, +}; + +static struct clk owire_clk = { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_OWIRE_REG, + .enable_shift = CCM_PCCR_OWIRE_OFFSET, + .disable = _clk_disable, +}; + +static struct clk rtc_clk = { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR_RTC_REG, + .enable_shift = CCM_PCCR_RTC_OFFSET, + .disable = _clk_disable, +}; + +static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate) +{ + return _clk_generic_round_rate(clk, rate, 8); +} + +static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if (div > 8 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + div--; + + reg = __raw_readl(CCM_PCDR0); + + if (clk->parent == &usb_clk[0]) { + reg &= ~CCM_PCDR0_48MDIV_MASK; + reg |= div << CCM_PCDR0_48MDIV_OFFSET; + } + __raw_writel(reg, CCM_PCDR0); + + return 0; +} + +static unsigned long _clk_clko_recalc(struct clk *clk) +{ + u32 div = 0; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + if (clk->parent == &usb_clk[0]) /* 48M */ + div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_48MDIV_MASK + >> CCM_PCDR0_48MDIV_OFFSET; + div++; + + return parent_rate / div; +} + +static struct clk clko_clk; + +static int _clk_clko_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK; + + if (parent == &ckil_clk) + reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &fpm_clk) + reg |= 1 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &ckih_clk) + reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == mpll_clk.parent) + reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == spll_clk.parent) + reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &mpll_clk) + reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &spll_clk) + reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &fclk_clk) + reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &hclk_clk) + reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &ipg_clk) + reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &per_clk[0]) + reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &per_clk[1]) + reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &per_clk[2]) + reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &per_clk[3]) + reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &ssi_clk[0]) + reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &ssi_clk[1]) + reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &nfc_clk) + reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &usb_clk[0]) + reg |= 0x14 << CCM_CCSR_CLKOSEL_OFFSET; + else if (parent == &clko_clk) + reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET; + else + return -EINVAL; + + __raw_writel(reg, CCM_CCSR); + + return 0; +} + +static struct clk clko_clk = { + .get_rate = _clk_clko_recalc, + .set_rate = _clk_clko_set_rate, + .round_rate = _clk_clko_round_rate, + .set_parent = _clk_clko_set_parent, +}; + + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + }, +static struct clk_lookup lookups[] = { +/* It's unlikely that any driver wants one of them directly: + _REGISTER_CLOCK(NULL, "ckih", ckih_clk) + _REGISTER_CLOCK(NULL, "ckil", ckil_clk) + _REGISTER_CLOCK(NULL, "fpm", fpm_clk) + _REGISTER_CLOCK(NULL, "mpll", mpll_clk) + _REGISTER_CLOCK(NULL, "spll", spll_clk) + _REGISTER_CLOCK(NULL, "fclk", fclk_clk) + _REGISTER_CLOCK(NULL, "hclk", hclk_clk) + _REGISTER_CLOCK(NULL, "ipg", ipg_clk) +*/ + _REGISTER_CLOCK(NULL, "perclk1", per_clk[0]) + _REGISTER_CLOCK(NULL, "perclk2", per_clk[1]) + _REGISTER_CLOCK(NULL, "perclk3", per_clk[2]) + _REGISTER_CLOCK(NULL, "perclk4", per_clk[3]) + _REGISTER_CLOCK(NULL, "clko", clko_clk) + _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]) + _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1]) + _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2]) + _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[3]) + _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0]) + _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1]) + _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2]) + _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0]) + _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0]) + _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1]) + _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0]) + _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1]) + _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2]) + _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0]) + _REGISTER_CLOCK(NULL, "csi", csi_clk[0]) + _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0]) + _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0]) + _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1]) + _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) + _REGISTER_CLOCK(NULL, "dma", dma_clk[0]) + _REGISTER_CLOCK(NULL, "brom", brom_clk) + _REGISTER_CLOCK(NULL, "emma", emma_clk[0]) + _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0]) + _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) + _REGISTER_CLOCK(NULL, "gpio", gpio_clk) + _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) + _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) + _REGISTER_CLOCK(NULL, "owire", owire_clk) + _REGISTER_CLOCK(NULL, "rtc", rtc_clk) +}; + +/* + * must be called very early to get information about the + * available clock rate when the timer framework starts + */ +int __init mx21_clocks_init(unsigned long lref, unsigned long href) +{ + u32 cscr; + + external_low_reference = lref; + external_high_reference = href; + + /* detect clock reference for both system PLL */ + cscr = CSCR(); + if (cscr & CCM_CSCR_MCU) + mpll_clk.parent = &ckih_clk; + else + mpll_clk.parent = &fpm_clk; + + if (cscr & CCM_CSCR_SP) + spll_clk.parent = &ckih_clk; + else + spll_clk.parent = &fpm_clk; + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + /* Turn off all clock gates */ + __raw_writel(0, CCM_PCCR0); + __raw_writel(CCM_PCCR_GPT1_MASK, CCM_PCCR1); + + /* This turns of the serial PLL as well */ + spll_clk.disable(&spll_clk); + + /* This will propagate to all children and init all the clock rates. */ + clk_enable(&per_clk[0]); + clk_enable(&gpio_clk); + +#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) + clk_enable(&uart_clk[0]); +#endif + + mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), + MX21_INT_GPT1); + return 0; +} diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c new file mode 100644 index 00000000000..0f0823c8b17 --- /dev/null +++ b/arch/arm/mach-imx/clock-imx27.c @@ -0,0 +1,763 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include + +#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off))) + +/* Register offsets */ +#define CCM_CSCR IO_ADDR_CCM(0x0) +#define CCM_MPCTL0 IO_ADDR_CCM(0x4) +#define CCM_MPCTL1 IO_ADDR_CCM(0x8) +#define CCM_SPCTL0 IO_ADDR_CCM(0xc) +#define CCM_SPCTL1 IO_ADDR_CCM(0x10) +#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) +#define CCM_PCDR0 IO_ADDR_CCM(0x18) +#define CCM_PCDR1 IO_ADDR_CCM(0x1c) +#define CCM_PCCR0 IO_ADDR_CCM(0x20) +#define CCM_PCCR1 IO_ADDR_CCM(0x24) +#define CCM_CCSR IO_ADDR_CCM(0x28) +#define CCM_PMCTL IO_ADDR_CCM(0x2c) +#define CCM_PMCOUNT IO_ADDR_CCM(0x30) +#define CCM_WKGDCTL IO_ADDR_CCM(0x34) + +#define CCM_CSCR_UPDATE_DIS (1 << 31) +#define CCM_CSCR_SSI2 (1 << 23) +#define CCM_CSCR_SSI1 (1 << 22) +#define CCM_CSCR_VPU (1 << 21) +#define CCM_CSCR_MSHC (1 << 20) +#define CCM_CSCR_SPLLRES (1 << 19) +#define CCM_CSCR_MPLLRES (1 << 18) +#define CCM_CSCR_SP (1 << 17) +#define CCM_CSCR_MCU (1 << 16) +#define CCM_CSCR_OSC26MDIV (1 << 4) +#define CCM_CSCR_OSC26M (1 << 3) +#define CCM_CSCR_FPM (1 << 2) +#define CCM_CSCR_SPEN (1 << 1) +#define CCM_CSCR_MPEN (1 << 0) + +/* i.MX27 TO 2+ */ +#define CCM_CSCR_ARM_SRC (1 << 15) + +#define CCM_SPCTL1_LF (1 << 15) +#define CCM_SPCTL1_BRMO (1 << 6) + +static struct clk mpll_main1_clk, mpll_main2_clk; + +static int clk_pccr_enable(struct clk *clk) +{ + unsigned long reg; + + if (!clk->enable_reg) + return 0; + + reg = __raw_readl(clk->enable_reg); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void clk_pccr_disable(struct clk *clk) +{ + unsigned long reg; + + if (!clk->enable_reg) + return; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static int clk_spll_enable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(CCM_CSCR); + reg |= CCM_CSCR_SPEN; + __raw_writel(reg, CCM_CSCR); + + while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF)); + + return 0; +} + +static void clk_spll_disable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(CCM_CSCR); + reg &= ~CCM_CSCR_SPEN; + __raw_writel(reg, CCM_CSCR); +} + +static int clk_cpu_set_parent(struct clk *clk, struct clk *parent) +{ + int cscr = __raw_readl(CCM_CSCR); + + if (clk->parent == parent) + return 0; + + if (mx27_revision() >= CHIP_REV_2_0) { + if (parent == &mpll_main1_clk) { + cscr |= CCM_CSCR_ARM_SRC; + } else { + if (parent == &mpll_main2_clk) + cscr &= ~CCM_CSCR_ARM_SRC; + else + return -EINVAL; + } + __raw_writel(cscr, CCM_CSCR); + clk->parent = parent; + return 0; + } + return -ENODEV; +} + +static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate) +{ + int div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (parent_rate % rate) + div++; + + if (div > 4) + div = 4; + + return parent_rate / div; +} + +static int set_rate_cpu(struct clk *clk, unsigned long rate) +{ + unsigned int div; + uint32_t reg; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if (div > 4 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + + div--; + + reg = __raw_readl(CCM_CSCR); + if (mx27_revision() >= CHIP_REV_2_0) { + reg &= ~(3 << 12); + reg |= div << 12; + reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN); + __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR); + } else { + printk(KERN_ERR "Can't set CPU frequency!\n"); + } + + return 0; +} + +static unsigned long round_rate_per(struct clk *clk, unsigned long rate) +{ + u32 div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (parent_rate % rate) + div++; + + if (div > 64) + div = 64; + + return parent_rate / div; +} + +static int set_rate_per(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + if (clk->id < 0 || clk->id > 3) + return -EINVAL; + + div = parent_rate / rate; + if (div > 64 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + div--; + + reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3)); + reg |= div << (clk->id << 3); + __raw_writel(reg, CCM_PCDR1); + + return 0; +} + +static unsigned long get_rate_usb(struct clk *clk) +{ + unsigned long usb_pdf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7; + + return parent_rate / (usb_pdf + 1U); +} + +static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf) +{ + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + if (mx27_revision() >= CHIP_REV_2_0) + pdf += 4; /* MX27 TO2+ */ + else + pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ + + return 2UL * parent_rate / pdf; +} + +static unsigned long get_rate_ssi1(struct clk *clk) +{ + return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f); +} + +static unsigned long get_rate_ssi2(struct clk *clk) +{ + return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f); +} + +static unsigned long get_rate_nfc(struct clk *clk) +{ + unsigned long nfc_pdf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + if (mx27_revision() >= CHIP_REV_2_0) + nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf; + else + nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf; + + return parent_rate / (nfc_pdf + 1); +} + +static unsigned long get_rate_vpu(struct clk *clk) +{ + unsigned long vpu_pdf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + if (mx27_revision() >= CHIP_REV_2_0) { + vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f; + vpu_pdf += 4; + } else { + vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf; + vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf; + } + + return 2UL * parent_rate / vpu_pdf; +} + +static unsigned long round_rate_parent(struct clk *clk, unsigned long rate) +{ + return clk->parent->round_rate(clk->parent, rate); +} + +static unsigned long get_rate_parent(struct clk *clk) +{ + return clk_get_rate(clk->parent); +} + +static int set_rate_parent(struct clk *clk, unsigned long rate) +{ + return clk->parent->set_rate(clk->parent, rate); +} + +/* in Hz */ +static unsigned long external_high_reference = 26000000; + +static unsigned long get_rate_high_reference(struct clk *clk) +{ + return external_high_reference; +} + +/* in Hz */ +static unsigned long external_low_reference = 32768; + +static unsigned long get_rate_low_reference(struct clk *clk) +{ + return external_low_reference; +} + +static unsigned long get_rate_fpm(struct clk *clk) +{ + return clk_get_rate(clk->parent) * 1024; +} + +static unsigned long get_rate_mpll(struct clk *clk) +{ + return mxc_decode_pll(__raw_readl(CCM_MPCTL0), + clk_get_rate(clk->parent)); +} + +static unsigned long get_rate_mpll_main(struct clk *clk) +{ + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + /* i.MX27 TO2: + * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2 + * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3 + */ + if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) + return 2UL * parent_rate / 3UL; + + return parent_rate; +} + +static unsigned long get_rate_spll(struct clk *clk) +{ + uint32_t reg; + unsigned long rate; + + rate = clk_get_rate(clk->parent); + + reg = __raw_readl(CCM_SPCTL0); + + /* On TO2 we have to write the value back. Otherwise we + * read 0 from this register the next time. + */ + if (mx27_revision() >= CHIP_REV_2_0) + __raw_writel(reg, CCM_SPCTL0); + + return mxc_decode_pll(reg, rate); +} + +static unsigned long get_rate_cpu(struct clk *clk) +{ + u32 div; + unsigned long rate; + + if (mx27_revision() >= CHIP_REV_2_0) + div = (__raw_readl(CCM_CSCR) >> 12) & 0x3; + else + div = (__raw_readl(CCM_CSCR) >> 13) & 0x7; + + rate = clk_get_rate(clk->parent); + return rate / (div + 1); +} + +static unsigned long get_rate_ahb(struct clk *clk) +{ + unsigned long rate, bclk_pdf; + + if (mx27_revision() >= CHIP_REV_2_0) + bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3; + else + bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf; + + rate = clk_get_rate(clk->parent); + return rate / (bclk_pdf + 1); +} + +static unsigned long get_rate_ipg(struct clk *clk) +{ + unsigned long rate, ipg_pdf; + + if (mx27_revision() >= CHIP_REV_2_0) + return clk_get_rate(clk->parent); + else + ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1; + + rate = clk_get_rate(clk->parent); + return rate / (ipg_pdf + 1); +} + +static unsigned long get_rate_per(struct clk *clk) +{ + unsigned long perclk_pdf, parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + if (clk->id < 0 || clk->id > 3) + return 0; + + perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f; + + return parent_rate / (perclk_pdf + 1); +} + +/* + * the high frequency external clock reference + * Default case is 26MHz. Could be changed at runtime + * with a call to change_external_high_reference() + */ +static struct clk ckih_clk = { + .get_rate = get_rate_high_reference, +}; + +static struct clk mpll_clk = { + .parent = &ckih_clk, + .get_rate = get_rate_mpll, +}; + +/* For i.MX27 TO2, it is the MPLL path 1 of ARM core + * It provides the clock source whose rate is same as MPLL + */ +static struct clk mpll_main1_clk = { + .id = 0, + .parent = &mpll_clk, + .get_rate = get_rate_mpll_main, +}; + +/* For i.MX27 TO2, it is the MPLL path 2 of ARM core + * It provides the clock source whose rate is same MPLL * 2 / 3 + */ +static struct clk mpll_main2_clk = { + .id = 1, + .parent = &mpll_clk, + .get_rate = get_rate_mpll_main, +}; + +static struct clk ahb_clk = { + .parent = &mpll_main2_clk, + .get_rate = get_rate_ahb, +}; + +static struct clk ipg_clk = { + .parent = &ahb_clk, + .get_rate = get_rate_ipg, +}; + +static struct clk cpu_clk = { + .parent = &mpll_main2_clk, + .set_parent = clk_cpu_set_parent, + .round_rate = round_rate_cpu, + .get_rate = get_rate_cpu, + .set_rate = set_rate_cpu, +}; + +static struct clk spll_clk = { + .parent = &ckih_clk, + .get_rate = get_rate_spll, + .enable = clk_spll_enable, + .disable = clk_spll_disable, +}; + +/* + * the low frequency external clock reference + * Default case is 32.768kHz. + */ +static struct clk ckil_clk = { + .get_rate = get_rate_low_reference, +}; + +/* Output of frequency pre multiplier */ +static struct clk fpm_clk = { + .parent = &ckil_clk, + .get_rate = get_rate_fpm, +}; + +#define PCCR0 CCM_PCCR0 +#define PCCR1 CCM_PCCR1 + +#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \ + static struct clk name = { \ + .id = i, \ + .enable_reg = er, \ + .enable_shift = es, \ + .get_rate = gr, \ + .enable = clk_pccr_enable, \ + .disable = clk_pccr_disable, \ + .secondary = s, \ + .parent = p, \ + } + +#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \ + static struct clk name = { \ + .id = i, \ + .enable_reg = er, \ + .enable_shift = es, \ + .get_rate = get_rate_##getsetround, \ + .set_rate = set_rate_##getsetround, \ + .round_rate = round_rate_##getsetround, \ + .enable = clk_pccr_enable, \ + .disable = clk_pccr_disable, \ + .secondary = s, \ + .parent = p, \ + } + +/* Forward declaration to keep the following list in order */ +static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1, + dma_clk1, lcdc_clk2, vpu_clk1; + +/* All clocks we can gate through PCCRx in the order of PCCRx bits */ +DEFINE_CLOCK(ssi2_clk1, 1, PCCR0, 0, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(ssi1_clk1, 0, PCCR0, 1, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(slcdc_clk, 0, PCCR0, 2, NULL, &slcdc_clk1, &ahb_clk); +DEFINE_CLOCK(sdhc3_clk1, 0, PCCR0, 3, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(sdhc2_clk1, 0, PCCR0, 4, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(sdhc1_clk1, 0, PCCR0, 5, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(scc_clk, 0, PCCR0, 6, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(sahara2_clk, 0, PCCR0, 7, NULL, &sahara2_clk1, &ahb_clk); +DEFINE_CLOCK(rtic_clk, 0, PCCR0, 8, NULL, &rtic_clk1, &ahb_clk); +DEFINE_CLOCK(rtc_clk, 0, PCCR0, 9, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(pwm_clk1, 0, PCCR0, 11, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(owire_clk, 0, PCCR0, 12, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(mstick_clk1, 0, PCCR0, 13, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(lcdc_clk1, 0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk); +DEFINE_CLOCK(kpp_clk, 0, PCCR0, 15, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(iim_clk, 0, PCCR0, 16, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(i2c2_clk, 1, PCCR0, 17, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(i2c1_clk, 0, PCCR0, 18, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(gpt6_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(gpt5_clk1, 0, PCCR0, 20, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(gpt4_clk1, 0, PCCR0, 21, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(gpt3_clk1, 0, PCCR0, 22, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(gpt2_clk1, 0, PCCR0, 23, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(gpt1_clk1, 0, PCCR0, 24, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(gpio_clk, 0, PCCR0, 25, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(fec_clk, 0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk); +DEFINE_CLOCK(emma_clk, 0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk); +DEFINE_CLOCK(dma_clk, 0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk); +DEFINE_CLOCK(cspi13_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(cspi2_clk1, 0, PCCR0, 30, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(cspi1_clk1, 0, PCCR0, 31, NULL, NULL, &ipg_clk); + +DEFINE_CLOCK(mstick_clk, 0, PCCR1, 2, NULL, &mstick_clk1, &ipg_clk); +DEFINE_CLOCK(nfc_clk, 0, PCCR1, 3, get_rate_nfc, NULL, &cpu_clk); +DEFINE_CLOCK(ssi2_clk, 1, PCCR1, 4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk); +DEFINE_CLOCK(ssi1_clk, 0, PCCR1, 5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk); +DEFINE_CLOCK(vpu_clk, 0, PCCR1, 6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk); +DEFINE_CLOCK1(per4_clk, 3, PCCR1, 7, per, NULL, &mpll_main2_clk); +DEFINE_CLOCK1(per3_clk, 2, PCCR1, 8, per, NULL, &mpll_main2_clk); +DEFINE_CLOCK1(per2_clk, 1, PCCR1, 9, per, NULL, &mpll_main2_clk); +DEFINE_CLOCK1(per1_clk, 0, PCCR1, 10, per, NULL, &mpll_main2_clk); +DEFINE_CLOCK(usb_clk1, 0, PCCR1, 11, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(slcdc_clk1, 0, PCCR1, 12, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(rtic_clk1, 0, PCCR1, 14, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(lcdc_clk2, 0, PCCR1, 15, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(vpu_clk1, 0, PCCR1, 16, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(fec_clk1, 0, PCCR1, 17, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(emma_clk1, 0, PCCR1, 18, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(emi_clk, 0, PCCR1, 19, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(ata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk); +DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(uart5_clk1, 0, PCCR1, 27, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(uart4_clk1, 0, PCCR1, 28, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(uart3_clk1, 0, PCCR1, 29, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk); + +/* Clocks we cannot directly gate, but drivers need their rates */ +DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk); +DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk); +DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk); +DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk); +DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk); +DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk); +DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk); +DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk); +DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk); +DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk); +DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk); +DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk); +DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk); +DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk); +DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk); +DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk); +DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk); +DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk); +DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk); +DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk); +DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk); + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + }, + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) + _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) + _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) + _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk) + _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk) + _REGISTER_CLOCK("imx-uart.5", NULL, uart6_clk) + _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk) + _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk) + _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk) + _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk) + _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk) + _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk) + _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk) + _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) + _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) + _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk) + _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) + _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) + _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) + _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) + _REGISTER_CLOCK(NULL, "csi", csi_clk) + _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk) + _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1) + _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk) + _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1) + _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk) + _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1) + _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk) + _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1) + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) + _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) + _REGISTER_CLOCK(NULL, "vpu", vpu_clk) + _REGISTER_CLOCK(NULL, "dma", dma_clk) + _REGISTER_CLOCK(NULL, "rtic", rtic_clk) + _REGISTER_CLOCK(NULL, "brom", brom_clk) + _REGISTER_CLOCK(NULL, "emma", emma_clk) + _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk) + _REGISTER_CLOCK("fec.0", NULL, fec_clk) + _REGISTER_CLOCK(NULL, "emi", emi_clk) + _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) + _REGISTER_CLOCK(NULL, "ata", ata_clk) + _REGISTER_CLOCK(NULL, "mstick", mstick_clk) + _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) + _REGISTER_CLOCK(NULL, "gpio", gpio_clk) + _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) + _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) +