From 9be58f317d79278afc23186d861ada774cf386ea Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 12 Nov 2010 13:49:27 -0800 Subject: msm: smd: Reduce driver log chatter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MSM smd driver logs numerous messages during startup that are useful for debug purposes. Change some of these to pr_debug() to match their purpose, and remove others that aren't really useful. Cc: Brian Swetland Cc: Arve Hjønnevåg Signed-off-by: David Brown Signed-off-by: Daniel Walker --- arch/arm/mach-msm/smd.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c index f07dc7c738f..657be73297d 100644 --- a/arch/arm/mach-msm/smd.c +++ b/arch/arm/mach-msm/smd.c @@ -14,6 +14,8 @@ * */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include #include #include @@ -89,7 +91,7 @@ static void smd_diag(void) x = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG); if (x != 0) { x[SZ_DIAG_ERR_MSG - 1] = 0; - pr_info("smem: DIAG '%s'\n", x); + pr_debug("DIAG '%s'\n", x); } } @@ -312,7 +314,7 @@ static void smd_state_change(struct smd_channel *ch, { ch->last_state = next; - pr_info("SMD: ch %d %d -> %d\n", ch->n, last, next); + pr_debug("ch %d %d -> %d\n", ch->n, last, next); switch (next) { case SMD_SS_OPENING: @@ -601,7 +603,7 @@ static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type) ch->pdev.name = ch->name; ch->pdev.id = -1; - pr_info("smd_alloc_channel() cid=%02d size=%05d '%s'\n", + pr_debug("smd_alloc_channel() cid=%02d size=%05d '%s'\n", ch->n, ch->fifo_size, ch->name); mutex_lock(&smd_creation_mutex); @@ -621,7 +623,7 @@ static void smd_channel_probe_worker(struct work_struct *work) shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64); if (!shared) { - pr_err("smd: cannot find allocation table\n"); + pr_err("cannot find allocation table\n"); return; } for (n = 0; n < 64; n++) { @@ -725,8 +727,6 @@ int smd_close(smd_channel_t *ch) { unsigned long flags; - pr_info("smd_close(%p)\n", ch); - if (ch == 0) return -1; @@ -939,7 +939,6 @@ int smsm_set_sleep_duration(uint32_t delay) int smd_core_init(void) { int r; - pr_info("smd_core_init()\n"); /* wait for essential items to be initialized */ for (;;) { @@ -992,15 +991,11 @@ int smd_core_init(void) smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0); #endif - pr_info("smd_core_init() done\n"); - return 0; } static int __devinit msm_smd_probe(struct platform_device *pdev) { - pr_info("smd_init()\n"); - /* * If we haven't waited for the ARM9 to boot up till now, * then we need to wait here. Otherwise this should just -- cgit v1.2.3-18-g5258 From 5d1394bb6b781df8148565783b0671f9b11500b7 Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 12 Nov 2010 13:49:51 -0800 Subject: msm: sirc: remove some unused variables Eliminate some unreferenced variables. arch/arm/mach-msm/sirc.c:43: warning: 'save_type' defined but not used arch/arm/mach-msm/sirc.c:44: warning: 'save_polarity' defined but not used Signed-off-by: David Brown [dwalker@codeaurora.org: changed the commit text a little.] Signed-off-by: Daniel Walker --- arch/arm/mach-msm/sirc.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c index b0794524ba6..152eefda3ce 100644 --- a/arch/arm/mach-msm/sirc.c +++ b/arch/arm/mach-msm/sirc.c @@ -40,9 +40,6 @@ static struct sirc_cascade_regs sirc_reg_table[] = { } }; -static unsigned int save_type; -static unsigned int save_polarity; - /* Mask off the given interrupt. Keep the int_enable mask in sync with the enable reg, so it can be restored after power collapse. */ static void sirc_irq_mask(unsigned int irq) -- cgit v1.2.3-18-g5258 From d2c5d2145f127fffb7498bee943a480de66910ff Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 12 Nov 2010 13:49:52 -0800 Subject: msm: smd: ifdef adjustment to remove unused variables Put some variables inside of the same ifdef as the code that uses them. arch/arm/mach-msm/smd_debug.c: In function 'smsm_print_sleep_info': arch/arm/mach-msm/smd_debug.c:274: warning: unused variable 'int_info' arch/arm/mach-msm/smd_debug.c:273: warning: unused variable 'gpio' Signed-off-by: David Brown [dwalker@codeaurora.org: changed the commit text a little.] Signed-off-by: Daniel Walker --- arch/arm/mach-msm/smd_debug.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c index f91c3b7bc65..8736afff82f 100644 --- a/arch/arm/mach-msm/smd_debug.c +++ b/arch/arm/mach-msm/smd_debug.c @@ -270,8 +270,10 @@ void smsm_print_sleep_info(void) { unsigned long flags; uint32_t *ptr; +#ifndef CONFIG_ARCH_MSM_SCORPION struct tramp_gpio_smem *gpio; struct smsm_interrupt_info *int_info; +#endif spin_lock_irqsave(&smem_lock, flags); -- cgit v1.2.3-18-g5258 From 44d4a4f784d0e1a50b3f1fc52bd6a661846abdc5 Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 12 Nov 2010 13:49:53 -0800 Subject: msm: make constant unsigned long to correct format warning Define VMALLOC_END as an unsigned long to match expected type. Eliminates a warning: arch/arm/mm/init.c: In function 'mem_init': arch/arm/mm/init.c:606: warning: format '%08lx' expects type 'long unsigned int', but argument 12 has type 'unsigned int' Signed-off-by: David Brown Signed-off-by: Daniel Walker --- arch/arm/mach-msm/include/mach/vmalloc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h index 31a32ad062d..d138448eff1 100644 --- a/arch/arm/mach-msm/include/mach/vmalloc.h +++ b/arch/arm/mach-msm/include/mach/vmalloc.h @@ -16,7 +16,7 @@ #ifndef __ASM_ARCH_MSM_VMALLOC_H #define __ASM_ARCH_MSM_VMALLOC_H -#define VMALLOC_END 0xd0000000 +#define VMALLOC_END 0xd0000000UL #endif -- cgit v1.2.3-18-g5258 From 4916a1083290edfb6cc53aa134f00597447de1ce Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Tue, 9 Nov 2010 15:41:29 +0530 Subject: msm: io: Export __msm_ioremap This is required for modules to use ioremap() Signed-off-by: Pavankumar Kondeti Signed-off-by: Daniel Walker --- arch/arm/mach-msm/io.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index d36b6107414..f912d7bf188 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -163,3 +163,4 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) return __arm_ioremap_caller(phys_addr, size, mtype, __builtin_return_address(0)); } +EXPORT_SYMBOL(__msm_ioremap); -- cgit v1.2.3-18-g5258 From 0cc2fc1f2f5f1fcf6699b43d73ca3e753ef63582 Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Wed, 24 Nov 2010 11:53:51 -0800 Subject: msm: gpio: Add v2 gpio support to MSM SoCs. Beginning with the MSM8x60, the hardware block responsible for gpio support changes. Provide gpiolib support for the new v2 architecture. Cc: Baruch Siach Cc: Pavan Kondeti Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/Makefile | 4 +- arch/arm/mach-msm/gpio-v2.c | 163 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-msm/gpio-v2.c (limited to 'arch') diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index b5a7b07a44f..4a1a7ea97c2 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -28,6 +28,8 @@ obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o -ifndef CONFIG_MSM_V2_TLMM +ifdef CONFIG_MSM_V2_TLMM +obj-y += gpio-v2.o +else obj-y += gpio.o endif diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c new file mode 100644 index 00000000000..d907af68c8e --- /dev/null +++ b/arch/arm/mach-msm/gpio-v2.c @@ -0,0 +1,163 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include "gpiomux.h" + +/* Bits of interest in the GPIO_IN_OUT register. + */ +enum { + GPIO_IN_BIT = 0, + GPIO_OUT_BIT = 1 +}; + +/* Bits of interest in the GPIO_CFG register. + */ +enum { + GPIO_OE_BIT = 9, +}; + +#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio))) +#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio))) + +static DEFINE_SPINLOCK(tlmm_lock); + +static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN_BIT); +} + +static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +{ + writel(val ? BIT(GPIO_OUT_BIT) : 0, GPIO_IN_OUT(offset)); +} + +static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + writel(readl(GPIO_CONFIG(offset)) & ~BIT(GPIO_OE_BIT), + GPIO_CONFIG(offset)); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); + return 0; +} + +static int msm_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, + int val) +{ + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + msm_gpio_set(chip, offset, val); + writel(readl(GPIO_CONFIG(offset)) | BIT(GPIO_OE_BIT), + GPIO_CONFIG(offset)); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); + return 0; +} + +static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return msm_gpiomux_get(chip->base + offset); +} + +static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + msm_gpiomux_put(chip->base + offset); +} + +static struct gpio_chip msm_gpio = { + .base = 0, + .ngpio = NR_GPIO_IRQS, + .direction_input = msm_gpio_direction_input, + .direction_output = msm_gpio_direction_output, + .get = msm_gpio_get, + .set = msm_gpio_set, + .request = msm_gpio_request, + .free = msm_gpio_free, +}; + +static int __devinit msm_gpio_probe(struct platform_device *dev) +{ + int ret; + + msm_gpio.label = dev->name; + ret = gpiochip_add(&msm_gpio); + + return ret; +} + +static int __devexit msm_gpio_remove(struct platform_device *dev) +{ + int ret = gpiochip_remove(&msm_gpio); + + if (ret < 0) + return ret; + + set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); + + return 0; +} + +static struct platform_driver msm_gpio_driver = { + .probe = msm_gpio_probe, + .remove = __devexit_p(msm_gpio_remove), + .driver = { + .name = "msmgpio", + .owner = THIS_MODULE, + }, +}; + +static struct platform_device msm_device_gpio = { + .name = "msmgpio", + .id = -1, +}; + +static int __init msm_gpio_init(void) +{ + int rc; + + rc = platform_driver_register(&msm_gpio_driver); + if (!rc) { + rc = platform_device_register(&msm_device_gpio); + if (rc) + platform_driver_unregister(&msm_gpio_driver); + } + + return rc; +} + +static void __exit msm_gpio_exit(void) +{ + platform_device_unregister(&msm_device_gpio); + platform_driver_unregister(&msm_gpio_driver); +} + +postcore_initcall(msm_gpio_init); +module_exit(msm_gpio_exit); + +MODULE_AUTHOR("Gregory Bean "); +MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:msmgpio"); -- cgit v1.2.3-18-g5258 From 70cc2c00d7471f21120befeb7fc107c856e3985b Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Wed, 24 Nov 2010 11:53:52 -0800 Subject: msm: gpio: Add irq support to v2 gpiolib. Complete the MSM v2 gpio subsystem by adding irq_chip. Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/gpio-v2.c | 309 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 286 insertions(+), 23 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c index d907af68c8e..0de19ec74e3 100644 --- a/arch/arm/mach-msm/gpio-v2.c +++ b/arch/arm/mach-msm/gpio-v2.c @@ -15,7 +15,13 @@ * 02110-1301, USA. * */ +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include #include +#include +#include #include #include #include @@ -27,29 +33,103 @@ /* Bits of interest in the GPIO_IN_OUT register. */ enum { - GPIO_IN_BIT = 0, - GPIO_OUT_BIT = 1 + GPIO_IN = 0, + GPIO_OUT = 1 +}; + +/* Bits of interest in the GPIO_INTR_STATUS register. + */ +enum { + INTR_STATUS = 0, }; /* Bits of interest in the GPIO_CFG register. */ enum { - GPIO_OE_BIT = 9, + GPIO_OE = 9, +}; + +/* Bits of interest in the GPIO_INTR_CFG register. + * When a GPIO triggers, two separate decisions are made, controlled + * by two separate flags. + * + * - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS + * register for that GPIO will be updated to reflect the triggering of that + * gpio. If this bit is 0, this register will not be updated. + * - Second, INTR_ENABLE controls whether an interrupt is triggered. + * + * If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt + * can be triggered but the status register will not reflect it. + */ +enum { + INTR_ENABLE = 0, + INTR_POL_CTL = 1, + INTR_DECT_CTL = 2, + INTR_RAW_STATUS_EN = 3, +}; + +/* Codes of interest in GPIO_INTR_CFG_SU. + */ +enum { + TARGET_PROC_SCORPION = 4, + TARGET_PROC_NONE = 7, }; + +#define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio))) #define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio))) #define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio))) +#define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio))) +#define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio))) + +/** + * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure + * + * @enabled_irqs: a bitmap used to optimize the summary-irq handler. By + * keeping track of which gpios are unmasked as irq sources, we avoid + * having to do readl calls on hundreds of iomapped registers each time + * the summary interrupt fires in order to locate the active interrupts. + * + * @wake_irqs: a bitmap for tracking which interrupt lines are enabled + * as wakeup sources. When the device is suspended, interrupts which are + * not wakeup sources are disabled. + * + * @dual_edge_irqs: a bitmap used to track which irqs are configured + * as dual-edge, as this is not supported by the hardware and requires + * some special handling in the driver. + */ +struct msm_gpio_dev { + struct gpio_chip gpio_chip; + DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS); + DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS); + DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS); +}; static DEFINE_SPINLOCK(tlmm_lock); +static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip) +{ + return container_of(chip, struct msm_gpio_dev, gpio_chip); +} + +static inline void set_gpio_bits(unsigned n, void __iomem *reg) +{ + writel(readl(reg) | n, reg); +} + +static inline void clear_gpio_bits(unsigned n, void __iomem *reg) +{ + writel(readl(reg) & ~n, reg); +} + static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) { - return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN_BIT); + return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN); } static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val) { - writel(val ? BIT(GPIO_OUT_BIT) : 0, GPIO_IN_OUT(offset)); + writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset)); } static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) @@ -57,8 +137,7 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) unsigned long irq_flags; spin_lock_irqsave(&tlmm_lock, irq_flags); - writel(readl(GPIO_CONFIG(offset)) & ~BIT(GPIO_OE_BIT), - GPIO_CONFIG(offset)); + clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); spin_unlock_irqrestore(&tlmm_lock, irq_flags); return 0; } @@ -71,8 +150,7 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, spin_lock_irqsave(&tlmm_lock, irq_flags); msm_gpio_set(chip, offset, val); - writel(readl(GPIO_CONFIG(offset)) | BIT(GPIO_OE_BIT), - GPIO_CONFIG(offset)); + set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); spin_unlock_irqrestore(&tlmm_lock, irq_flags); return 0; } @@ -87,30 +165,215 @@ static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) msm_gpiomux_put(chip->base + offset); } -static struct gpio_chip msm_gpio = { - .base = 0, - .ngpio = NR_GPIO_IRQS, - .direction_input = msm_gpio_direction_input, - .direction_output = msm_gpio_direction_output, - .get = msm_gpio_get, - .set = msm_gpio_set, - .request = msm_gpio_request, - .free = msm_gpio_free, +static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return MSM_GPIO_TO_INT(chip->base + offset); +} + +static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq) +{ + return irq - MSM_GPIO_TO_INT(chip->base); +} + +static struct msm_gpio_dev msm_gpio = { + .gpio_chip = { + .base = 0, + .ngpio = NR_GPIO_IRQS, + .direction_input = msm_gpio_direction_input, + .direction_output = msm_gpio_direction_output, + .get = msm_gpio_get, + .set = msm_gpio_set, + .to_irq = msm_gpio_to_irq, + .request = msm_gpio_request, + .free = msm_gpio_free, + }, +}; + +/* For dual-edge interrupts in software, since the hardware has no + * such support: + * + * At appropriate moments, this function may be called to flip the polarity + * settings of both-edge irq lines to try and catch the next edge. + * + * The attempt is considered successful if: + * - the status bit goes high, indicating that an edge was caught, or + * - the input value of the gpio doesn't change during the attempt. + * If the value changes twice during the process, that would cause the first + * test to fail but would force the second, as two opposite + * transitions would cause a detection no matter the polarity setting. + * + * The do-loop tries to sledge-hammer closed the timing hole between + * the initial value-read and the polarity-write - if the line value changes + * during that window, an interrupt is lost, the new polarity setting is + * incorrect, and the first success test will fail, causing a retry. + * + * Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c. + */ +static void msm_gpio_update_dual_edge_pos(unsigned gpio) +{ + int loop_limit = 100; + unsigned val, val2, intstat; + + do { + val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); + if (val) + clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); + else + set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); + val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); + intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS); + if (intstat || val == val2) + return; + } while (loop_limit-- > 0); + pr_err("dual-edge irq failed to stabilize, " + "interrupts dropped. %#08x != %#08x\n", + val, val2); +} + +static void msm_gpio_irq_ack(unsigned int irq) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + + writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); + if (test_bit(gpio, msm_gpio.dual_edge_irqs)) + msm_gpio_update_dual_edge_pos(gpio); +} + +static void msm_gpio_irq_mask(unsigned int irq) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio)); + clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); + __clear_bit(gpio, msm_gpio.enabled_irqs); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); +} + +static void msm_gpio_irq_unmask(unsigned int irq) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + __set_bit(gpio, msm_gpio.enabled_irqs); + set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); + writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio)); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); +} + +static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + unsigned long irq_flags; + uint32_t bits; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + + bits = readl(GPIO_INTR_CFG(gpio)); + + if (flow_type & IRQ_TYPE_EDGE_BOTH) { + bits |= BIT(INTR_DECT_CTL); + irq_desc[irq].handle_irq = handle_edge_irq; + if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) + __set_bit(gpio, msm_gpio.dual_edge_irqs); + else + __clear_bit(gpio, msm_gpio.dual_edge_irqs); + } else { + bits &= ~BIT(INTR_DECT_CTL); + irq_desc[irq].handle_irq = handle_level_irq; + __clear_bit(gpio, msm_gpio.dual_edge_irqs); + } + + if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) + bits |= BIT(INTR_POL_CTL); + else + bits &= ~BIT(INTR_POL_CTL); + + writel(bits, GPIO_INTR_CFG(gpio)); + + if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) + msm_gpio_update_dual_edge_pos(gpio); + + spin_unlock_irqrestore(&tlmm_lock, irq_flags); + + return 0; +} + +/* + * When the summary IRQ is raised, any number of GPIO lines may be high. + * It is the job of the summary handler to find all those GPIO lines + * which have been set as summary IRQ lines and which are triggered, + * and to call their interrupt handlers. + */ +static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + unsigned long i; + + for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); + i < NR_GPIO_IRQS; + i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) { + if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS)) + generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, + i)); + } + desc->chip->ack(irq); +} + +static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + + if (on) { + if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) + set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); + set_bit(gpio, msm_gpio.wake_irqs); + } else { + clear_bit(gpio, msm_gpio.wake_irqs); + if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) + set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); + } + + return 0; +} + +static struct irq_chip msm_gpio_irq_chip = { + .name = "msmgpio", + .mask = msm_gpio_irq_mask, + .unmask = msm_gpio_irq_unmask, + .ack = msm_gpio_irq_ack, + .set_type = msm_gpio_irq_set_type, + .set_wake = msm_gpio_irq_set_wake, }; static int __devinit msm_gpio_probe(struct platform_device *dev) { - int ret; + int i, irq, ret; + + bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS); + bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS); + bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS); + msm_gpio.gpio_chip.label = dev->name; + ret = gpiochip_add(&msm_gpio.gpio_chip); + if (ret < 0) + return ret; - msm_gpio.label = dev->name; - ret = gpiochip_add(&msm_gpio); + for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { + irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); + set_irq_chip(irq, &msm_gpio_irq_chip); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } - return ret; + set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, + msm_summary_irq_handler); + return 0; } static int __devexit msm_gpio_remove(struct platform_device *dev) { - int ret = gpiochip_remove(&msm_gpio); + int ret = gpiochip_remove(&msm_gpio.gpio_chip); if (ret < 0) return ret; -- cgit v1.2.3-18-g5258 From 23513c3b39207c569da2c8afdced62ec43b4a272 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:47 -0800 Subject: msm: iommu: Increase maximum MID size to 5 bits On msm8x60, the MID field on the AXI connection to the IOMMU can be up to five bits wide. Thus, allow the IOMMU context platform data to map up to 32 MIDs. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/include/mach/iommu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 218ef5732a2..17fc79fc8bc 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -26,7 +26,7 @@ * be present. These mappings are typically determined at design time and are * not expected to change at run time. */ -#define MAX_NUM_MIDS 16 +#define MAX_NUM_MIDS 32 /** * struct msm_iommu_dev - a single IOMMU hardware instance -- cgit v1.2.3-18-g5258 From c4bd2eebee37b885b47ec48961923b671148703f Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:48 -0800 Subject: msm: iomap: Addresses and IRQs for 2nd GFX core IOMMU Add register addresses and IRQ numbers for the IOMMU used for the second 2D graphics core. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/include/mach/irqs-8x60.h | 7 ++++++- arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h index 36074cfc9ad..f65841c74c0 100644 --- a/arch/arm/mach-msm/include/mach/irqs-8x60.h +++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h @@ -237,7 +237,12 @@ #define GSBI11_QUP_IRQ (GIC_SPI_START + 194) #define INT_UART12DM_IRQ (GIC_SPI_START + 195) #define GSBI12_QUP_IRQ (GIC_SPI_START + 196) -/*SPI 197 to 216 arent used in 8x60*/ + +/*SPI 197 to 209 arent used in 8x60*/ +#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) +#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) + +/*SPI 212 to 216 arent used in 8x60*/ #define SMPSS_SPARE_1 (GIC_SPI_START + 217) #define SMPSS_SPARE_2 (GIC_SPI_START + 218) #define SMPSS_SPARE_3 (GIC_SPI_START + 219) diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 45bab50e3ee..7c43a9bff1a 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -98,4 +98,7 @@ #define MSM_IOMMU_GFX2D0_PHYS 0x07D00000 #define MSM_IOMMU_GFX2D0_SIZE SZ_1M +#define MSM_IOMMU_GFX2D1_PHYS 0x07E00000 +#define MSM_IOMMU_GFX2D1_SIZE SZ_1M + #endif -- cgit v1.2.3-18-g5258 From 12943325cda3be10819e047cd8b5032a4fef6080 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:49 -0800 Subject: msm: iommu: Use more consistent naming in platform data Rename all the IOMMU platform devices so that the names are more consistent with the rest of the codebase. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/devices-msm8x60-iommu.c | 136 +++++++++++++++--------------- 1 file changed, 68 insertions(+), 68 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c index 89b9d4437e9..9e657e0ee18 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c @@ -259,55 +259,55 @@ static struct platform_device msm_root_iommu_dev = { .id = -1, }; -static struct msm_iommu_dev jpegd_smmu = { +static struct msm_iommu_dev jpegd_iommu = { .name = "jpegd", .clk_rate = -1 }; -static struct msm_iommu_dev vpe_smmu = { +static struct msm_iommu_dev vpe_iommu = { .name = "vpe" }; -static struct msm_iommu_dev mdp0_smmu = { +static struct msm_iommu_dev mdp0_iommu = { .name = "mdp0" }; -static struct msm_iommu_dev mdp1_smmu = { +static struct msm_iommu_dev mdp1_iommu = { .name = "mdp1" }; -static struct msm_iommu_dev rot_smmu = { +static struct msm_iommu_dev rot_iommu = { .name = "rot" }; -static struct msm_iommu_dev ijpeg_smmu = { +static struct msm_iommu_dev ijpeg_iommu = { .name = "ijpeg" }; -static struct msm_iommu_dev vfe_smmu = { +static struct msm_iommu_dev vfe_iommu = { .name = "vfe", .clk_rate = -1 }; -static struct msm_iommu_dev vcodec_a_smmu = { +static struct msm_iommu_dev vcodec_a_iommu = { .name = "vcodec_a" }; -static struct msm_iommu_dev vcodec_b_smmu = { +static struct msm_iommu_dev vcodec_b_iommu = { .name = "vcodec_b" }; -static struct msm_iommu_dev gfx3d_smmu = { +static struct msm_iommu_dev gfx3d_iommu = { .name = "gfx3d", .clk_rate = 27000000 }; -static struct msm_iommu_dev gfx2d0_smmu = { +static struct msm_iommu_dev gfx2d0_iommu = { .name = "gfx2d0", .clk_rate = 27000000 }; -static struct platform_device msm_device_smmu_jpegd = { +static struct platform_device msm_device_iommu_jpegd = { .name = "msm_iommu", .id = 0, .dev = { @@ -317,7 +317,7 @@ static struct platform_device msm_device_smmu_jpegd = { .resource = msm_iommu_jpegd_resources, }; -static struct platform_device msm_device_smmu_vpe = { +static struct platform_device msm_device_iommu_vpe = { .name = "msm_iommu", .id = 1, .dev = { @@ -327,7 +327,7 @@ static struct platform_device msm_device_smmu_vpe = { .resource = msm_iommu_vpe_resources, }; -static struct platform_device msm_device_smmu_mdp0 = { +static struct platform_device msm_device_iommu_mdp0 = { .name = "msm_iommu", .id = 2, .dev = { @@ -337,7 +337,7 @@ static struct platform_device msm_device_smmu_mdp0 = { .resource = msm_iommu_mdp0_resources, }; -static struct platform_device msm_device_smmu_mdp1 = { +static struct platform_device msm_device_iommu_mdp1 = { .name = "msm_iommu", .id = 3, .dev = { @@ -347,7 +347,7 @@ static struct platform_device msm_device_smmu_mdp1 = { .resource = msm_iommu_mdp1_resources, }; -static struct platform_device msm_device_smmu_rot = { +static struct platform_device msm_device_iommu_rot = { .name = "msm_iommu", .id = 4, .dev = { @@ -357,7 +357,7 @@ static struct platform_device msm_device_smmu_rot = { .resource = msm_iommu_rot_resources, }; -static struct platform_device msm_device_smmu_ijpeg = { +static struct platform_device msm_device_iommu_ijpeg = { .name = "msm_iommu", .id = 5, .dev = { @@ -367,7 +367,7 @@ static struct platform_device msm_device_smmu_ijpeg = { .resource = msm_iommu_ijpeg_resources, }; -static struct platform_device msm_device_smmu_vfe = { +static struct platform_device msm_device_iommu_vfe = { .name = "msm_iommu", .id = 6, .dev = { @@ -377,7 +377,7 @@ static struct platform_device msm_device_smmu_vfe = { .resource = msm_iommu_vfe_resources, }; -static struct platform_device msm_device_smmu_vcodec_a = { +static struct platform_device msm_device_iommu_vcodec_a = { .name = "msm_iommu", .id = 7, .dev = { @@ -387,7 +387,7 @@ static struct platform_device msm_device_smmu_vcodec_a = { .resource = msm_iommu_vcodec_a_resources, }; -static struct platform_device msm_device_smmu_vcodec_b = { +static struct platform_device msm_device_iommu_vcodec_b = { .name = "msm_iommu", .id = 8, .dev = { @@ -397,7 +397,7 @@ static struct platform_device msm_device_smmu_vcodec_b = { .resource = msm_iommu_vcodec_b_resources, }; -static struct platform_device msm_device_smmu_gfx3d = { +static struct platform_device msm_device_iommu_gfx3d = { .name = "msm_iommu", .id = 9, .dev = { @@ -407,7 +407,7 @@ static struct platform_device msm_device_smmu_gfx3d = { .resource = msm_iommu_gfx3d_resources, }; -static struct platform_device msm_device_smmu_gfx2d0 = { +static struct platform_device msm_device_iommu_gfx2d0 = { .name = "msm_iommu", .id = 10, .dev = { @@ -553,7 +553,7 @@ static struct platform_device msm_device_jpegd_src_ctx = { .name = "msm_iommu_ctx", .id = 0, .dev = { - .parent = &msm_device_smmu_jpegd.dev, + .parent = &msm_device_iommu_jpegd.dev, }, }; @@ -561,7 +561,7 @@ static struct platform_device msm_device_jpegd_dst_ctx = { .name = "msm_iommu_ctx", .id = 1, .dev = { - .parent = &msm_device_smmu_jpegd.dev, + .parent = &msm_device_iommu_jpegd.dev, }, }; @@ -569,7 +569,7 @@ static struct platform_device msm_device_vpe_src_ctx = { .name = "msm_iommu_ctx", .id = 2, .dev = { - .parent = &msm_device_smmu_vpe.dev, + .parent = &msm_device_iommu_vpe.dev, }, }; @@ -577,7 +577,7 @@ static struct platform_device msm_device_vpe_dst_ctx = { .name = "msm_iommu_ctx", .id = 3, .dev = { - .parent = &msm_device_smmu_vpe.dev, + .parent = &msm_device_iommu_vpe.dev, }, }; @@ -585,7 +585,7 @@ static struct platform_device msm_device_mdp_vg1_ctx = { .name = "msm_iommu_ctx", .id = 4, .dev = { - .parent = &msm_device_smmu_mdp0.dev, + .parent = &msm_device_iommu_mdp0.dev, }, }; @@ -593,7 +593,7 @@ static struct platform_device msm_device_mdp_rgb1_ctx = { .name = "msm_iommu_ctx", .id = 5, .dev = { - .parent = &msm_device_smmu_mdp0.dev, + .parent = &msm_device_iommu_mdp0.dev, }, }; @@ -601,7 +601,7 @@ static struct platform_device msm_device_mdp_vg2_ctx = { .name = "msm_iommu_ctx", .id = 6, .dev = { - .parent = &msm_device_smmu_mdp1.dev, + .parent = &msm_device_iommu_mdp1.dev, }, }; @@ -609,7 +609,7 @@ static struct platform_device msm_device_mdp_rgb2_ctx = { .name = "msm_iommu_ctx", .id = 7, .dev = { - .parent = &msm_device_smmu_mdp1.dev, + .parent = &msm_device_iommu_mdp1.dev, }, }; @@ -617,7 +617,7 @@ static struct platform_device msm_device_rot_src_ctx = { .name = "msm_iommu_ctx", .id = 8, .dev = { - .parent = &msm_device_smmu_rot.dev, + .parent = &msm_device_iommu_rot.dev, }, }; @@ -625,7 +625,7 @@ static struct platform_device msm_device_rot_dst_ctx = { .name = "msm_iommu_ctx", .id = 9, .dev = { - .parent = &msm_device_smmu_rot.dev, + .parent = &msm_device_iommu_rot.dev, }, }; @@ -633,7 +633,7 @@ static struct platform_device msm_device_ijpeg_src_ctx = { .name = "msm_iommu_ctx", .id = 10, .dev = { - .parent = &msm_device_smmu_ijpeg.dev, + .parent = &msm_device_iommu_ijpeg.dev, }, }; @@ -641,7 +641,7 @@ static struct platform_device msm_device_ijpeg_dst_ctx = { .name = "msm_iommu_ctx", .id = 11, .dev = { - .parent = &msm_device_smmu_ijpeg.dev, + .parent = &msm_device_iommu_ijpeg.dev, }, }; @@ -649,7 +649,7 @@ static struct platform_device msm_device_vfe_imgwr_ctx = { .name = "msm_iommu_ctx", .id = 12, .dev = { - .parent = &msm_device_smmu_vfe.dev, + .parent = &msm_device_iommu_vfe.dev, }, }; @@ -657,7 +657,7 @@ static struct platform_device msm_device_vfe_misc_ctx = { .name = "msm_iommu_ctx", .id = 13, .dev = { - .parent = &msm_device_smmu_vfe.dev, + .parent = &msm_device_iommu_vfe.dev, }, }; @@ -665,7 +665,7 @@ static struct platform_device msm_device_vcodec_a_stream_ctx = { .name = "msm_iommu_ctx", .id = 14, .dev = { - .parent = &msm_device_smmu_vcodec_a.dev, + .parent = &msm_device_iommu_vcodec_a.dev, }, }; @@ -673,7 +673,7 @@ static struct platform_device msm_device_vcodec_a_mm1_ctx = { .name = "msm_iommu_ctx", .id = 15, .dev = { - .parent = &msm_device_smmu_vcodec_a.dev, + .parent = &msm_device_iommu_vcodec_a.dev, }, }; @@ -681,7 +681,7 @@ static struct platform_device msm_device_vcodec_b_mm2_ctx = { .name = "msm_iommu_ctx", .id = 16, .dev = { - .parent = &msm_device_smmu_vcodec_b.dev, + .parent = &msm_device_iommu_vcodec_b.dev, }, }; @@ -689,7 +689,7 @@ static struct platform_device msm_device_gfx3d_rbpa_ctx = { .name = "msm_iommu_ctx", .id = 17, .dev = { - .parent = &msm_device_smmu_gfx3d.dev, + .parent = &msm_device_iommu_gfx3d.dev, }, }; @@ -697,7 +697,7 @@ static struct platform_device msm_device_gfx3d_cpvgttc_ctx = { .name = "msm_iommu_ctx", .id = 18, .dev = { - .parent = &msm_device_smmu_gfx3d.dev, + .parent = &msm_device_iommu_gfx3d.dev, }, }; @@ -705,7 +705,7 @@ static struct platform_device msm_device_gfx3d_smmu_ctx = { .name = "msm_iommu_ctx", .id = 19, .dev = { - .parent = &msm_device_smmu_gfx3d.dev, + .parent = &msm_device_iommu_gfx3d.dev, }, }; @@ -713,7 +713,7 @@ static struct platform_device msm_device_gfx2d0_pixv1_ctx = { .name = "msm_iommu_ctx", .id = 20, .dev = { - .parent = &msm_device_smmu_gfx2d0.dev, + .parent = &msm_device_iommu_gfx2d0.dev, }, }; @@ -721,36 +721,36 @@ static struct platform_device msm_device_gfx2d0_texv3_ctx = { .name = "msm_iommu_ctx", .id = 21, .dev = { - .parent = &msm_device_smmu_gfx2d0.dev, + .parent = &msm_device_iommu_gfx2d0.dev, }, }; static struct platform_device *msm_iommu_devs[] = { - &msm_device_smmu_jpegd, - &msm_device_smmu_vpe, - &msm_device_smmu_mdp0, - &msm_device_smmu_mdp1, - &msm_device_smmu_rot, - &msm_device_smmu_ijpeg, - &msm_device_smmu_vfe, - &msm_device_smmu_vcodec_a, - &msm_device_smmu_vcodec_b, - &msm_device_smmu_gfx3d, - &msm_device_smmu_gfx2d0, + &msm_device_iommu_jpegd, + &msm_device_iommu_vpe, + &msm_device_iommu_mdp0, + &msm_device_iommu_mdp1, + &msm_device_iommu_rot, + &msm_device_iommu_ijpeg, + &msm_device_iommu_vfe, + &msm_device_iommu_vcodec_a, + &msm_device_iommu_vcodec_b, + &msm_device_iommu_gfx3d, + &msm_device_iommu_gfx2d0, }; static struct msm_iommu_dev *msm_iommu_data[] = { - &jpegd_smmu, - &vpe_smmu, - &mdp0_smmu, - &mdp1_smmu, - &rot_smmu, - &ijpeg_smmu, - &vfe_smmu, - &vcodec_a_smmu, - &vcodec_b_smmu, - &gfx3d_smmu, - &gfx2d0_smmu, + &jpegd_iommu, + &vpe_iommu, + &mdp0_iommu, + &mdp1_iommu, + &rot_iommu, + &ijpeg_iommu, + &vfe_iommu, + &vcodec_a_iommu, + &vcodec_b_iommu, + &gfx3d_iommu, + &gfx2d0_iommu, }; static struct platform_device *msm_iommu_ctx_devs[] = { @@ -826,7 +826,7 @@ static int msm8x60_iommu_init(void) ret = platform_device_register(msm_iommu_devs[i]); if (ret != 0) { - pr_err("platform_device_register smmu failed, " + pr_err("platform_device_register iommu failed, " "i = %d\n", i); goto failure_unwind; } @@ -837,7 +837,7 @@ static int msm8x60_iommu_init(void) msm_iommu_ctx_data[i], sizeof(*msm_iommu_ctx_devs[i])); if (ret != 0) { - pr_err("platform_device_add_data smmu failed, " + pr_err("platform_device_add_data iommu failed, " "i = %d\n", i); goto failure_unwind2; } -- cgit v1.2.3-18-g5258 From a5fcd5f59a2658a579533d6774e871aea7ab5e92 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:50 -0800 Subject: msm: iommu: Revise GFX3D IOMMU contexts and M2V mappings Based on recommendations from chip designers, optimize the Machine ID to translation context mappings for the 3D core's IOMMU. Remove the the "gfx3d_smmu" context device, as it is no longer needed under the new mapping scheme. Signed-off-by: Stepan Moskovchenko [dwalker@codeaurora.org: updated commit text] Signed-off-by: Daniel Walker --- arch/arm/mach-msm/devices-msm8x60-iommu.c | 45 +++++++++++-------------------- 1 file changed, 15 insertions(+), 30 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c index 9e657e0ee18..22d0c7cb71f 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c @@ -519,22 +519,17 @@ static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = { .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} }; -static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = { - .name = "gfx3d_rbpa", +static struct msm_iommu_ctx_dev gfx3d_user_ctx = { + .name = "gfx3d_user", .num = 0, - .mids = {-1} + .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} }; -static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = { - .name = "gfx3d_cpvgttc", +static struct msm_iommu_ctx_dev gfx3d_priv_ctx = { + .name = "gfx3d_priv", .num = 1, - .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} -}; - -static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = { - .name = "gfx3d_smmu", - .num = 2, - .mids = {8, 9, 10, 11, 12, -1} + .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31, -1} }; static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = { @@ -685,7 +680,7 @@ static struct platform_device msm_device_vcodec_b_mm2_ctx = { }, }; -static struct platform_device msm_device_gfx3d_rbpa_ctx = { +static struct platform_device msm_device_gfx3d_user_ctx = { .name = "msm_iommu_ctx", .id = 17, .dev = { @@ -693,7 +688,7 @@ static struct platform_device msm_device_gfx3d_rbpa_ctx = { }, }; -static struct platform_device msm_device_gfx3d_cpvgttc_ctx = { +static struct platform_device msm_device_gfx3d_priv_ctx = { .name = "msm_iommu_ctx", .id = 18, .dev = { @@ -701,17 +696,9 @@ static struct platform_device msm_device_gfx3d_cpvgttc_ctx = { }, }; -static struct platform_device msm_device_gfx3d_smmu_ctx = { - .name = "msm_iommu_ctx", - .id = 19, - .dev = { - .parent = &msm_device_iommu_gfx3d.dev, - }, -}; - static struct platform_device msm_device_gfx2d0_pixv1_ctx = { .name = "msm_iommu_ctx", - .id = 20, + .id = 19, .dev = { .parent = &msm_device_iommu_gfx2d0.dev, }, @@ -719,7 +706,7 @@ static struct platform_device msm_device_gfx2d0_pixv1_ctx = { static struct platform_device msm_device_gfx2d0_texv3_ctx = { .name = "msm_iommu_ctx", - .id = 21, + .id = 20, .dev = { .parent = &msm_device_iommu_gfx2d0.dev, }, @@ -771,9 +758,8 @@ static struct platform_device *msm_iommu_ctx_devs[] = { &msm_device_vcodec_a_stream_ctx, &msm_device_vcodec_a_mm1_ctx, &msm_device_vcodec_b_mm2_ctx, - &msm_device_gfx3d_rbpa_ctx, - &msm_device_gfx3d_cpvgttc_ctx, - &msm_device_gfx3d_smmu_ctx, + &msm_device_gfx3d_user_ctx, + &msm_device_gfx3d_priv_ctx, &msm_device_gfx2d0_pixv1_ctx, &msm_device_gfx2d0_texv3_ctx, }; @@ -796,9 +782,8 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { &vcodec_a_stream_ctx, &vcodec_a_mm1_ctx, &vcodec_b_mm2_ctx, - &gfx3d_rbpa_ctx, - &gfx3d_cpvgttc_ctx, - &gfx3d_smmu_ctx, + &gfx3d_user_ctx, + &gfx3d_priv_ctx, &gfx2d0_pixv1_ctx, &gfx2d0_texv3_ctx, }; -- cgit v1.2.3-18-g5258 From ff25ff842ea6afd58ccc2e3f386ee5ac540b6a63 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:51 -0800 Subject: msm: iommu: Revise GFX2D0 IOMMU contexts and M2V mappings Based on recommendations from chip designers, optimize the Machine ID to translation context mappings for the first 2D core's IOMMU. Remove the "gfx2d0_texv3_smmu" context, as it is no longer needed under the new mapping scheme. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/devices-msm8x60-iommu.c | 28 ++++++---------------------- 1 file changed, 6 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c index 22d0c7cb71f..8cccb268054 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c @@ -532,16 +532,10 @@ static struct msm_iommu_ctx_dev gfx3d_priv_ctx = { 31, -1} }; -static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = { - .name = "gfx2d0_pixv1_smmu", +static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = { + .name = "gfx2d0_2d0", .num = 0, - .mids = {0, 3, 4, -1} -}; - -static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = { - .name = "gfx2d0_texv3_smmu", - .num = 1, - .mids = {1, 6, 7, -1} + .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} }; static struct platform_device msm_device_jpegd_src_ctx = { @@ -696,7 +690,7 @@ static struct platform_device msm_device_gfx3d_priv_ctx = { }, }; -static struct platform_device msm_device_gfx2d0_pixv1_ctx = { +static struct platform_device msm_device_gfx2d0_2d0_ctx = { .name = "msm_iommu_ctx", .id = 19, .dev = { @@ -704,14 +698,6 @@ static struct platform_device msm_device_gfx2d0_pixv1_ctx = { }, }; -static struct platform_device msm_device_gfx2d0_texv3_ctx = { - .name = "msm_iommu_ctx", - .id = 20, - .dev = { - .parent = &msm_device_iommu_gfx2d0.dev, - }, -}; - static struct platform_device *msm_iommu_devs[] = { &msm_device_iommu_jpegd, &msm_device_iommu_vpe, @@ -760,8 +746,7 @@ static struct platform_device *msm_iommu_ctx_devs[] = { &msm_device_vcodec_b_mm2_ctx, &msm_device_gfx3d_user_ctx, &msm_device_gfx3d_priv_ctx, - &msm_device_gfx2d0_pixv1_ctx, - &msm_device_gfx2d0_texv3_ctx, + &msm_device_gfx2d0_2d0_ctx, }; static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { @@ -784,8 +769,7 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { &vcodec_b_mm2_ctx, &gfx3d_user_ctx, &gfx3d_priv_ctx, - &gfx2d0_pixv1_ctx, - &gfx2d0_texv3_ctx, + &gfx2d0_2d0_ctx, }; static int msm8x60_iommu_init(void) -- cgit v1.2.3-18-g5258 From e8952e3b32701817705b216b492a9be4fa5cbefc Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:52 -0800 Subject: msm: iommu: Support for the 2nd GFX core's IOMMU Add the platform data and resources needed for the second 2D graphics core's IOMMU. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/devices-msm8x60-iommu.c | 54 +++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c index 8cccb268054..a6ecd39ae06 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c @@ -254,6 +254,27 @@ static struct resource msm_iommu_gfx2d0_resources[] = { }, }; +static struct resource msm_iommu_gfx2d1_resources[] = { + { + .start = MSM_IOMMU_GFX2D1_PHYS, + .end = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, + .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ, + .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + static struct platform_device msm_root_iommu_dev = { .name = "msm_iommu", .id = -1, @@ -307,6 +328,11 @@ static struct msm_iommu_dev gfx2d0_iommu = { .clk_rate = 27000000 }; +static struct msm_iommu_dev gfx2d1_iommu = { + .name = "gfx2d1", + .clk_rate = 27000000 +}; + static struct platform_device msm_device_iommu_jpegd = { .name = "msm_iommu", .id = 0, @@ -417,6 +443,16 @@ static struct platform_device msm_device_iommu_gfx2d0 = { .resource = msm_iommu_gfx2d0_resources, }; +struct platform_device msm_device_iommu_gfx2d1 = { + .name = "msm_iommu", + .id = 11, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources), + .resource = msm_iommu_gfx2d1_resources, +}; + static struct msm_iommu_ctx_dev jpegd_src_ctx = { .name = "jpegd_src", .num = 0, @@ -538,6 +574,12 @@ static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = { .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} }; +static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = { + .name = "gfx2d1_2d1", + .num = 0, + .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} +}; + static struct platform_device msm_device_jpegd_src_ctx = { .name = "msm_iommu_ctx", .id = 0, @@ -698,6 +740,14 @@ static struct platform_device msm_device_gfx2d0_2d0_ctx = { }, }; +static struct platform_device msm_device_gfx2d1_2d1_ctx = { + .name = "msm_iommu_ctx", + .id = 20, + .dev = { + .parent = &msm_device_iommu_gfx2d1.dev, + }, +}; + static struct platform_device *msm_iommu_devs[] = { &msm_device_iommu_jpegd, &msm_device_iommu_vpe, @@ -710,6 +760,7 @@ static struct platform_device *msm_iommu_devs[] = { &msm_device_iommu_vcodec_b, &msm_device_iommu_gfx3d, &msm_device_iommu_gfx2d0, + &msm_device_iommu_gfx2d1, }; static struct msm_iommu_dev *msm_iommu_data[] = { @@ -724,6 +775,7 @@ static struct msm_iommu_dev *msm_iommu_data[] = { &vcodec_b_iommu, &gfx3d_iommu, &gfx2d0_iommu, + &gfx2d1_iommu, }; static struct platform_device *msm_iommu_ctx_devs[] = { @@ -747,6 +799,7 @@ static struct platform_device *msm_iommu_ctx_devs[] = { &msm_device_gfx3d_user_ctx, &msm_device_gfx3d_priv_ctx, &msm_device_gfx2d0_2d0_ctx, + &msm_device_gfx2d1_2d1_ctx, }; static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { @@ -770,6 +823,7 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { &gfx3d_user_ctx, &gfx3d_priv_ctx, &gfx2d0_2d0_ctx, + &gfx2d1_2d1_ctx, }; static int msm8x60_iommu_init(void) -- cgit v1.2.3-18-g5258 From 516cbc793eb4be5123289d067b54dfcdabeddb25 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:53 -0800 Subject: msm: iommu: Mark functions with the right section names Mark the init and exit functions as __init and __exit where appropriate. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/devices-msm8x60-iommu.c | 4 ++-- arch/arm/mach-msm/iommu.c | 2 +- arch/arm/mach-msm/iommu_dev.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c index a6ecd39ae06..f9e7bd34ec5 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c @@ -826,7 +826,7 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { &gfx2d1_2d1_ctx, }; -static int msm8x60_iommu_init(void) +static int __init msm8x60_iommu_init(void) { int ret, i; @@ -886,7 +886,7 @@ failure: return ret; } -static void msm8x60_iommu_exit(void) +static void __exit msm8x60_iommu_exit(void) { int i; diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index f71747db3be..134add78918 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -585,7 +585,7 @@ static struct iommu_ops msm_iommu_ops = { .domain_has_cap = msm_iommu_domain_has_cap }; -static int msm_iommu_init(void) +static int __init msm_iommu_init(void) { register_iommu(&msm_iommu_ops); return 0; diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c index 9019cee2907..b83c73b41fd 100644 --- a/arch/arm/mach-msm/iommu_dev.c +++ b/arch/arm/mach-msm/iommu_dev.c @@ -346,7 +346,7 @@ static struct platform_driver msm_iommu_ctx_driver = { .remove = msm_iommu_ctx_remove, }; -static int msm_iommu_driver_init(void) +static int __init msm_iommu_driver_init(void) { int ret; ret = platform_driver_register(&msm_iommu_driver); @@ -365,7 +365,7 @@ error: return ret; } -static void msm_iommu_driver_exit(void) +static void __exit msm_iommu_driver_exit(void) { platform_driver_unregister(&msm_iommu_ctx_driver); platform_driver_unregister(&msm_iommu_driver); -- cgit v1.2.3-18-g5258 From f6f41eb9ccc0e6fad0ccba4c5e0a97de935db734 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:54 -0800 Subject: msm: iommu: Don't flush page tables if no devices attached Don't flush the page tables on an IOMMU domain if there are no IOMMU devices attached to the domain. The act of attaching to the domain will cause an implicit flush of those areas if the page tables are configured to not be L2 cacheable. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/iommu.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index 134add78918..74f2157eba4 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -50,13 +50,16 @@ static void __flush_iotlb(struct iommu_domain *domain) unsigned long *fl_table = priv->pgtable; int i; - dmac_flush_range(fl_table, fl_table + SZ_16K); + if (!list_empty(&priv->list_attached)) { + dmac_flush_range(fl_table, fl_table + SZ_16K); - for (i = 0; i < NUM_FL_PTE; i++) - if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) { - void *sl_table = __va(fl_table[i] & FL_BASE_MASK); - dmac_flush_range(sl_table, sl_table + SZ_4K); - } + for (i = 0; i < NUM_FL_PTE; i++) + if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) { + void *sl_table = __va(fl_table[i] & + FL_BASE_MASK); + dmac_flush_range(sl_table, sl_table + SZ_4K); + } + } #endif list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) { -- cgit v1.2.3-18-g5258 From 2607b0a26094b2d2d174c3e27b2ecc9c49d86f40 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Mon, 15 Nov 2010 17:46:10 -0800 Subject: msm: iommu: Kconfig item for cacheable page tables Add a Kconfig item to allow the IOMMU page tables to be coherent in the L2 cache. This generally reduces IOTLB miss latencies and has been shown to improve multimedia performance. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index dbbcfeb919d..1c6f76b3d1a 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -122,6 +122,10 @@ config MACH_MSM8X60_FFA endmenu +config IOMMU_PGTABLES_L2 + def_bool y + depends on ARCH_MSM8X60 && MMU && SMP && CPU_DCACHE_DISABLE=n + config MSM_DEBUG_UART int default 1 if MSM_DEBUG_UART1 -- cgit v1.2.3-18-g5258 From 00d4b2bb03b9ed27f28336b0a68f2bd7f67caa40 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:56 -0800 Subject: msm: iommu: Check if device is already attached An IOMMU device can only be attached to one IOMMU domain at any given time. Check whether the device is already attached to a domain before allowing it to be attached to another domain. If so, return busy. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/iommu.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index 74f2157eba4..67e8f531b7a 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -241,6 +241,11 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) goto fail; } + if (!list_empty(&ctx_drvdata->attached_elm)) { + ret = -EBUSY; + goto fail; + } + list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm) if (tmp_drvdata == ctx_drvdata) { ret = -EBUSY; -- cgit v1.2.3-18-g5258 From 0ab84745ef65043a616b36b26bec58e1cb62a742 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:57 -0800 Subject: msm: iommu: Kconfig dependency for the IOMMU API Make the IOMMU driver select the IOMMU API in the kernel configuration. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 1c6f76b3d1a..1a11f1ed216 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -44,6 +44,7 @@ config ARCH_MSM8X60 select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX + select IOMMU_API endchoice @@ -166,4 +167,7 @@ config MSM_GPIOMUX config MSM_V2_TLMM bool + +config IOMMU_API + bool endif -- cgit v1.2.3-18-g5258 From 08bd6839783319085ee0db4c888534e626225774 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Mon, 15 Nov 2010 18:19:35 -0800 Subject: msm: iommu: Definitions for extended memory attributes Add the register field definitions and memory attribute definitions that will be needed to support IOMMU transactions with cache-coherent memory access. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/include/mach/iommu.h | 13 +++++++++++++ arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h | 22 +++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 17fc79fc8bc..296c0f10f23 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -20,6 +20,19 @@ #include +/* Sharability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NON_SH 0x0 +#define MSM_IOMMU_ATTR_SH 0x4 + +/* Cacheability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NONCACHED 0x0 +#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 +#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 +#define MSM_IOMMU_ATTR_CACHED_WT 0x3 + +/* Mask for the cache policy attribute */ +#define MSM_IOMMU_CP_MASK 0x03 + /* Maximum number of Machine IDs that we are allowing to be mapped to the same * context bank. The number of MIDs mapped to the same CB does not affect * performance, but there is a practical limit on how many distinct MIDs may diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h index f9386d3a2f7..c2c3da9444f 100644 --- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h +++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h @@ -54,6 +54,7 @@ do { \ #define NUM_FL_PTE 4096 #define NUM_SL_PTE 256 +#define NUM_TEX_CLASS 8 /* First-level page table bits */ #define FL_BASE_MASK 0xFFFFFC00 @@ -63,6 +64,9 @@ do { \ #define FL_AP_WRITE (1 << 10) #define FL_AP_READ (1 << 11) #define FL_SHARED (1 << 16) +#define FL_BUFFERABLE (1 << 2) +#define FL_CACHEABLE (1 << 3) +#define FL_TEX0 (1 << 12) #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) /* Second-level page table bits */ @@ -73,8 +77,20 @@ do { \ #define SL_AP0 (1 << 4) #define SL_AP1 (2 << 4) #define SL_SHARED (1 << 10) +#define SL_BUFFERABLE (1 << 2) +#define SL_CACHEABLE (1 << 3) +#define SL_TEX0 (1 << 6) #define SL_OFFSET(va) (((va) & 0xFF000) >> 12) +/* Memory type and cache policy attributes */ +#define MT_SO 0 +#define MT_DEV 1 +#define MT_NORMAL 2 +#define CP_NONCACHED 0 +#define CP_WB_WA 1 +#define CP_WT 2 +#define CP_WB_NWA 3 + /* Global register setters / getters */ #define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) #define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v)) @@ -706,7 +722,9 @@ do { \ #define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5) #define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6) #define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7) - +#define NMRR_ICP(nmrr, n) (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2)) +#define NMRR_OCP(nmrr, n) (((nmrr) & (3 << ((n) * 2 + 16))) >> \ + ((n) * 2 + 16)) /* PAR */ #define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT) @@ -750,6 +768,8 @@ do { \ #define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5) #define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6) #define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7) +#define PRRR_NOS(prrr, n) ((prrr) & (1 << ((n) + 24)) ? 1 : 0) +#define PRRR_MT(prrr, n) ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2))) /* RESUME */ -- cgit v1.2.3-18-g5258 From 100832c9b6adb3d63407416931caeba3f3b9a777 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Mon, 15 Nov 2010 18:20:08 -0800 Subject: msm: iommu: Support cache-coherent memory access Add support for allowing IOMMU memory transactions to be cache coherent, eliminating the need for software cache management in certain situations. This can lead to improvements in performance and power usage, assuming the multimedia core's access pattern exhibits spatial locality and that its working set fits into the cache. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/iommu.c | 93 +++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 82 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index 67e8f531b7a..a468ee309d6 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -33,6 +33,16 @@ #include #include +#define MRC(reg, processor, op1, crn, crm, op2) \ +__asm__ __volatile__ ( \ +" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \ +: "=r" (reg)) + +#define RCP15_PRRR(reg) MRC(reg, p15, 0, c10, c2, 0) +#define RCP15_NMRR(reg) MRC(reg, p15, 0, c10, c2, 1) + +static int msm_iommu_tex_class[4]; + DEFINE_SPINLOCK(msm_iommu_lock); struct msm_priv { @@ -98,6 +108,7 @@ static void __reset_context(void __iomem *base, int ctx) static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) { + unsigned int prrr, nmrr; __reset_context(base, ctx); /* Set up HTW mode */ @@ -130,11 +141,11 @@ static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) /* Turn on TEX Remap */ SET_TRE(base, ctx, 1); - /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume - * TEX class 0 for everything until attributes are properly worked out - */ - SET_PRRR(base, ctx, 0); - SET_NMRR(base, ctx, 0); + /* Set TEX remap attributes */ + RCP15_PRRR(prrr); + RCP15_NMRR(nmrr); + SET_PRRR(base, ctx, prrr); + SET_NMRR(base, ctx, nmrr); /* Turn on BFB prefetch */ SET_BFBDFE(base, ctx, 1); @@ -304,12 +315,21 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, unsigned long *sl_table; unsigned long *sl_pte; unsigned long sl_offset; + unsigned int pgprot; size_t len = 0x1000UL << order; - int ret = 0; + int ret = 0, tex, sh; spin_lock_irqsave(&msm_iommu_lock, flags); - priv = domain->priv; + sh = (prot & MSM_IOMMU_ATTR_SH) ? 1 : 0; + tex = msm_iommu_tex_class[prot & MSM_IOMMU_CP_MASK]; + + if (tex < 0 || tex > NUM_TEX_CLASS - 1) { + ret = -EINVAL; + goto fail; + } + + priv = domain->priv; if (!priv) { ret = -EINVAL; goto fail; @@ -330,6 +350,18 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, goto fail; } + if (len == SZ_16M || len == SZ_1M) { + pgprot = sh ? FL_SHARED : 0; + pgprot |= tex & 0x01 ? FL_BUFFERABLE : 0; + pgprot |= tex & 0x02 ? FL_CACHEABLE : 0; + pgprot |= tex & 0x04 ? FL_TEX0 : 0; + } else { + pgprot = sh ? SL_SHARED : 0; + pgprot |= tex & 0x01 ? SL_BUFFERABLE : 0; + pgprot |= tex & 0x02 ? SL_CACHEABLE : 0; + pgprot |= tex & 0x04 ? SL_TEX0 : 0; + } + fl_offset = FL_OFFSET(va); /* Upper 12 bits */ fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */ @@ -338,12 +370,12 @@ static int msm_iommu_map(struct iommu_domain *dom