From b45756f65d90dca10cbe3e9ef04ecf96c01124a2 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Mon, 29 Nov 2010 16:58:29 +0900 Subject: ARM: S5PV310: Add Interrupt of MCT This patch adds IRQ_MCT0, IRQ_MCT1, IRQ_MCT_L0, and IRQ_MCT_L1. (MCT: Multi-Core Timer). And updated MAX_COMBINER_NR. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/include/mach/irqs.h | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h index 99e7dad8a85..f9a2830620d 100644 --- a/arch/arm/mach-s5pv310/include/mach/irqs.h +++ b/arch/arm/mach-s5pv310/include/mach/irqs.h @@ -25,6 +25,8 @@ #define IRQ_SPI(x) S5P_IRQ(x+32) +#define IRQ_MCT1 IRQ_SPI(35) + #define IRQ_EINT0 IRQ_SPI(40) #define IRQ_EINT1 IRQ_SPI(41) #define IRQ_EINT2 IRQ_SPI(42) @@ -36,9 +38,8 @@ #define IRQ_JPEG IRQ_SPI(48) #define IRQ_2D IRQ_SPI(49) #define IRQ_PCIE IRQ_SPI(50) -#define IRQ_SYSTEM_TIMER IRQ_SPI(51) +#define IRQ_MCT0 IRQ_SPI(51) #define IRQ_MFC IRQ_SPI(52) -#define IRQ_WDT IRQ_SPI(53) #define IRQ_AUDIO_SS IRQ_SPI(54) #define IRQ_AC97 IRQ_SPI(55) #define IRQ_SPDIF IRQ_SPI(56) @@ -85,6 +86,8 @@ #define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) +#define IRQ_MCT_L1 COMBINER_IRQ(35, 3) + #define IRQ_EINT4 COMBINER_IRQ(37, 0) #define IRQ_EINT5 COMBINER_IRQ(37, 1) #define IRQ_EINT6 COMBINER_IRQ(37, 2) @@ -101,7 +104,11 @@ #define IRQ_EINT16_31 COMBINER_IRQ(39, 0) -#define MAX_COMBINER_NR 40 +#define IRQ_MCT_L0 COMBINER_IRQ(51, 0) + +#define IRQ_WDT COMBINER_IRQ(53, 0) + +#define MAX_COMBINER_NR 54 #define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) -- cgit v1.2.3-18-g5258 From 1f2d6c49f087c84ed54ad3e0801faeca3e2ccfdd Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Mon, 29 Nov 2010 17:04:46 +0900 Subject: ARM: S5PV310: Limit the irqs which support cascade interrupt The irqs from SPI(0) to SPI(39) and SPI(51), SPI(53) are connected to the interrupt combiner. This patch limits the irqs which should be initialized to support cascade interrupt. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 82ce4aa6d61..3d0c1cb68d9 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -127,6 +127,15 @@ void __init s5pv310_init_irq(void) gic_cpu_init(0, S5P_VA_GIC_CPU); for (irq = 0; irq < MAX_COMBINER_NR; irq++) { + + /* + * From SPI(0) to SPI(39) and SPI(51), SPI(53) are + * connected to the interrupt combiner. These irqs + * should be initialized to support cascade interrupt. + */ + if ((irq >= 40) && !(irq == 51) && !(irq == 53)) + continue; + combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), COMBINER_IRQ(irq, 0)); combiner_cascade_irq(irq, IRQ_SPI(irq)); -- cgit v1.2.3-18-g5258 From 85140ad591e696bc88b0ad7c978256f91099e6c9 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Mon, 29 Nov 2010 17:05:16 +0900 Subject: ARM: S5PV310: Add irq_mask to handle combiner irqs properly The 4 combiner groups use same registers to handle the interrupt. In previous implementation, the whole registers are checked to find which interupt is occurred and thus interrupt in other groups can be detected. This patch adds irq_mask to solve this problem. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/irq-combiner.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c index c3f88c3faf6..aad5c3d525d 100644 --- a/arch/arm/mach-s5pv310/irq-combiner.c +++ b/arch/arm/mach-s5pv310/irq-combiner.c @@ -24,6 +24,7 @@ static DEFINE_SPINLOCK(irq_controller_lock); struct combiner_chip_data { unsigned int irq_offset; + unsigned int irq_mask; void __iomem *base; }; @@ -62,6 +63,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) spin_lock(&irq_controller_lock); status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); spin_unlock(&irq_controller_lock); + status &= chip_data->irq_mask; if (status == 0) goto out; @@ -104,10 +106,12 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base, combiner_data[combiner_nr].base = base; combiner_data[combiner_nr].irq_offset = irq_start; + combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); /* Disable all interrupts */ - __raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR); + __raw_writel(combiner_data[combiner_nr].irq_mask, + base + COMBINER_ENABLE_CLEAR); /* Setup the Linux IRQ subsystem */ -- cgit v1.2.3-18-g5258 From 7af36b9787e19b4cbde9ee984e431d64b586784e Mon Sep 17 00:00:00 2001 From: Sunyoung Kang Date: Sat, 18 Sep 2010 10:59:31 +0900 Subject: ARM: S5PV310: Update CMU registers for CPUFREQ This patch adds CMU(Clock Management Unit) registers for S5PV310/S5PC210 CPUFREQ driver and modifies some register names according to datasheet. Signed-off-by: Sunyoung Kang Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 12 ++-- arch/arm/mach-s5pv310/include/mach/regs-clock.h | 77 ++++++++++++++++++++++++- 2 files changed, 81 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 58c9d33f36f..fdce2b48efc 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -244,7 +244,7 @@ static struct clksrc_clk clk_mout_corebus = { .id = -1, }, .sources = &clkset_mout_corebus, - .reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 }, + .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, }; static struct clksrc_clk clk_sclk_dmc = { @@ -253,7 +253,7 @@ static struct clksrc_clk clk_sclk_dmc = { .id = -1, .parent = &clk_mout_corebus.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, }; static struct clksrc_clk clk_aclk_cored = { @@ -262,7 +262,7 @@ static struct clksrc_clk clk_aclk_cored = { .id = -1, .parent = &clk_sclk_dmc.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, }; static struct clksrc_clk clk_aclk_corep = { @@ -271,7 +271,7 @@ static struct clksrc_clk clk_aclk_corep = { .id = -1, .parent = &clk_aclk_cored.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, }; static struct clksrc_clk clk_aclk_acp = { @@ -280,7 +280,7 @@ static struct clksrc_clk clk_aclk_acp = { .id = -1, .parent = &clk_mout_corebus.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, }; static struct clksrc_clk clk_pclk_acp = { @@ -289,7 +289,7 @@ static struct clksrc_clk clk_pclk_acp = { .id = -1, .parent = &clk_aclk_acp.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, }; /* Core list of CMU_TOP side */ diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h index f1028cad978..9e9e44c3290 100644 --- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h @@ -19,6 +19,12 @@ #define S5P_INFORM0 S5P_CLKREG(0x800) +#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) +#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) + +#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) +#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) + #define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) #define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) #define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) @@ -58,6 +64,8 @@ #define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) #define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) +#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) + #define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) #define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) #define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) @@ -66,8 +74,9 @@ #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) #define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) -#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) -#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500) +#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) +#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) +#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) #define S5P_APLL_LOCK S5P_CLKREG(0x14000) #define S5P_MPLL_LOCK S5P_CLKREG(0x14004) @@ -84,6 +93,70 @@ #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) +/* APLL_LOCK */ +#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ + +/* APLL_CON0 */ +#define S5P_APLLCON0_ENABLE_SHIFT (31) +#define S5P_APLLCON0_LOCKED_SHIFT (29) +#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) + +/* CLK_SRC_CPU */ +#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) +#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) + +/* CLKDIV_CPU0 */ +#define S5P_CLKDIV_CPU0_CORE_SHIFT (0) +#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT) +#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4) +#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT) +#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8) +#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT) +#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12) +#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT) +#define S5P_CLKDIV_CPU0_ATB_SHIFT (16) +#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT) +#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20) +#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) +#define S5P_CLKDIV_CPU0_APLL_SHIFT (24) +#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT) + +/* CLKDIV_DMC0 */ +#define S5P_CLKDIV_DMC0_ACP_SHIFT (0) +#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT) +#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4) +#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) +#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8) +#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT) +#define S5P_CLKDIV_DMC0_DMC_SHIFT (12) +#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT) +#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16) +#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT) +#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20) +#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT) +#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24) +#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT) +#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28) +#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT) + +/* CLKDIV_TOP */ +#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0) +#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT) +#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4) +#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT) +#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8) +#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT) +#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12) +#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT) +#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16) +#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT) + +/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/ +#define S5P_CLKDIV_BUS_GDLR_SHIFT (0) +#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT) +#define S5P_CLKDIV_BUS_GPLR_SHIFT (4) +#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) + /* Compatibility defines */ #define S5P_EPLL_CON S5P_EPLL_CON0 -- cgit v1.2.3-18-g5258 From 09dc781e94b881d23e3c5da8c72d6832ae542938 Mon Sep 17 00:00:00 2001 From: Sangwook Ju Date: Wed, 22 Dec 2010 07:26:40 +0900 Subject: ARM: S5PV310: Define missing CMU register for CPUFREQ This patch adds missing CMU(Clock Management Unit) registers for updated S5PV310 CPUFREQ driver. Signed-off-by: Sangwook Ju Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/include/mach/regs-clock.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h index 9e9e44c3290..b5c4ada1cff 100644 --- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h @@ -89,7 +89,9 @@ #define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) #define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) +#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504) #define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) +#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) @@ -100,6 +102,7 @@ #define S5P_APLLCON0_ENABLE_SHIFT (31) #define S5P_APLLCON0_LOCKED_SHIFT (29) #define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) +#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) /* CLK_SRC_CPU */ #define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) -- cgit v1.2.3-18-g5258 From dd0b7e20da906b40d55f24bb2dc21abd58ed3f55 Mon Sep 17 00:00:00 2001 From: Sunyoung Kang Date: Wed, 22 Dec 2010 07:21:17 +0900 Subject: ARM: S5PV310: Add DMC registers and map_desc This patch adds DMC io mapping for access it and adds registers. This is used in checking DRAM memory type. Signed-off-by: Sunyoung Kang Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/cpu.c | 5 +++++ arch/arm/mach-s5pv310/include/mach/map.h | 2 ++ arch/arm/mach-s5pv310/include/mach/regs-mem.h | 23 +++++++++++++++++++++++ 3 files changed, 30 insertions(+) create mode 100644 arch/arm/mach-s5pv310/include/mach/regs-mem.h (limited to 'arch') diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 82ce4aa6d61..283dd75effe 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -72,6 +72,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = { .pfn = __phys_to_pfn(S5PV310_PA_GPIO3), .length = SZ_256, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_DMC0, + .pfn = __phys_to_pfn(S5PV310_PA_DMC0), + .length = SZ_4K, + .type = MT_DEVICE, }, { .virtual = (unsigned long)S3C_VA_UART, .pfn = __phys_to_pfn(S3C_PA_UART), diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h index 7acf4e77e92..37294f13ca0 100644 --- a/arch/arm/mach-s5pv310/include/mach/map.h +++ b/arch/arm/mach-s5pv310/include/mach/map.h @@ -44,6 +44,8 @@ #define S5PV310_PA_WATCHDOG (0x10060000) #define S5PV310_PA_RTC (0x10070000) +#define S5PV310_PA_DMC0 (0x10400000) + #define S5PV310_PA_COMBINER (0x10448000) #define S5PV310_PA_COREPERI (0x10500000) diff --git a/arch/arm/mach-s5pv310/include/mach/regs-mem.h b/arch/arm/mach-s5pv310/include/mach/regs-mem.h new file mode 100644 index 00000000000..834227140ea --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/regs-mem.h @@ -0,0 +1,23 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 - SROMC and DMC register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_MEM_H +#define __ASM_ARCH_REGS_MEM_H __FILE__ + +#include + +#define S5P_DMC0_MEMCON_OFFSET 0x04 + +#define S5P_DMC0_MEMTYPE_SHIFT 8 +#define S5P_DMC0_MEMTYPE_MASK 0xF + +#endif /* __ASM_ARCH_REGS_MEM_H */ -- cgit v1.2.3-18-g5258 From f40f91fefcf3a9049bcfa31ac53bc0e775444dab Mon Sep 17 00:00:00 2001 From: Sunyoung Kang Date: Thu, 16 Sep 2010 17:59:21 +0900 Subject: ARM: S5PV310: Add support CPUFREQ This patch adds support CPUFREQ driver for S5PV310 and S5PC210. This can support DVFS(Dynamic Voltage and Frequency Scaling). The voltage scaling depends on existence of regulator. Sigend-off-by: Sunyoung Kang Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/cpufreq.c | 561 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 561 insertions(+) create mode 100644 arch/arm/mach-s5pv310/cpufreq.c (limited to 'arch') diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-s5pv310/cpufreq.c new file mode 100644 index 00000000000..bcd4ebf93e5 --- /dev/null +++ b/arch/arm/mach-s5pv310/cpufreq.c @@ -0,0 +1,561 @@ +/* linux/arch/arm/mach-s5pv310/cpufreq.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 - CPU frequency scaling support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +static struct clk *cpu_clk; +static struct clk *moutcore; +static struct clk *mout_mpll; +static struct clk *mout_apll; + +#ifdef CONFIG_REGULATOR +static struct regulator *arm_regulator; +static struct regulator *int_regulator; +#endif + +static struct cpufreq_freqs freqs; +static unsigned int armclk_use_apll; +static unsigned int memtype; + +enum s5pv310_memory_type { + DDR2 = 4, + LPDDR2, + DDR3, +}; + +enum cpufreq_level_index { + L0, L1, L2, L3, L4, CPUFREQ_LEVEL_END, +}; + +static struct cpufreq_frequency_table s5pv310_freq_table[] = { + {L0, 1000*1000}, + {L1, 800*1000}, + {L2, 400*1000}, + {L3, 200*1000}, + {L4, 100*1000}, + {0, CPUFREQ_TABLE_END}, +}; + +static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END + 1][7] = { + /* + * Clock divider value for following + * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, + * DIVATB, DIVPCLK_DBG, DIVAPLL } + */ + + /* ARM L0: 1000MHz */ + { 0, 3, 7, 3, 3, 0, 0 }, + + /* ARM L1: 800MHz */ + { 0, 3, 7, 3, 3, 0, 0 }, + + /* ARM L2: 400MHz */ + { 1, 1, 3, 1, 1, 0, 0 }, + + /* ARM L3: 200MHz */ + { 3, 0, 1, 0, 0, 0, 0 }, + + /* ARM L4A: 100MHz, for DDR2/3 */ + { 7, 0, 1, 0, 0, 0, 0 }, + + /* ARM L4B: 100MHz, for LPDDR2 (SMDKV310 has LPDDR2) */ + { 7, 0, 1, 0, 0, 0, 0 }, +}; + +static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END + 1][8] = { + /* + * Clock divider value for following + * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD + * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS } + */ + + /* DMC L0: 400MHz */ + { 3, 1, 1, 1, 1, 1, 3, 1 }, + + /* DMC L1: 400MHz */ + { 3, 1, 1, 1, 1, 1, 3, 1 }, + + /* DMC L2: 400MHz */ + { 3, 1, 1, 1, 1, 1, 3, 1 }, + + /* DMC L3: 400MHz */ + { 3, 1, 1, 1, 1, 1, 3, 1 }, + + /* DMC L4A: 400MHz, for DDR2/3 */ + { 7, 1, 1, 1, 1, 1, 3, 1 }, + + /* DMC L4B: 200MHz, for LPDDR2 */ + { 7, 1, 1, 3, 1, 1, 3, 1 }, +}; + +static unsigned int clkdiv_top[CPUFREQ_LEVEL_END + 1][5] = { + /* + * Clock divider value for following + * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND } + */ + + /* ACLK200 L0: 200MHz */ + { 3, 7, 4, 5, 1 }, + + /* ACLK200 L1: 200MHz */ + { 3, 7, 4, 5, 1 }, + + /* ACLK200 L2: 200MHz */ + { 3, 7, 4, 5, 1 }, + + /* ACLK200 L3: 200MHz */ + { 3, 7, 4, 5, 1 }, + + /* ACLK200 L4A: 100MHz */ + { 7, 7, 7, 7, 1 }, + + /* ACLK200 L4B: 100MHz */ + { 7, 7, 7, 7, 1 }, +}; + +static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END + 1][2] = { + /* + * Clock divider value for following + * { DIVGDL/R, DIVGPL/R } + */ + + /* ACLK_GDL/R L0: 200MHz */ + { 3, 1 }, + + /* ACLK_GDL/R L1: 200MHz */ + { 3, 1 }, + + /* ACLK_GDL/R L2: 200MHz */ + { 3, 1 }, + + /* ACLK_GDL/R L3: 200MHz */ + { 3, 1 }, + + /* ACLK_GDL/R L4A: 100MHz */ + { 7, 1 }, + + /* ACLK_GDL/R L4B: 100MHz */ + { 7, 1 }, +}; + +struct cpufreq_voltage_table { + unsigned int index; /* any */ + unsigned int arm_volt; /* uV */ + unsigned int int_volt; +}; + +static struct cpufreq_voltage_table s5pv310_volt_table[] = { + { + .index = L0, + .arm_volt = 1200000, + .int_volt = 1100000, + }, { + .index = L1, + .arm_volt = 1100000, + .int_volt = 1100000, + }, { + .index = L2, + .arm_volt = 1050000, + .int_volt = 1100000, + }, { + .index = L3, + .arm_volt = 1050000, + .int_volt = 1100000, + }, { + .index = L4, + .arm_volt = 1000000, + .int_volt = 1000000, + }, +}; + +int s5pv310_verify_speed(struct cpufreq_policy *policy) +{ + return cpufreq_frequency_table_verify(policy, s5pv310_freq_table); +} + +unsigned int s5pv310_getspeed(unsigned int cpu) +{ + return clk_get_rate(cpu_clk) / 1000; +} + +void s5pv310_set_clkdiv(unsigned int div_index) +{ + unsigned int tmp; + + /* Change Divider - CPU0 */ + + tmp = __raw_readl(S5P_CLKDIV_CPU); + + tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK | + S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK | + S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK | + S5P_CLKDIV_CPU0_APLL_MASK); + + tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) | + (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) | + (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) | + (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) | + (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) | + (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) | + (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT)); + + __raw_writel(tmp, S5P_CLKDIV_CPU); + + do { + tmp = __raw_readl(S5P_CLKDIV_STATCPU); + } while (tmp & 0x1111111); + + /* Change Divider - DMC0 */ + + tmp = __raw_readl(S5P_CLKDIV_DMC0); + + tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK | + S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK | + S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK | + S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK); + + tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) | + (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) | + (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) | + (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) | + (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) | + (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) | + (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) | + (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT)); + + __raw_writel(tmp, S5P_CLKDIV_DMC0); + + do { + tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0); + } while (tmp & 0x11111111); + + /* Change Divider - TOP */ + + tmp = __raw_readl(S5P_CLKDIV_TOP); + + tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK | + S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK | + S5P_CLKDIV_TOP_ONENAND_MASK); + + tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) | + (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) | + (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) | + (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) | + (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT)); + + __raw_writel(tmp, S5P_CLKDIV_TOP); + + do { + tmp = __raw_readl(S5P_CLKDIV_STAT_TOP); + } while (tmp & 0x11111); + + /* Change Divider - LEFTBUS */ + + tmp = __raw_readl(S5P_CLKDIV_LEFTBUS); + + tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); + + tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) | + (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT)); + + __raw_writel(tmp, S5P_CLKDIV_LEFTBUS); + + do { + tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS); + } while (tmp & 0x11); + + /* Change Divider - RIGHTBUS */ + + tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS); + + tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); + + tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) | + (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT)); + + __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS); + + do { + tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS); + } while (tmp & 0x11); +} + +static int s5pv310_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + unsigned int index, div_index, tmp; + unsigned int arm_volt, int_volt; + unsigned int need_apll = 0; + + freqs.old = s5pv310_getspeed(policy->cpu); + + if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, + target_freq, relation, &index)) + return -EINVAL; + + freqs.new = s5pv310_freq_table[index].frequency; + freqs.cpu = policy->cpu; + + if (freqs.new == freqs.old) + return 0; + + /* + * If freqs.new is higher than 800MHz + * cpufreq driver should turn on apll + */ + if (index < L1) + need_apll = 1; + + /* If the memory type is LPDDR2, use L4-B instead of L4-A */ + if ((index == L4) && (memtype == LPDDR2)) + div_index = index + 1; + else + div_index = index; + + /* get the voltage value */ + arm_volt = s5pv310_volt_table[index].arm_volt; + int_volt = s5pv310_volt_table[index].int_volt; + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + /* control regulator */ + if (freqs.new > freqs.old) { + /* Voltage up */ +#ifdef CONFIG_REGULATOR + regulator_set_voltage(arm_regulator, arm_volt, arm_volt); + regulator_set_voltage(int_regulator, int_volt, int_volt); +#endif + } + + /* Clock Configuration Procedure */ + + /* 1. Change the system clock divider values */ + s5pv310_set_clkdiv(div_index); + + /* 2. Change the divider values for special clocks in CMU_TOP */ + /* currently nothing */ + + /* 3. Change the XPLL values or Select the parent XPLL */ + if (need_apll) { + if (!armclk_use_apll) { + /* + * If the parent clock of armclk isn't apll + * here need to set apll (include m,p,s value) + */ + + /* a. MUX_CORE_SEL = MPLL, + * ARMCLK uses MPLL for lock time */ + clk_set_parent(moutcore, mout_mpll); + + do { + tmp = (__raw_readl(S5P_CLKMUX_STATCPU) + >> S5P_CLKSRC_CPU_MUXCORE_SHIFT); + tmp &= 0x7; + } while (tmp != 0x2); + + /* b. Set APLL Lock time */ + __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK); + + /* c. Change PLL PMS values */ + __raw_writel(S5P_APLL_VAL_1000, S5P_APLL_CON0); + + /* d. Turn on a PLL */ + tmp = __raw_readl(S5P_APLL_CON0); + tmp |= (0x1 << S5P_APLLCON0_ENABLE_SHIFT); + __raw_writel(tmp, S5P_APLL_CON0); + + /* e. wait_lock_time */ + do { + tmp = __raw_readl(S5P_APLL_CON0); + } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT))); + + armclk_use_apll = 1; + + } + + /* MUX_CORE_SEL = APLL */ + clk_set_parent(moutcore, mout_apll); + + do { + tmp = __raw_readl(S5P_CLKMUX_STATCPU); + tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK; + } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)); + + } else { + if (clk_get_parent(moutcore) != mout_mpll) { + clk_set_parent(moutcore, mout_mpll); + + do { + tmp = __raw_readl(S5P_CLKMUX_STATCPU); + tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK; + } while (tmp != (0x2 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)); + } + } + + /* control regulator */ + if (freqs.new < freqs.old) { + /* Voltage down */ +#ifdef CONFIG_REGULATOR + regulator_set_voltage(arm_regulator, arm_volt, arm_volt); + regulator_set_voltage(int_regulator, int_volt, int_volt); +#endif + } + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return 0; +} + +#ifdef CONFIG_PM +static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy, + pm_message_t pmsg) +{ + return 0; +} + +static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy) +{ + return 0; +} +#endif + +static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy) +{ + policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu); + + cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu); + + /* set the transition latency value */ + policy->cpuinfo.transition_latency = 100000; + + /* + * S5PV310 multi-core processors has 2 cores + * that the frequency cannot be set independently. + * Each cpu is bound to the same speed. + * So the affected cpu is all of the cpus. + */ + cpumask_setall(policy->cpus); + + return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table); +} + +static struct cpufreq_driver s5pv310_driver = { + .flags = CPUFREQ_STICKY, + .verify = s5pv310_verify_speed, + .target = s5pv310_target, + .get = s5pv310_getspeed, + .init = s5pv310_cpufreq_cpu_init, + .name = "s5pv310_cpufreq", +#ifdef CONFIG_PM + .suspend = s5pv310_cpufreq_suspend, + .resume = s5pv310_cpufreq_resume, +#endif +}; + +static int __init s5pv310_cpufreq_init(void) +{ + unsigned int tmp; + + cpu_clk = clk_get(NULL, "armclk"); + if (IS_ERR(cpu_clk)) + return PTR_ERR(cpu_clk); + + moutcore = clk_get(NULL, "moutcore"); + if (IS_ERR(moutcore)) + goto out; + + mout_mpll = clk_get(NULL, "mout_mpll"); + if (IS_ERR(mout_mpll)) + goto out; + + mout_apll = clk_get(NULL, "mout_apll"); + if (IS_ERR(mout_apll)) + goto out; + +#ifdef CONFIG_REGULATOR + arm_regulator = regulator_get(NULL, "vdd_arm"); + if (IS_ERR(arm_regulator)) { + printk(KERN_ERR "failed to get resource %s\n", "vdd_arm"); + goto out; + } + + int_regulator = regulator_get(NULL, "vdd_int"); + if (IS_ERR(int_regulator)) { + printk(KERN_ERR "failed to get resource %s\n", "vdd_int"); + goto out; + } +#endif + + /* check parent clock of armclk */ + tmp = __raw_readl(S5P_CLKSRC_CPU); + if (tmp & S5P_CLKSRC_CPU_MUXCORE_SHIFT) + armclk_use_apll = 0; + else + armclk_use_apll = 1; + + /* + * Check DRAM type. + * Because DVFS level is different according to DRAM type. + */ + memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET); + memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT); + memtype &= S5P_DMC0_MEMTYPE_MASK; + + if ((memtype < DDR2) && (memtype > DDR3)) { + printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype); + goto out; + } else { + printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype); + } + + return cpufreq_register_driver(&s5pv310_driver); + +out: + if (!IS_ERR(cpu_clk)) + clk_put(cpu_clk); + + if (!IS_ERR(moutcore)) + clk_put(moutcore); + + if (!IS_ERR(mout_mpll)) + clk_put(mout_mpll); + + if (!IS_ERR(mout_apll)) + clk_put(mout_apll); + +#ifdef CONFIG_REGULATOR + if (!IS_ERR(arm_regulator)) + regulator_put(arm_regulator); + + if (!IS_ERR(int_regulator)) + regulator_put(int_regulator); +#endif + + printk(KERN_ERR "%s: failed initialization\n", __func__); + + return -EINVAL; +} +late_initcall(s5pv310_cpufreq_init); -- cgit v1.2.3-18-g5258 From bf5ce054f5ffdb9a2f5556edab07e86acec916ed Mon Sep 17 00:00:00 2001 From: Sangwook Ju Date: Wed, 22 Dec 2010 16:49:32 +0900 Subject: ARM: S5PV310: Update CPUFREQ This patch updates following of CPUFREQ. - Updated DVFS table and divider value - Added common function - Added some function for changing APLL and setting Signed-off-by: Sangwook Ju Reviewed-by: Jaecheol Lee Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/cpufreq.c | 301 +++++++++++++++++++++------------------- 1 file changed, 160 insertions(+), 141 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-s5pv310/cpufreq.c index bcd4ebf93e5..b04cbc73112 100644 --- a/arch/arm/mach-s5pv310/cpufreq.c +++ b/arch/arm/mach-s5pv310/cpufreq.c @@ -24,6 +24,7 @@ #include #include +#include static struct clk *cpu_clk; static struct clk *moutcore; @@ -36,7 +37,6 @@ static struct regulator *int_regulator; #endif static struct cpufreq_freqs freqs; -static unsigned int armclk_use_apll; static unsigned int memtype; enum s5pv310_memory_type { @@ -46,19 +46,18 @@ enum s5pv310_memory_type { }; enum cpufreq_level_index { - L0, L1, L2, L3, L4, CPUFREQ_LEVEL_END, + L0, L1, L2, L3, CPUFREQ_LEVEL_END, }; static struct cpufreq_frequency_table s5pv310_freq_table[] = { {L0, 1000*1000}, {L1, 800*1000}, {L2, 400*1000}, - {L3, 200*1000}, - {L4, 100*1000}, + {L3, 100*1000}, {0, CPUFREQ_TABLE_END}, }; -static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END + 1][7] = { +static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = { /* * Clock divider value for following * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, @@ -66,25 +65,38 @@ static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END + 1][7] = { */ /* ARM L0: 1000MHz */ - { 0, 3, 7, 3, 3, 0, 0 }, + { 0, 3, 7, 3, 3, 0, 1 }, /* ARM L1: 800MHz */ - { 0, 3, 7, 3, 3, 0, 0 }, + { 0, 3, 7, 3, 3, 0, 1 }, /* ARM L2: 400MHz */ - { 1, 1, 3, 1, 1, 0, 0 }, + { 0, 1, 3, 1, 3, 0, 1 }, - /* ARM L3: 200MHz */ - { 3, 0, 1, 0, 0, 0, 0 }, + /* ARM L3: 100MHz */ + { 0, 0, 1, 0, 3, 1, 1 }, +}; - /* ARM L4A: 100MHz, for DDR2/3 */ - { 7, 0, 1, 0, 0, 0, 0 }, +static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = { + /* + * Clock divider value for following + * { DIVCOPY, DIVHPM } + */ + + /* ARM L0: 1000MHz */ + { 3, 0 }, + + /* ARM L1: 800MHz */ + { 3, 0 }, - /* ARM L4B: 100MHz, for LPDDR2 (SMDKV310 has LPDDR2) */ - { 7, 0, 1, 0, 0, 0, 0 }, + /* ARM L2: 400MHz */ + { 3, 0 }, + + /* ARM L3: 100MHz */ + { 3, 0 }, }; -static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END + 1][8] = { +static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = { /* * Clock divider value for following * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD @@ -97,20 +109,14 @@ static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END + 1][8] = { /* DMC L1: 400MHz */ { 3, 1, 1, 1, 1, 1, 3, 1 }, - /* DMC L2: 400MHz */ - { 3, 1, 1, 1, 1, 1, 3, 1 }, - - /* DMC L3: 400MHz */ - { 3, 1, 1, 1, 1, 1, 3, 1 }, - - /* DMC L4A: 400MHz, for DDR2/3 */ - { 7, 1, 1, 1, 1, 1, 3, 1 }, + /* DMC L2: 266.7MHz */ + { 7, 1, 1, 2, 1, 1, 3, 1 }, - /* DMC L4B: 200MHz, for LPDDR2 */ + /* DMC L3: 200MHz */ { 7, 1, 1, 3, 1, 1, 3, 1 }, }; -static unsigned int clkdiv_top[CPUFREQ_LEVEL_END + 1][5] = { +static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = { /* * Clock divider value for following * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND } @@ -122,20 +128,14 @@ static unsigned int clkdiv_top[CPUFREQ_LEVEL_END + 1][5] = { /* ACLK200 L1: 200MHz */ { 3, 7, 4, 5, 1 }, - /* ACLK200 L2: 200MHz */ - { 3, 7, 4, 5, 1 }, - - /* ACLK200 L3: 200MHz */ - { 3, 7, 4, 5, 1 }, - - /* ACLK200 L4A: 100MHz */ - { 7, 7, 7, 7, 1 }, + /* ACLK200 L2: 160MHz */ + { 4, 7, 5, 7, 1 }, - /* ACLK200 L4B: 100MHz */ - { 7, 7, 7, 7, 1 }, + /* ACLK200 L3: 133.3MHz */ + { 5, 7, 7, 7, 1 }, }; -static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END + 1][2] = { +static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = { /* * Clock divider value for following * { DIVGDL/R, DIVGPL/R } @@ -147,17 +147,11 @@ static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END + 1][2] = { /* ACLK_GDL/R L1: 200MHz */ { 3, 1 }, - /* ACLK_GDL/R L2: 200MHz */ - { 3, 1 }, - - /* ACLK_GDL/R L3: 200MHz */ - { 3, 1 }, + /* ACLK_GDL/R L2: 160MHz */ + { 4, 1 }, - /* ACLK_GDL/R L4A: 100MHz */ - { 7, 1 }, - - /* ACLK_GDL/R L4B: 100MHz */ - { 7, 1 }, + /* ACLK_GDL/R L3: 133.3MHz */ + { 5, 1 }, }; struct cpufreq_voltage_table { @@ -166,7 +160,7 @@ struct cpufreq_voltage_table { unsigned int int_volt; }; -static struct cpufreq_voltage_table s5pv310_volt_table[] = { +static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = { { .index = L0, .arm_volt = 1200000, @@ -177,19 +171,29 @@ static struct cpufreq_voltage_table s5pv310_volt_table[] = { .int_volt = 1100000, }, { .index = L2, - .arm_volt = 1050000, - .int_volt = 1100000, + .arm_volt = 1000000, + .int_volt = 1000000, }, { .index = L3, - .arm_volt = 1050000, - .int_volt = 1100000, - }, { - .index = L4, - .arm_volt = 1000000, + .arm_volt = 900000, .int_volt = 1000000, }, }; +static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = { + /* APLL FOUT L0: 1000MHz */ + ((250 << 16) | (6 << 8) | 1), + + /* APLL FOUT L1: 800MHz */ + ((200 << 16) | (6 << 8) | 1), + + /* APLL FOUT L2 : 400MHz */ + ((200 << 16) | (6 << 8) | 2), + + /* APLL FOUT L3: 100MHz */ + ((200 << 16) | (6 << 8) | 4), +}; + int s5pv310_verify_speed(struct cpufreq_policy *policy) { return cpufreq_frequency_table_verify(policy, s5pv310_freq_table); @@ -227,6 +231,21 @@ void s5pv310_set_clkdiv(unsigned int div_index) tmp = __raw_readl(S5P_CLKDIV_STATCPU); } while (tmp & 0x1111111); + /* Change Divider - CPU1 */ + + tmp = __raw_readl(S5P_CLKDIV_CPU1); + + tmp &= ~((0x7 << 4) | 0x7); + + tmp |= ((clkdiv_cpu1[div_index][0] << 4) | + (clkdiv_cpu1[div_index][1] << 0)); + + __raw_writel(tmp, S5P_CLKDIV_CPU1); + + do { + tmp = __raw_readl(S5P_CLKDIV_STATCPU1); + } while (tmp & 0x11); + /* Change Divider - DMC0 */ tmp = __raw_readl(S5P_CLKDIV_DMC0); @@ -302,16 +321,100 @@ void s5pv310_set_clkdiv(unsigned int div_index) } while (tmp & 0x11); } +static void s5pv310_set_apll(unsigned int index) +{ + unsigned int tmp; + + /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ + clk_set_parent(moutcore, mout_mpll); + + do { + tmp = (__raw_readl(S5P_CLKMUX_STATCPU) + >> S5P_CLKSRC_CPU_MUXCORE_SHIFT); + tmp &= 0x7; + } while (tmp != 0x2); + + /* 2. Set APLL Lock time */ + __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK); + + /* 3. Change PLL PMS values */ + tmp = __raw_readl(S5P_APLL_CON0); + tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); + tmp |= s5pv310_apll_pms_table[index]; + __raw_writel(tmp, S5P_APLL_CON0); + + /* 4. wait_lock_time */ + do { + tmp = __raw_readl(S5P_APLL_CON0); + } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT))); + + /* 5. MUX_CORE_SEL = APLL */ + clk_set_parent(moutcore, mout_apll); + + do { + tmp = __raw_readl(S5P_CLKMUX_STATCPU); + tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK; + } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)); +} + +static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index) +{ + unsigned int tmp; + + if (old_index > new_index) { + /* The frequency changing to L0 needs to change apll */ + if (freqs.new == s5pv310_freq_table[L0].frequency) { + /* 1. Change the system clock divider values */ + s5pv310_set_clkdiv(new_index); + + /* 2. Change the apll m,p,s value */ + s5pv310_set_apll(new_index); + } else { + /* 1. Change the system clock divider values */ + s5pv310_set_clkdiv(new_index); + + /* 2. Change just s value in apll m,p,s value */ + tmp = __raw_readl(S5P_APLL_CON0); + tmp &= ~(0x7 << 0); + tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); + __raw_writel(tmp, S5P_APLL_CON0); + } + } + + else if (old_index < new_index) { + /* The frequency changing from L0 needs to change apll */ + if (freqs.old == s5pv310_freq_table[L0].frequency) { + /* 1. Change the apll m,p,s value */ + s5pv310_set_apll(new_index); + + /* 2. Change the system clock divider values */ + s5pv310_set_clkdiv(new_index); + } else { + /* 1. Change just s value in apll m,p,s value */ + tmp = __raw_readl(S5P_APLL_CON0); + tmp &= ~(0x7 << 0); + tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); + __raw_writel(tmp, S5P_APLL_CON0); + + /* 2. Change the system clock divider values */ + s5pv310_set_clkdiv(new_index); + } + } +} + static int s5pv310_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) { - unsigned int index, div_index, tmp; + unsigned int index, old_index; unsigned int arm_volt, int_volt; - unsigned int need_apll = 0; freqs.old = s5pv310_getspeed(policy->cpu); + if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, + freqs.old, relation, &old_index)) + return -EINVAL; + if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, target_freq, relation, &index)) return -EINVAL; @@ -322,19 +425,6 @@ static int s5pv310_target(struct cpufreq_policy *policy, if (freqs.new == freqs.old) return 0; - /* - * If freqs.new is higher than 800MHz - * cpufreq driver should turn on apll - */ - if (index < L1) - need_apll = 1; - - /* If the memory type is LPDDR2, use L4-B instead of L4-A */ - if ((index == L4) && (memtype == LPDDR2)) - div_index = index + 1; - else - div_index = index; - /* get the voltage value */ arm_volt = s5pv310_volt_table[index].arm_volt; int_volt = s5pv310_volt_table[index].int_volt; @@ -351,69 +441,7 @@ static int s5pv310_target(struct cpufreq_policy *policy, } /* Clock Configuration Procedure */ - - /* 1. Change the system clock divider values */ - s5pv310_set_clkdiv(div_index); - - /* 2. Change the divider values for special clocks in CMU_TOP */ - /* currently nothing */ - - /* 3. Change the XPLL values or Select the parent XPLL */ - if (need_apll) { - if (!armclk_use_apll) { - /* - * If the parent clock of armclk isn't apll - * here need to set apll (include m,p,s value) - */ - - /* a. MUX_CORE_SEL = MPLL, - * ARMCLK uses MPLL for lock time */ - clk_set_parent(moutcore, mout_mpll); - - do { - tmp = (__raw_readl(S5P_CLKMUX_STATCPU) - >> S5P_CLKSRC_CPU_MUXCORE_SHIFT); - tmp &= 0x7; - } while (tmp != 0x2); - - /* b. Set APLL Lock time */ - __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK); - - /* c. Change PLL PMS values */ - __raw_writel(S5P_APLL_VAL_1000, S5P_APLL_CON0); - - /* d. Turn on a PLL */ - tmp = __raw_readl(S5P_APLL_CON0); - tmp |= (0x1 << S5P_APLLCON0_ENABLE_SHIFT); - __raw_writel(tmp, S5P_APLL_CON0); - - /* e. wait_lock_time */ - do { - tmp = __raw_readl(S5P_APLL_CON0); - } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT))); - - armclk_use_apll = 1; - - } - - /* MUX_CORE_SEL = APLL */ - clk_set_parent(moutcore, mout_apll); - - do { - tmp = __raw_readl(S5P_CLKMUX_STATCPU); - tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK; - } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)); - - } else { - if (clk_get_parent(moutcore) != mout_mpll) { - clk_set_parent(moutcore, mout_mpll); - - do { - tmp = __raw_readl(S5P_CLKMUX_STATCPU); - tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK; - } while (tmp != (0x2 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)); - } - } + s5pv310_set_frequency(old_index, index); /* control regulator */ if (freqs.new < freqs.old) { @@ -477,8 +505,6 @@ static struct cpufreq_driver s5pv310_driver = { static int __init s5pv310_cpufreq_init(void) { - unsigned int tmp; - cpu_clk = clk_get(NULL, "armclk"); if (IS_ERR(cpu_clk)) return PTR_ERR(cpu_clk); @@ -509,13 +535,6 @@ static int __init s5pv310_cpufreq_init(void) } #endif - /* check parent clock of armclk */ - tmp = __raw_readl(S5P_CLKSRC_CPU); - if (tmp & S5P_CLKSRC_CPU_MUXCORE_SHIFT) - armclk_use_apll = 0; - else - armclk_use_apll = 1; - /* * Check DRAM type. * Because DVFS level is different according to DRAM type. -- cgit v1.2.3-18-g5258 From 877d1b571d7763dbf57e38de2827177ad5369e64 Mon Sep 17 00:00:00 2001 From: Jaecheol Lee Date: Thu, 23 Dec 2010 14:25:31 +0900 Subject: ARM: S5PV310: Add FOUT APLL get rate function FOUT APLL clock is used as a source of ARM core clock. So we need that the clock source can be changed dynamically by using CPUFREQ driver. This patch can give correct frequency when calling clk_get_rate() function. Signed-off-by: Jaecheol Lee Signed-off-by: Sangwook Ju Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index fdce2b48efc..752a07ed7c1 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -990,6 +990,17 @@ static struct clksrc_clk *sysclks[] = { &clk_dout_mmc4, }; +static int xtal_rate; + +static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk) +{ + return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); +} + +static struct clk_ops s5pv310_fout_apll_ops = { + .get_rate = s5pv310_fout_apll_get_rate, +}; + void __init_or_cpufreq s5pv310_setup_clocks(void) { struct clk *xtal_clk; @@ -1013,6 +1024,9 @@ void __init_or_cpufreq s5pv310_setup_clocks(void) BUG_ON(IS_ERR(xtal_clk)); xtal = clk_get_rate(xtal_clk); + + xtal_rate = xtal; + clk_put(xtal_clk); printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); @@ -1026,7 +1040,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void) vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), __raw_readl(S5P_VPLL_CON1), pll_4650); - clk_fout_apll.rate = apll; + clk_fout_apll.ops = &s5pv310_fout_apll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; clk_fout_vpll.rate = vpll; -- cgit v1.2.3-18-g5258 From b333fb16dcc50541df1930addea3eac03c838a4c Mon Sep 17 00:00:00 2001 From: Sunyoung Kang Date: Thu, 16 Sep 2010 11:11:45 +0900 Subject: ARM: S5PV310: Update Kconfig and Makefile for supporting CPUFREQ This patch adds ARCH_HAS_CPUFREQ in Kconfig of ARCH_S5PV310 and updates Makefile for supporting build S5PV310 CPUFREQ driver. Signed-off-by: Sunyoung Kang Signed-off-by: Kukjin Kim --- arch/arm/Kconfig | 1 + arch/arm/mach-s5pv310/Makefile | 1 + 2 files changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d56d21c0573..5ecaec63a47 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -738,6 +738,7 @@ config ARCH_S5PV310 select ARCH_SPARSEMEM_ENABLE select GENERIC_GPIO select HAVE_CLK + select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_I2C if I2C diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile index 84afc64e7c0..6a8a1ef00c3 100644 --- a/arch/arm/mach-s5pv310/Makefile +++ b/arch/arm/mach-s5pv310/Makefile @@ -14,6 +14,7 @@ obj- := obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o +obj-$(CONFIG_CPU_FREQ) += cpufreq.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o -- cgit v1.2.3-18-g5258 From 85e0dbf94eb369882d5ad768e3687a4af6f36dbe Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:44:28 +0900 Subject: ARM: S5P6442: Implement i2c-gpio config Signed-off-by: Jassi Brar Acked-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p6442/setup-i2c0.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-s5p6442/setup-i2c0.c b/arch/arm/mach-s5p6442/setup-i2c0.c index 662695dd776..aad85656b0c 100644 --- a/arch/arm/mach-s5p6442/setup-i2c0.c +++ b/arch/arm/mach-s5p6442/setup-i2c0.c @@ -14,12 +14,15 @@ #include #include +#include struct platform_device; /* don't need the contents */ +#include #include void s3c_i2c0_cfg_gpio(struct platform_device *dev) { - /* Will be populated later */ + s3c_gpio_cfgall_range(S5P6442_GPD1(0), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); } -- cgit v1.2.3-18-g5258 From c204fb151781dedef364ded77324b5c77a5b83a9 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:44:30 +0900 Subject: ARM: S5P6442: Enable I2C0 device on SMDK6442 This patch enables I2C0 device for WM8580 on SMDK6442. Signed-off-by: Jassi Brar Acked-by: Mark Brown [kgene.kim@samsung.com: minor changed title and description] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p6442/mach-smdk6442.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c index 819fd80d00a..e69f137b0a3 100644 --- a/arch/arm/mach-s5p6442/mach-smdk6442.c +++ b/arch/arm/mach-s5p6442/mach-smdk6442.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -25,6 +26,7 @@ #include #include #include +#include /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -65,10 +67,15 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = { }; static struct platform_device *smdk6442_devices[] __initdata = { + &s3c_device_i2c0, &s5p6442_device_iis0, &s3c_device_wdt, }; +static struct i2c_board_info smdk6442_i2c_devs0[] __initdata = { + { I2C_BOARD_INFO("wm8580", 0x1b), }, +}; + static void __init smdk6442_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -78,6 +85,9 @@ static void __init smdk6442_map_io(void) static void __init smdk6442_machine_init(void) { + s3c_i2c0_set_platdata(NULL); + i2c_register_board_info(0, smdk6442_i2c_devs0, + ARRAY_SIZE(smdk6442_i2c_devs0)); platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices)); } -- cgit v1.2.3-18-g5258 From 6cb26da8205a47cab75118af8849766a10d098db Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:44:36 +0900 Subject: ARM: S5P6450: Define clocks for I2S Define missing controller clocks for the I2S-0,1 blocks. Signed-off-by: Jassi Brar Acked-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/clock-s5p6450.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index 7fc6abd3591..d8b20ee8cc8 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -260,6 +260,18 @@ static struct clk init_clocks_disable[] = { .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 26), + }, { + .name = "iis", + .id = 1, + .parent = &clk_pclk_low.clk, + .enable = s5p64x0_pclk_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "iis", + .id = 2, + .parent = &clk_pclk_low.clk, + .enable = s5p64x0_pclk_ctrl, + .ctrlbit = (1 << 16), }, { .name = "i2c", .id = 1, -- cgit v1.2.3-18-g5258 From cf57b1a7f288829547b03385bf22124a96c82a4e Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:44:39 +0900 Subject: ARM: S5P6450: Define base addresses for I2S Define the base address of I2S-1 and 2 for S5P6450. Signed-off-by: Jassi Brar Acked-by: Mark Brown [kgene.kim@samsung.com: Added description] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/include/mach/map.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h index 31e534156e0..4d3d332152d 100644 --- a/arch/arm/mach-s5p64x0/include/mach/map.h +++ b/arch/arm/mach-s5p64x0/include/mach/map.h @@ -63,6 +63,8 @@ #define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) #define S5P64X0_PA_I2S (0xF2000000) +#define S5P6450_PA_I2S1 0xF2800000 +#define S5P6450_PA_I2S2 0xF2900000 #define S5P64X0_PA_PCM (0xF2100000) -- cgit v1.2.3-18-g5258 From e0b9c88b12dd190591eb5903cd0572a97d2a6bf1 Mon Sep 17 00:00:00 2001 From: Rajeshwari Shinde Date: Tue, 21 Dec 2010 09:44:42 +0900 Subject: ARM: S5P64X0: Segregate audio devices Segregate I2S devices for S5P6440 and S5P6450. Signed-off-by: Rajeshwari Shinde Signed-off-by: Jassi Brar Acked-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/dev-audio.c | 123 ++++++++++++++++++++++++++---- arch/arm/plat-samsung/include/plat/devs.h | 2 + 2 files changed, 112 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c index 14f89e73b8d..35f1f226dab 100644 --- a/arch/arm/mach-s5p64x0/dev-audio.c +++ b/arch/arm/mach-s5p64x0/dev-audio.c @@ -24,13 +24,13 @@ static const char *rclksrc[] = { [1] = "sclk_audio2", }; -static int s5p64x0_cfg_i2s(struct platform_device *pdev) +static int s5p6440_cfg_i2s(struct platform_device *pdev) { - /* configure GPIO for i2s port */ switch (pdev->id) { case 0: - s3c_gpio_cfgpin_range(S5P6440_GPR(4), 5, S3C_GPIO_SFN(5)); - s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin_range(S5P6440_GPC(4), 2, S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5P6440_GPC(7), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin_range(S5P6440_GPH(6), 4, S3C_GPIO_SFN(5)); break; default: printk(KERN_ERR "Invalid Device %d\n", pdev->id); @@ -40,8 +40,8 @@ static int s5p64x0_cfg_i2s(struct platform_device *pdev) return 0; } -static struct s3c_audio_pdata s5p64x0_i2s_pdata = { - .cfg_gpio = s5p64x0_cfg_i2s, +static struct s3c_audio_pdata s5p6440_i2s_pdata = { + .cfg_gpio = s5p6440_cfg_i2s, .type = { .i2s = { .quirks = QUIRK_PRI_6CHAN, @@ -50,7 +50,7 @@ static struct s3c_audio_pdata s5p64x0_i2s_pdata = { }, }; -static struct resource s5p64x0_iis0_resource[] = { +static struct resource s5p64x0_i2s0_resource[] = { [0] = { .start = S5P64X0_PA_I2S, .end = S5P64X0_PA_I2S + 0x100 - 1, @@ -71,20 +71,117 @@ static struct resource s5p64x0_iis0_resource[] = { struct platform_device s5p6440_device_iis = { .name = "samsung-i2s", .id = 0, - .num_resources = ARRAY_SIZE(s5p64x0_iis0_resource), - .resource = s5p64x0_iis0_resource, + .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource), + .resource = s5p64x0_i2s0_resource, .dev = { - .platform_data = &s5p64x0_i2s_pdata, + .platform_data = &s5p6440_i2s_pdata, + }, +}; + +static int s5p6450_cfg_i2s(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5)); + break; + case 1: + s3c_gpio_cfgpin(S5P6440_GPB(4), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin_range(S5P6450_GPC(0), 4, S3C_GPIO_SFN(5)); + break; + case 2: + s3c_gpio_cfgpin_range(S5P6450_GPK(0), 5, S3C_GPIO_SFN(5)); + break; + default: + printk(KERN_ERR "Invalid Device %d\n", pdev->id); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s5p6450_i2s0_pdata = { + .cfg_gpio = s5p6450_cfg_i2s, + .type = { + .i2s = { + .quirks = QUIRK_PRI_6CHAN, + .src_clk = rclksrc, + }, }, }; struct platform_device s5p6450_device_iis0 = { .name = "samsung-i2s", .id = 0, - .num_resources = ARRAY_SIZE(s5p64x0_iis0_resource), - .resource = s5p64x0_iis0_resource, + .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource), + .resource = s5p64x0_i2s0_resource, + .dev = { + .platform_data = &s5p6450_i2s0_pdata, + }, +}; + +static struct s3c_audio_pdata s5p6450_i2s_pdata = { + .cfg_gpio = s5p6450_cfg_i2s, + .type = { + .i2s = { + .src_clk = rclksrc, + }, + }, +}; + +static struct resource s5p6450_i2s1_resource[] = { + [0] = { + .start = S5P6450_PA_I2S1, + .end = S5P6450_PA_I2S1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S1_TX, + .end = DMACH_I2S1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S1_RX, + .end = DMACH_I2S1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5p6450_device_iis1 = { + .name = "samsung-i2s", + .id = 1, + .num_resources = ARRAY_SIZE(s5p6450_i2s1_resource), + .resource = s5p6450_i2s1_resource, + .dev = { + .platform_data = &s5p6450_i2s_pdata, + }, +}; + +static struct resource s5p6450_i2s2_resource[] = { + [0] = { + .start = S5P6450_PA_I2S2, + .end = S5P6450_PA_I2S2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S2_TX, + .end = DMACH_I2S2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S2_RX, + .end = DMACH_I2S2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5p6450_device_iis2 = { + .name = "samsung-i2s", + .id = 2, + .num_resources = ARRAY_SIZE(s5p6450_i2s2_resource), + .resource = s5p6450_i2s2_resource, .dev = { - .platform_data = &s5p64x0_i2s_pdata, + .platform_data = &s5p6450_i2s_pdata, }, }; diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index dec0ded6a5e..126196e9983 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -115,6 +115,8 @@ extern struct platform_device s5p6440_device_pcm; extern struct platform_device s5p6440_device_iis; extern struct platform_device s5p6450_device_iis0; +extern struct platform_device s5p6450_device_iis1; +extern struct platform_device s5p6450_device_iis2; extern struct platform_device s5p6450_device_pcm0; extern struct platform_device s5pc100_device_ac97; -- cgit v1.2.3-18-g5258 From 149bb5bcc3b1c5f4044e0ad088afdc8a12b51c64 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:46:29 +0900 Subject: ARM: S5P6440: Enable I2S device to work on SMDK6440 Add missing virtual ASoC DMA device and WM8580 as I2C slave, so that the I2S can work on SMDK6440. [kgene.kim@samsung.com: removed virtual ASoC DMA device to avoid build error and it will be added next time] Signed-off-by: Jassi Brar Acked-by: Mark Brown [kgene.kim@samsung.com: minor changed title] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/mach-smdk6440.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c index 87c3f03c618..e9802755dae 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c @@ -117,6 +117,7 @@ static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = { static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = { { I2C_BOARD_INFO("24c08", 0x50), }, + { I2C_BOARD_INFO("wm8580", 0x1b), }, }; static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = { -- cgit v1.2.3-18-g5258 From fcf8897d038b819267cae2c661438331785c2979 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:48:32 +0900 Subject: ARM: S5P6450: Enable I2S device to work on SMDK6450 Add missing virtual ASoC DMA device and WM8580 as I2C slave, so that the I2S can work on SMDK6450. [kgene.kim@samsung.com: removed virtual ASoC DMA device to avoid build error and it will be added next time] Signed-off-by: Jassi Brar Acked-by: Mark Brown [kgene.kim@samsung.com: minor changed title] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/mach-smdk6450.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c index d609f5af2b9..b78f5629278 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c @@ -135,6 +135,7 @@ static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = { }; static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = { + { I2C_BOARD_INFO("wm8580", 0x1b), }, { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung KS24C080C EEPROM */ }; -- cgit v1.2.3-18-g5258 From 0031e9d91e45d1ddf17702c1f105096b8740d456 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:48:35 +0900 Subject: ARM: S5PV210: Enable I2S device to work on SMDKC110 Add missing virtual ASoC DMA device and WM8580 as I2C slave, so that the I2S can work on SMDKC110. [kgene.kim@samsung.com: removed virtual ASoC DMA device to avoid build error and it will be added next time] Signed-off-by: Jassi Brar Acked-by: Mark Brown [kgene.kim@samsung.com: minor changed title] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv210/mach-smdkc110.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c index 5dd1681c069..bb20a14da10 100644 --- a/arch/arm/mach-s5pv210/mach-smdkc110.c +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c @@ -94,6 +94,7 @@ static struct platform_device *smdkc110_devices[] __initdata = { static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = { { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */ + { I2C_BOARD_INFO("wm8580", 0x1b), }, }; static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = { -- cgit v1.2.3-18-g5258 From d8710bc8de918059efaadd126320c2b34c514548 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:48:37 +0900 Subject: ARM: S5PV210: Enable I2S device to work on SMDKV210 Add missing virtual ASoC DMA device and WM8580 as I2C slave, so that the I2S can work on SMDKV210. [kgene.kim@samsung.com: removed virtual ASoC DMA device to avoid build error and it will be added next time] Signed-off-by: Jassi Brar Acked-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv210/mach-smdkv210.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index 1fbc45b2a43..82e63562507 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -123,6 +123,7 @@ static struct platform_device *smdkv210_devices[] __initdata = { static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = { { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */ + { I2C_BOARD_INFO("wm8580", 0x1b), }, }; static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = { -- cgit v1.2.3-18-g5258 From f5cc4354907dccd6bb343cca18074c751a94f913 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:52:14 +0900 Subject: ARM: S5PV310: Enable I2C1 device Enable the I2C1 device on SMDKV310 and SMDKC210. Signed-off-by: Jassi Brar Acked-by: Mark Brown [kgene.kim@samsung.com: minor changed title] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index d64efe0d4c9..3e1fe9d6b1f 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -70,10 +70,12 @@ config MACH_SMDKC210 select CPU_S5PV310 select S3C_DEV_RTC select S3C_DEV_WDT + select S3C_DEV_I2C1 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 + select S5PV310_SETUP_I2C1 select S5PV310_SETUP_SDHCI help Machine support for Samsung SMDKC210 @@ -98,10 +100,12 @@ config MACH_SMDKV310 select CPU_S5PV310 select S3C_DEV_RTC select S3C_DEV_WDT + select S3C_DEV_I2C1 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 + select S5PV310_SETUP_I2C1 select S5PV310_SETUP_SDHCI help Machine support for Samsung SMDKV310 -- cgit v1.2.3-18-g5258 From 3055c6dad620af9e2c5432feb5ec7d5ac46d54b0 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:54:35 +0900 Subject: ARM: S5PV310: Add PDMA clocks Define PDMA clocks for the controller 0 and 1. Signed-off-by: Jassi Brar Acked-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c in