From 0b2c3afdaaaa3e577300b2235df43eb8af00020b Mon Sep 17 00:00:00 2001 From: Chris Zankel Date: Tue, 12 Feb 2008 10:11:45 -0800 Subject: [XTENSA] Fix icache flush for cache aliasing Set the execution bit in the temporary TLB when we flush the instruction cache. Signed-off-by: Chris Zankel --- arch/xtensa/mm/misc.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/xtensa') diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S index e1f880368e3..c885664211d 100644 --- a/arch/xtensa/mm/misc.S +++ b/arch/xtensa/mm/misc.S @@ -295,7 +295,7 @@ ENTRY(__tlbtemp_mapping_itlb) ENTRY(__invalidate_icache_page_alias) entry sp, 16 - addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) + addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE) mov a4, a2 witlb a6, a2 isync -- cgit v1.2.3-18-g5258