From 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sat, 16 Apr 2005 15:20:36 -0700 Subject: Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip! --- arch/sparc/kernel/Makefile | 27 + arch/sparc/kernel/apc.c | 186 ++++ arch/sparc/kernel/asm-offsets.c | 45 + arch/sparc/kernel/auxio.c | 138 +++ arch/sparc/kernel/cpu.c | 168 ++++ arch/sparc/kernel/devices.c | 160 ++++ arch/sparc/kernel/ebus.c | 361 ++++++++ arch/sparc/kernel/entry.S | 1956 +++++++++++++++++++++++++++++++++++++++ arch/sparc/kernel/errtbls.c | 276 ++++++ arch/sparc/kernel/etrap.S | 321 +++++++ arch/sparc/kernel/head.S | 1326 ++++++++++++++++++++++++++ arch/sparc/kernel/idprom.c | 108 +++ arch/sparc/kernel/init_task.c | 28 + arch/sparc/kernel/ioport.c | 731 +++++++++++++++ arch/sparc/kernel/irq.c | 614 ++++++++++++ arch/sparc/kernel/module.c | 159 ++++ arch/sparc/kernel/muldiv.c | 240 +++++ arch/sparc/kernel/pcic.c | 1041 +++++++++++++++++++++ arch/sparc/kernel/pmc.c | 99 ++ arch/sparc/kernel/process.c | 746 +++++++++++++++ arch/sparc/kernel/ptrace.c | 632 +++++++++++++ arch/sparc/kernel/rtrap.S | 319 +++++++ arch/sparc/kernel/sclow.S | 86 ++ arch/sparc/kernel/semaphore.c | 155 ++++ arch/sparc/kernel/setup.c | 476 ++++++++++ arch/sparc/kernel/signal.c | 1181 +++++++++++++++++++++++ arch/sparc/kernel/smp.c | 295 ++++++ arch/sparc/kernel/sparc-stub.c | 724 +++++++++++++++ arch/sparc/kernel/sparc_ksyms.c | 334 +++++++ arch/sparc/kernel/sun4c_irq.c | 250 +++++ arch/sparc/kernel/sun4d_irq.c | 594 ++++++++++++ arch/sparc/kernel/sun4d_smp.c | 486 ++++++++++ arch/sparc/kernel/sun4m_irq.c | 399 ++++++++ arch/sparc/kernel/sun4m_smp.c | 451 +++++++++ arch/sparc/kernel/sun4setup.c | 75 ++ arch/sparc/kernel/sunos_asm.S | 67 ++ arch/sparc/kernel/sunos_ioctl.c | 231 +++++ arch/sparc/kernel/sys_solaris.c | 37 + arch/sparc/kernel/sys_sparc.c | 485 ++++++++++ arch/sparc/kernel/sys_sunos.c | 1194 ++++++++++++++++++++++++ arch/sparc/kernel/systbls.S | 186 ++++ arch/sparc/kernel/tadpole.c | 126 +++ arch/sparc/kernel/tick14.c | 85 ++ arch/sparc/kernel/time.c | 641 +++++++++++++ arch/sparc/kernel/trampoline.S | 162 ++++ arch/sparc/kernel/traps.c | 515 +++++++++++ arch/sparc/kernel/unaligned.c | 548 +++++++++++ arch/sparc/kernel/vmlinux.lds.S | 103 +++ arch/sparc/kernel/windows.c | 127 +++ arch/sparc/kernel/wof.S | 428 +++++++++ arch/sparc/kernel/wuf.S | 360 +++++++ 51 files changed, 20482 insertions(+) create mode 100644 arch/sparc/kernel/Makefile create mode 100644 arch/sparc/kernel/apc.c create mode 100644 arch/sparc/kernel/asm-offsets.c create mode 100644 arch/sparc/kernel/auxio.c create mode 100644 arch/sparc/kernel/cpu.c create mode 100644 arch/sparc/kernel/devices.c create mode 100644 arch/sparc/kernel/ebus.c create mode 100644 arch/sparc/kernel/entry.S create mode 100644 arch/sparc/kernel/errtbls.c create mode 100644 arch/sparc/kernel/etrap.S create mode 100644 arch/sparc/kernel/head.S create mode 100644 arch/sparc/kernel/idprom.c create mode 100644 arch/sparc/kernel/init_task.c create mode 100644 arch/sparc/kernel/ioport.c create mode 100644 arch/sparc/kernel/irq.c create mode 100644 arch/sparc/kernel/module.c create mode 100644 arch/sparc/kernel/muldiv.c create mode 100644 arch/sparc/kernel/pcic.c create mode 100644 arch/sparc/kernel/pmc.c create mode 100644 arch/sparc/kernel/process.c create mode 100644 arch/sparc/kernel/ptrace.c create mode 100644 arch/sparc/kernel/rtrap.S create mode 100644 arch/sparc/kernel/sclow.S create mode 100644 arch/sparc/kernel/semaphore.c create mode 100644 arch/sparc/kernel/setup.c create mode 100644 arch/sparc/kernel/signal.c create mode 100644 arch/sparc/kernel/smp.c create mode 100644 arch/sparc/kernel/sparc-stub.c create mode 100644 arch/sparc/kernel/sparc_ksyms.c create mode 100644 arch/sparc/kernel/sun4c_irq.c create mode 100644 arch/sparc/kernel/sun4d_irq.c create mode 100644 arch/sparc/kernel/sun4d_smp.c create mode 100644 arch/sparc/kernel/sun4m_irq.c create mode 100644 arch/sparc/kernel/sun4m_smp.c create mode 100644 arch/sparc/kernel/sun4setup.c create mode 100644 arch/sparc/kernel/sunos_asm.S create mode 100644 arch/sparc/kernel/sunos_ioctl.c create mode 100644 arch/sparc/kernel/sys_solaris.c create mode 100644 arch/sparc/kernel/sys_sparc.c create mode 100644 arch/sparc/kernel/sys_sunos.c create mode 100644 arch/sparc/kernel/systbls.S create mode 100644 arch/sparc/kernel/tadpole.c create mode 100644 arch/sparc/kernel/tick14.c create mode 100644 arch/sparc/kernel/time.c create mode 100644 arch/sparc/kernel/trampoline.S create mode 100644 arch/sparc/kernel/traps.c create mode 100644 arch/sparc/kernel/unaligned.c create mode 100644 arch/sparc/kernel/vmlinux.lds.S create mode 100644 arch/sparc/kernel/windows.c create mode 100644 arch/sparc/kernel/wof.S create mode 100644 arch/sparc/kernel/wuf.S (limited to 'arch/sparc/kernel') diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile new file mode 100644 index 00000000000..3d22ba2af01 --- /dev/null +++ b/arch/sparc/kernel/Makefile @@ -0,0 +1,27 @@ +# $Id: Makefile,v 1.62 2000/12/15 00:41:17 davem Exp $ +# Makefile for the linux kernel. +# + +extra-y := head.o init_task.o vmlinux.lds + +EXTRA_AFLAGS := -ansi + +IRQ_OBJS := irq.o sun4m_irq.o sun4c_irq.o sun4d_irq.o +obj-y := entry.o wof.o wuf.o etrap.o rtrap.o traps.o $(IRQ_OBJS) \ + process.o signal.o ioport.o setup.o idprom.o \ + sys_sparc.o sunos_asm.o systbls.o \ + time.o windows.o cpu.o devices.o sclow.o \ + tadpole.o tick14.o ptrace.o sys_solaris.o \ + unaligned.o muldiv.o semaphore.o + +obj-$(CONFIG_PCI) += pcic.o +obj-$(CONFIG_SUN4) += sun4setup.o +obj-$(CONFIG_SMP) += trampoline.o smp.o sun4m_smp.o sun4d_smp.o +obj-$(CONFIG_SUN_AUXIO) += auxio.o +obj-$(CONFIG_PCI) += ebus.o +obj-$(CONFIG_SUN_PM) += apc.o pmc.o +obj-$(CONFIG_MODULES) += module.o sparc_ksyms.o + +ifdef CONFIG_SUNOS_EMUL +obj-y += sys_sunos.o sunos_ioctl.o +endif diff --git a/arch/sparc/kernel/apc.c b/arch/sparc/kernel/apc.c new file mode 100644 index 00000000000..406dd94afb4 --- /dev/null +++ b/arch/sparc/kernel/apc.c @@ -0,0 +1,186 @@ +/* apc - Driver implementation for power management functions + * of Aurora Personality Chip (APC) on SPARCstation-4/5 and + * derivatives. + * + * Copyright (c) 2002 Eric Brower (ebrower@usa.net) + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* Debugging + * + * #define APC_DEBUG_LED + */ + +#define APC_MINOR MISC_DYNAMIC_MINOR +#define APC_OBPNAME "power-management" +#define APC_DEVNAME "apc" + +volatile static u8 __iomem *regs; +static int apc_regsize; +static int apc_no_idle __initdata = 0; + +#define apc_readb(offs) (sbus_readb(regs+offs)) +#define apc_writeb(val, offs) (sbus_writeb(val, regs+offs)) + +/* Specify "apc=noidle" on the kernel command line to + * disable APC CPU standby support. Certain prototype + * systems (SPARCstation-Fox) do not play well with APC + * CPU idle, so disable this if your system has APC and + * crashes randomly. + */ +static int __init apc_setup(char *str) +{ + if(!strncmp(str, "noidle", strlen("noidle"))) { + apc_no_idle = 1; + return 1; + } + return 0; +} +__setup("apc=", apc_setup); + +/* + * CPU idle callback function + * See .../arch/sparc/kernel/process.c + */ +void apc_swift_idle(void) +{ +#ifdef APC_DEBUG_LED + set_auxio(0x00, AUXIO_LED); +#endif + + apc_writeb(apc_readb(APC_IDLE_REG) | APC_IDLE_ON, APC_IDLE_REG); + +#ifdef APC_DEBUG_LED + set_auxio(AUXIO_LED, 0x00); +#endif +} + +static inline void apc_free(void) +{ + sbus_iounmap(regs, apc_regsize); +} + +static int apc_open(struct inode *inode, struct file *f) +{ + return 0; +} + +static int apc_release(struct inode *inode, struct file *f) +{ + return 0; +} + +static int apc_ioctl(struct inode *inode, struct file *f, + unsigned int cmd, unsigned long __arg) +{ + __u8 inarg, __user *arg; + + arg = (__u8 __user *) __arg; + switch (cmd) { + case APCIOCGFANCTL: + if (put_user(apc_readb(APC_FANCTL_REG) & APC_REGMASK, arg)) + return -EFAULT; + break; + + case APCIOCGCPWR: + if (put_user(apc_readb(APC_CPOWER_REG) & APC_REGMASK, arg)) + return -EFAULT; + break; + + case APCIOCGBPORT: + if (put_user(apc_readb(APC_BPORT_REG) & APC_BPMASK, arg)) + return -EFAULT; + break; + + case APCIOCSFANCTL: + if (get_user(inarg, arg)) + return -EFAULT; + apc_writeb(inarg & APC_REGMASK, APC_FANCTL_REG); + break; + case APCIOCSCPWR: + if (get_user(inarg, arg)) + return -EFAULT; + apc_writeb(inarg & APC_REGMASK, APC_CPOWER_REG); + break; + case APCIOCSBPORT: + if (get_user(inarg, arg)) + return -EFAULT; + apc_writeb(inarg & APC_BPMASK, APC_BPORT_REG); + break; + default: + return -EINVAL; + }; + + return 0; +} + +static struct file_operations apc_fops = { + .ioctl = apc_ioctl, + .open = apc_open, + .release = apc_release, +}; + +static struct miscdevice apc_miscdev = { APC_MINOR, APC_DEVNAME, &apc_fops }; + +static int __init apc_probe(void) +{ + struct sbus_bus *sbus = NULL; + struct sbus_dev *sdev = NULL; + int iTmp = 0; + + for_each_sbus(sbus) { + for_each_sbusdev(sdev, sbus) { + if (!strcmp(sdev->prom_name, APC_OBPNAME)) { + goto sbus_done; + } + } + } + +sbus_done: + if (!sdev) { + return -ENODEV; + } + + apc_regsize = sdev->reg_addrs[0].reg_size; + regs = sbus_ioremap(&sdev->resource[0], 0, + apc_regsize, APC_OBPNAME); + if(!regs) { + printk(KERN_ERR "%s: unable to map registers\n", APC_DEVNAME); + return -ENODEV; + } + + iTmp = misc_register(&apc_miscdev); + if (iTmp != 0) { + printk(KERN_ERR "%s: unable to register device\n", APC_DEVNAME); + apc_free(); + return -ENODEV; + } + + /* Assign power management IDLE handler */ + if(!apc_no_idle) + pm_idle = apc_swift_idle; + + printk(KERN_INFO "%s: power management initialized%s\n", + APC_DEVNAME, apc_no_idle ? " (CPU idle disabled)" : ""); + return 0; +} + +/* This driver is not critical to the boot process + * and is easiest to ioremap when SBus is already + * initialized, so we install ourselves thusly: + */ +__initcall(apc_probe); + diff --git a/arch/sparc/kernel/asm-offsets.c b/arch/sparc/kernel/asm-offsets.c new file mode 100644 index 00000000000..1f55231f07d --- /dev/null +++ b/arch/sparc/kernel/asm-offsets.c @@ -0,0 +1,45 @@ +/* + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * On sparc, thread_info data is static and TI_XXX offsets are computed by hand. + */ + +#include +#include +// #include + +#define DEFINE(sym, val) \ + asm volatile("\n->" #sym " %0 " #val : : "i" (val)) + +#define BLANK() asm volatile("\n->" : : ) + +int foo(void) +{ + DEFINE(AOFF_task_thread, offsetof(struct task_struct, thread)); + BLANK(); + /* XXX This is the stuff for sclow.S, kill it. */ + DEFINE(AOFF_task_pid, offsetof(struct task_struct, pid)); + DEFINE(AOFF_task_uid, offsetof(struct task_struct, uid)); + DEFINE(AOFF_task_gid, offsetof(struct task_struct, gid)); + DEFINE(AOFF_task_euid, offsetof(struct task_struct, euid)); + DEFINE(AOFF_task_egid, offsetof(struct task_struct, egid)); + /* DEFINE(THREAD_INFO, offsetof(struct task_struct, thread_info)); */ + DEFINE(ASIZ_task_uid, sizeof(current->uid)); + DEFINE(ASIZ_task_gid, sizeof(current->gid)); + DEFINE(ASIZ_task_euid, sizeof(current->euid)); + DEFINE(ASIZ_task_egid, sizeof(current->egid)); + BLANK(); + DEFINE(AOFF_thread_fork_kpsr, + offsetof(struct thread_struct, fork_kpsr)); + BLANK(); + DEFINE(AOFF_mm_context, offsetof(struct mm_struct, context)); + + /* DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28); */ + return 0; +} diff --git a/arch/sparc/kernel/auxio.c b/arch/sparc/kernel/auxio.c new file mode 100644 index 00000000000..d3b3648362c --- /dev/null +++ b/arch/sparc/kernel/auxio.c @@ -0,0 +1,138 @@ +/* auxio.c: Probing for the Sparc AUXIO register at boot time. + * + * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) + */ + +#include +#include +#include +#include +#include +#include +#include +#include /* memset(), Linux has no bzero() */ + +/* Probe and map in the Auxiliary I/O register */ + +/* auxio_register is not static because it is referenced + * in entry.S::floppy_tdone + */ +void __iomem *auxio_register = NULL; +static DEFINE_SPINLOCK(auxio_lock); + +void __init auxio_probe(void) +{ + int node, auxio_nd; + struct linux_prom_registers auxregs[1]; + struct resource r; + + switch (sparc_cpu_model) { + case sun4d: + case sun4: + return; + default: + break; + } + node = prom_getchild(prom_root_node); + auxio_nd = prom_searchsiblings(node, "auxiliary-io"); + if(!auxio_nd) { + node = prom_searchsiblings(node, "obio"); + node = prom_getchild(node); + auxio_nd = prom_searchsiblings(node, "auxio"); + if(!auxio_nd) { +#ifdef CONFIG_PCI + /* There may be auxio on Ebus */ + return; +#else + if(prom_searchsiblings(node, "leds")) { + /* VME chassis sun4m machine, no auxio exists. */ + return; + } + prom_printf("Cannot find auxio node, cannot continue...\n"); + prom_halt(); +#endif + } + } + if(prom_getproperty(auxio_nd, "reg", (char *) auxregs, sizeof(auxregs)) <= 0) + return; + prom_apply_obio_ranges(auxregs, 0x1); + /* Map the register both read and write */ + r.flags = auxregs[0].which_io & 0xF; + r.start = auxregs[0].phys_addr; + r.end = auxregs[0].phys_addr + auxregs[0].reg_size - 1; + auxio_register = sbus_ioremap(&r, 0, auxregs[0].reg_size, "auxio"); + /* Fix the address on sun4m and sun4c. */ + if((((unsigned long) auxregs[0].phys_addr) & 3) == 3 || + sparc_cpu_model == sun4c) + auxio_register += (3 - ((unsigned long)auxio_register & 3)); + + set_auxio(AUXIO_LED, 0); +} + +unsigned char get_auxio(void) +{ + if(auxio_register) + return sbus_readb(auxio_register); + return 0; +} + +void set_auxio(unsigned char bits_on, unsigned char bits_off) +{ + unsigned char regval; + unsigned long flags; + spin_lock_irqsave(&auxio_lock, flags); + switch(sparc_cpu_model) { + case sun4c: + regval = sbus_readb(auxio_register); + sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN, + auxio_register); + break; + case sun4m: + if(!auxio_register) + break; /* VME chassic sun4m, no auxio. */ + regval = sbus_readb(auxio_register); + sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN4M, + auxio_register); + break; + case sun4d: + break; + default: + panic("Can't set AUXIO register on this machine."); + }; + spin_unlock_irqrestore(&auxio_lock, flags); +} + + +/* sun4m power control register (AUXIO2) */ + +volatile unsigned char * auxio_power_register = NULL; + +void __init auxio_power_probe(void) +{ + struct linux_prom_registers regs; + int node; + struct resource r; + + /* Attempt to find the sun4m power control node. */ + node = prom_getchild(prom_root_node); + node = prom_searchsiblings(node, "obio"); + node = prom_getchild(node); + node = prom_searchsiblings(node, "power"); + if (node == 0 || node == -1) + return; + + /* Map the power control register. */ + if (prom_getproperty(node, "reg", (char *)®s, sizeof(regs)) <= 0) + return; + prom_apply_obio_ranges(®s, 1); + memset(&r, 0, sizeof(r)); + r.flags = regs.which_io & 0xF; + r.start = regs.phys_addr; + r.end = regs.phys_addr + regs.reg_size - 1; + auxio_power_register = (unsigned char *) sbus_ioremap(&r, 0, + regs.reg_size, "auxpower"); + + /* Display a quick message on the console. */ + if (auxio_power_register) + printk(KERN_INFO "Power off control detected.\n"); +} diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c new file mode 100644 index 00000000000..6a4ebc62193 --- /dev/null +++ b/arch/sparc/kernel/cpu.c @@ -0,0 +1,168 @@ +/* cpu.c: Dinky routines to look for the kind of Sparc cpu + * we are on. + * + * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 }; + +struct cpu_iu_info { + int psr_impl; + int psr_vers; + char* cpu_name; /* should be enough I hope... */ +}; + +struct cpu_fp_info { + int psr_impl; + int fp_vers; + char* fp_name; +}; + +/* In order to get the fpu type correct, you need to take the IDPROM's + * machine type value into consideration too. I will fix this. + */ +struct cpu_fp_info linux_sparc_fpu[] = { + { 0, 0, "Fujitsu MB86910 or Weitek WTL1164/5"}, + { 0, 1, "Fujitsu MB86911 or Weitek WTL1164/5 or LSI L64831"}, + { 0, 2, "LSI Logic L64802 or Texas Instruments ACT8847"}, + /* SparcStation SLC, SparcStation1 */ + { 0, 3, "Weitek WTL3170/2"}, + /* SPARCstation-5 */ + { 0, 4, "Lsi Logic/Meiko L64804 or compatible"}, + { 0, 5, "reserved"}, + { 0, 6, "reserved"}, + { 0, 7, "No FPU"}, + { 1, 0, "ROSS HyperSparc combined IU/FPU"}, + { 1, 1, "Lsi Logic L64814"}, + { 1, 2, "Texas Instruments TMS390-C602A"}, + { 1, 3, "Cypress CY7C602 FPU"}, + { 1, 4, "reserved"}, + { 1, 5, "reserved"}, + { 1, 6, "reserved"}, + { 1, 7, "No FPU"}, + { 2, 0, "BIT B5010 or B5110/20 or B5210"}, + { 2, 1, "reserved"}, + { 2, 2, "reserved"}, + { 2, 3, "reserved"}, + { 2, 4, "reserved"}, + { 2, 5, "reserved"}, + { 2, 6, "reserved"}, + { 2, 7, "No FPU"}, + /* SuperSparc 50 module */ + { 4, 0, "SuperSparc on-chip FPU"}, + /* SparcClassic */ + { 4, 4, "TI MicroSparc on chip FPU"}, + { 5, 0, "Matsushita MN10501"}, + { 5, 1, "reserved"}, + { 5, 2, "reserved"}, + { 5, 3, "reserved"}, + { 5, 4, "reserved"}, + { 5, 5, "reserved"}, + { 5, 6, "reserved"}, + { 5, 7, "No FPU"}, + { 9, 3, "Fujitsu or Weitek on-chip FPU"}, +}; + +#define NSPARCFPU (sizeof(linux_sparc_fpu)/sizeof(struct cpu_fp_info)) + +struct cpu_iu_info linux_sparc_chips[] = { + /* Sun4/100, 4/200, SLC */ + { 0, 0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"}, + /* borned STP1012PGA */ + { 0, 4, "Fujitsu MB86904"}, + { 0, 5, "Fujitsu TurboSparc MB86907"}, + /* SparcStation2, SparcServer 490 & 690 */ + { 1, 0, "LSI Logic Corporation - L64811"}, + /* SparcStation2 */ + { 1, 1, "Cypress/ROSS CY7C601"}, + /* Embedded controller */ + { 1, 3, "Cypress/ROSS CY7C611"}, + /* Ross Technologies HyperSparc */ + { 1, 0xf, "ROSS HyperSparc RT620"}, + { 1, 0xe, "ROSS HyperSparc RT625 or RT626"}, + /* ECL Implementation, CRAY S-MP Supercomputer... AIEEE! */ + /* Someone please write the code to support this beast! ;) */ + { 2, 0, "Bipolar Integrated Technology - B5010"}, + { 3, 0, "LSI Logic Corporation - unknown-type"}, + { 4, 0, "Texas Instruments, Inc. - SuperSparc-(II)"}, + /* SparcClassic -- borned STP1010TAB-50*/ + { 4, 1, "Texas Instruments, Inc. - MicroSparc"}, + { 4, 2, "Texas Instruments, Inc. - MicroSparc II"}, + { 4, 3, "Texas Instruments, Inc. - SuperSparc 51"}, + { 4, 4, "Texas Instruments, Inc. - SuperSparc 61"}, + { 4, 5, "Texas Instruments, Inc. - unknown"}, + { 5, 0, "Matsushita - MN10501"}, + { 6, 0, "Philips Corporation - unknown"}, + { 7, 0, "Harvest VLSI Design Center, Inc. - unknown"}, + /* Gallium arsenide 200MHz, BOOOOGOOOOMIPS!!! */ + { 8, 0, "Systems and Processes Engineering Corporation (SPEC)"}, + { 9, 0, "Fujitsu or Weitek Power-UP"}, + { 9, 1, "Fujitsu or Weitek Power-UP"}, + { 9, 2, "Fujitsu or Weitek Power-UP"}, + { 9, 3, "Fujitsu or Weitek Power-UP"}, + { 0xa, 0, "UNKNOWN CPU-VENDOR/TYPE"}, + { 0xb, 0, "UNKNOWN CPU-VENDOR/TYPE"}, + { 0xc, 0, "UNKNOWN CPU-VENDOR/TYPE"}, + { 0xd, 0, "UNKNOWN CPU-VENDOR/TYPE"}, + { 0xe, 0, "UNKNOWN CPU-VENDOR/TYPE"}, + { 0xf, 0, "UNKNOWN CPU-VENDOR/TYPE"}, +}; + +#define NSPARCCHIPS (sizeof(linux_sparc_chips)/sizeof(struct cpu_iu_info)) + +char *sparc_cpu_type; +char *sparc_fpu_type; + +unsigned int fsr_storage; + +void __init cpu_probe(void) +{ + int psr_impl, psr_vers, fpu_vers; + int i, psr; + + psr_impl = ((get_psr()>>28)&0xf); + psr_vers = ((get_psr()>>24)&0xf); + + psr = get_psr(); + put_psr(psr | PSR_EF); + fpu_vers = ((get_fsr()>>17)&0x7); + put_psr(psr); + + for(i = 0; i +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +extern void cpu_probe(void); +extern void clock_stop_probe(void); /* tadpole.c */ +extern void sun4c_probe_memerr_reg(void); + +static char *cpu_mid_prop(void) +{ + if (sparc_cpu_model == sun4d) + return "cpu-id"; + return "mid"; +} + +static int check_cpu_node(int nd, int *cur_inst, + int (*compare)(int, int, void *), void *compare_arg, + int *prom_node, int *mid) +{ + char node_str[128]; + + prom_getstring(nd, "device_type", node_str, sizeof(node_str)); + if (strcmp(node_str, "cpu")) + return -ENODEV; + + if (!compare(nd, *cur_inst, compare_arg)) { + if (prom_node) + *prom_node = nd; + if (mid) { + *mid = prom_getintdefault(nd, cpu_mid_prop(), 0); + if (sparc_cpu_model == sun4m) + *mid &= 3; + } + return 0; + } + + (*cur_inst)++; + + return -ENODEV; +} + +static int __cpu_find_by(int (*compare)(int, int, void *), void *compare_arg, + int *prom_node, int *mid) +{ + int nd, cur_inst, err; + + nd = prom_root_node; + cur_inst = 0; + + err = check_cpu_node(nd, &cur_inst, compare, compare_arg, + prom_node, mid); + if (!err) + return 0; + + nd = prom_getchild(nd); + while ((nd = prom_getsibling(nd)) != 0) { + err = check_cpu_node(nd, &cur_inst, compare, compare_arg, + prom_node, mid); + if (!err) + return 0; + } + + return -ENODEV; +} + +static int cpu_instance_compare(int nd, int instance, void *_arg) +{ + int desired_instance = (int) _arg; + + if (instance == desired_instance) + return 0; + return -ENODEV; +} + +int cpu_find_by_instance(int instance, int *prom_node, int *mid) +{ + return __cpu_find_by(cpu_instance_compare, (void *)instance, + prom_node, mid); +} + +static int cpu_mid_compare(int nd, int instance, void *_arg) +{ + int desired_mid = (int) _arg; + int this_mid; + + this_mid = prom_getintdefault(nd, cpu_mid_prop(), 0); + if (this_mid == desired_mid + || (sparc_cpu_model == sun4m && (this_mid & 3) == desired_mid)) + return 0; + return -ENODEV; +} + +int cpu_find_by_mid(int mid, int *prom_node) +{ + return __cpu_find_by(cpu_mid_compare, (void *)mid, + prom_node, NULL); +} + +/* sun4m uses truncated mids since we base the cpuid on the ttable/irqset + * address (0-3). This gives us the true hardware mid, which might have + * some other bits set. On 4d hardware and software mids are the same. + */ +int cpu_get_hwmid(int prom_node) +{ + return prom_getintdefault(prom_node, cpu_mid_prop(), -ENODEV); +} + +void __init device_scan(void) +{ + prom_printf("Booting Linux...\n"); + +#ifndef CONFIG_SMP + { + int err, cpu_node; + err = cpu_find_by_instance(0, &cpu_node, NULL); + if (err) { + /* Probably a sun4e, Sun is trying to trick us ;-) */ + prom_printf("No cpu nodes, cannot continue\n"); + prom_halt(); + } + cpu_data(0).clock_tick = prom_getintdefault(cpu_node, + "clock-frequency", + 0); + } +#endif /* !CONFIG_SMP */ + + cpu_probe(); +#ifdef CONFIG_SUN_AUXIO + { + extern void auxio_probe(void); + extern void auxio_power_probe(void); + auxio_probe(); + auxio_power_probe(); + } +#endif + clock_stop_probe(); + + if (ARCH_SUN4C_SUN4) + sun4c_probe_memerr_reg(); + + return; +} diff --git a/arch/sparc/kernel/ebus.c b/arch/sparc/kernel/ebus.c new file mode 100644 index 00000000000..1754192c69d --- /dev/null +++ b/arch/sparc/kernel/ebus.c @@ -0,0 +1,361 @@ +/* $Id: ebus.c,v 1.20 2002/01/05 01:13:43 davem Exp $ + * ebus.c: PCI to EBus bridge device. + * + * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) + * + * Adopted for sparc by V. Roganov and G. Raiko. + * Fixes for different platforms by Pete Zaitcev. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +struct linux_ebus *ebus_chain = 0; + +/* We are together with pcic.c under CONFIG_PCI. */ +extern unsigned int pcic_pin_to_irq(unsigned int, char *name); + +/* + * IRQ Blacklist + * Here we list PROMs and systems that are known to supply crap as IRQ numbers. + */ +struct ebus_device_irq { + char *name; + unsigned int pin; +}; + +struct ebus_system_entry { + char *esname; + struct ebus_device_irq *ipt; +}; + +static struct ebus_device_irq je1_1[] = { + { "8042", 3 }, + { "SUNW,CS4231", 0 }, + { "parallel", 0 }, + { "se", 2 }, + { 0, 0 } +}; + +/* + * Gleb's JE1 supplied reasonable pin numbers, but mine did not (OBP 2.32). + * Blacklist the sucker... Note that Gleb's system will work. + */ +static struct ebus_system_entry ebus_blacklist[] = { + { "SUNW,JavaEngine1", je1_1 }, + { 0, 0 } +}; + +static struct ebus_device_irq *ebus_blackp = NULL; + +/* + */ +static inline unsigned long ebus_alloc(size_t size) +{ + return (unsigned long)kmalloc(size, GFP_ATOMIC); +} + +/* + */ +int __init ebus_blacklist_irq(char *name) +{ + struct ebus_device_irq *dp; + + if ((dp = ebus_blackp) != NULL) { + for (; dp->name != NULL; dp++) { + if (strcmp(name, dp->name) == 0) { + return pcic_pin_to_irq(dp->pin, name); + } + } + } + return 0; +} + +void __init fill_ebus_child(int node, struct linux_prom_registers *preg, + struct linux_ebus_child *dev) +{ + int regs[PROMREG_MAX]; + int irqs[PROMREG_MAX]; + char lbuf[128]; + int i, len; + + dev->prom_node = node; + prom_getstring(node, "name", lbuf, sizeof(lbuf)); + strcpy(dev->prom_name, lbuf); + + len = prom_getproperty(node, "reg", (void *)regs, sizeof(regs)); + if (len == -1) len = 0; + dev->num_addrs = len / sizeof(regs[0]); + + for (i = 0; i < dev->num_addrs; i++) { + if (regs[i] >= dev->parent->num_addrs) { + prom_printf("UGH: property for %s was %d, need < %d\n", + dev->prom_name, len, dev->parent->num_addrs); + panic(__FUNCTION__); + } + dev->resource[i].start = dev->parent->resource[regs[i]].start; /* XXX resource */ + } + + for (i = 0; i < PROMINTR_MAX; i++) + dev->irqs[i] = PCI_IRQ_NONE; + + if ((dev->irqs[0] = ebus_blacklist_irq(dev->prom_name)) != 0) { + dev->num_irqs = 1; + } else if ((len = prom_getproperty(node, "interrupts", + (char *)&irqs, sizeof(irqs))) == -1 || len == 0) { + dev->num_irqs = 0; + dev->irqs[0] = 0; + if (dev->parent->num_irqs != 0) { + dev->num_irqs = 1; + dev->irqs[0] = dev->parent->irqs[0]; +/* P3 */ /* printk("EBUS: dev %s irq %d from parent\n", dev->prom_name, dev->irqs[0]); */ + } + } else { + dev->num_irqs = len / sizeof(irqs[0]); + if (irqs[0] == 0 || irqs[0] >= 8) { + /* + * XXX Zero is a valid pin number... + * This works as long as Ebus is not wired to INTA#. + */ + printk("EBUS: %s got bad irq %d from PROM\n", + dev->prom_name, irqs[0]); + dev->num_irqs = 0; + dev->irqs[0] = 0; + } else { + dev->irqs[0] = pcic_pin_to_irq(irqs[0], dev->prom_name); + } + } +} + +void __init fill_ebus_device(int node, struct linux_ebus_device *dev) +{ + struct linux_prom_registers regs[PROMREG_MAX]; + struct linux_ebus_child *child; + int irqs[PROMINTR_MAX]; + char lbuf[128]; + int i, n, len; + unsigned long baseaddr; + + dev->prom_node = node; + prom_getstring(node, "name", lbuf, sizeof(lbuf)); + strcpy(dev->prom_name, lbuf); + + len = prom_getproperty(node, "reg", (void *)regs, sizeof(regs)); + if (len % sizeof(struct linux_prom_registers)) { + prom_printf("UGH: proplen for %s was %d, need multiple of %d\n", + dev->prom_name, len, + (int)sizeof(struct linux_prom_registers)); + panic(__FUNCTION__); + } + dev->num_addrs = len / sizeof(struct linux_prom_registers); + + for (i = 0; i < dev->num_addrs; i++) { + /* + * XXX Collect JE-1 PROM + * + * Example - JS-E with 3.11: + * /ebus + * regs + * 0x00000000, 0x0, 0x00000000, 0x0, 0x00000000, + * 0x82000010, 0x0, 0xf0000000, 0x0, 0x01000000, + * 0x82000014, 0x0, 0x38800000, 0x0, 0x00800000, + * ranges + * 0x00, 0x00000000, 0x02000010, 0x0, 0x0, 0x01000000, + * 0x01, 0x01000000, 0x02000014, 0x0, 0x0, 0x00800000, + * /ebus/8042 + * regs + * 0x00000001, 0x00300060, 0x00000008, + * 0x00000001, 0x00300060, 0x00000008, + */ + n = regs[i].which_io; + if (n >= 4) { + /* XXX This is copied from old JE-1 by Gleb. */ + n = (regs[i].which_io - 0x10) >> 2; + } else { + ; + } + +/* + * XXX Now as we have regions, why don't we make an on-demand allocation... + */ + dev->resource[i].start = 0; + if ((baseaddr = dev->bus->self->resource[n].start + + regs[i].phys_addr) != 0) { + /* dev->resource[i].name = dev->prom_name; */ + if ((baseaddr = (unsigned long) ioremap(baseaddr, + regs[i].reg_size)) == 0) { + panic("ebus: unable to remap dev %s", + dev->prom_name); + } + } + dev->resource[i].start = baseaddr; /* XXX Unaligned */ + } + + for (i = 0; i < PROMINTR_MAX; i++) + dev->irqs[i] = PCI_IRQ_NONE; + + if ((dev->irqs[0] = ebus_blacklist_irq(dev->prom_name)) != 0) { + dev->num_irqs = 1; + } else if ((len = prom_getproperty(node, "interrupts", + (char *)&irqs, sizeof(irqs))) == -1 || len == 0) { + dev->num_irqs = 0; + if ((dev->irqs[0] = dev->bus->self->irq) != 0) { + dev->num_irqs = 1; +/* P3 */ /* printk("EBUS: child %s irq %d from parent\n", dev->prom_name, dev->irqs[0]); */ + } + } else { + dev->num_irqs = 1; /* dev->num_irqs = len / sizeof(irqs[0]); */ + if (irqs[0] == 0 || irqs[0] >= 8) { + /* See above for the parent. XXX */ + printk("EBUS: %s got bad irq %d from PROM\n", + dev->prom_name, irqs[0]); + dev->num_irqs = 0; + dev->irqs[0] = 0; + } else { + dev->irqs[0] = pcic_pin_to_irq(irqs[0], dev->prom_name); + } + } + + if ((node = prom_getchild(node))) { + dev->children = (struct linux_ebus_child *) + ebus_alloc(sizeof(struct linux_ebus_child)); + + child = dev->children; + child->next = 0; + child->parent = dev; + child->bus = dev->bus; + fill_ebus_child(node, ®s[0], child); + + while ((node = prom_getsibling(node)) != 0) { + child->next = (struct linux_ebus_child *) + ebus_alloc(sizeof(struct linux_ebus_child)); + + child = child->next; + child->next = 0; + child->parent = dev; + child->bus = dev->bus; + fill_ebus_child(node, ®s[0], child); + } + } +} + +void __init ebus_init(void) +{ + struct linux_prom_pci_registers regs[PROMREG_MAX]; + struct linux_pbm_info *pbm; + struct linux_ebus_device *dev; + struct linux_ebus *ebus; + struct ebus_system_entry *sp; + struct pci_dev *pdev; + struct pcidev_cookie *cookie; + char lbuf[128]; + unsigned long addr, *base; + unsigned short pci_command; + int nd, len, ebusnd; + int reg, nreg; + int num_ebus = 0; + + prom_getstring(prom_root_node, "name", lbuf, sizeof(lbuf)); + for (sp = ebus_blacklist; sp->esname != NULL; sp++) { + if (strcmp(lbuf, sp->esname) == 0) { + ebus_blackp = sp->ipt; + break; + } + } + + pdev = pci_get_device(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_EBUS, 0); + if (!pdev) { + return; + } + cookie = pdev->sysdata; + ebusnd = cookie->prom_node; + + ebus_chain = ebus = (struct linux_ebus *) + ebus_alloc(sizeof(struct linux_ebus)); + ebus->next = 0; + + while (ebusnd) { + + prom_getstring(ebusnd, "name", lbuf, sizeof(lbuf)); + ebus->prom_node = ebusnd; + strcpy(ebus->prom_name, lbuf); + ebus->self = pdev; + ebus->parent = pbm = cookie->pbm; + + /* Enable BUS Master. */ + pci_read_config_word(pdev, PCI_COMMAND, &pci_command); + pci_command |= PCI_COMMAND_MASTER; + pci_write_config_word(pdev, PCI_COMMAND, pci_command); + + len = prom_getproperty(ebusnd, "reg", (void *)regs, + sizeof(regs)); + if (len == 0 || len == -1) { + prom_printf("%s: can't find reg property\n", + __FUNCTION__); + prom_halt(); + } + nreg = len / sizeof(struct linux_prom_pci_registers); + + base = &ebus->self->resource[0].start; + for (reg = 0; reg < nreg; reg++) { + if (!(regs[reg].which_io & 0x03000000)) + continue; + + addr = regs[reg].phys_lo; + *base++ = addr; + } + + nd = prom_getchild(ebusnd); + if (!nd) + goto next_ebus; + + ebus->devices = (struct linux_ebus_device *) + ebus_alloc(sizeof(struct linux_ebus_device)); + + dev = ebus->devices; + dev->next = 0; + dev->children = 0; + dev->bus = ebus; + fill_ebus_device(nd, dev); + + while ((nd = prom_getsibling(nd)) != 0) { + dev->next = (struct linux_ebus_device *) + ebus_alloc(sizeof(struct linux_ebus_device)); + + dev = dev->next; + dev->next = 0; + dev->children = 0; + dev->bus = ebus; + fill_ebus_device(nd, dev); + } + + next_ebus: + pdev = pci_get_device(PCI_VENDOR_ID_SUN, + PCI_DEVICE_ID_SUN_EBUS, pdev); + if (!pdev) + break; + + cookie = pdev->sysdata; + ebusnd = cookie->prom_node; + + ebus->next = (struct linux_ebus *) + ebus_alloc(sizeof(struct linux_ebus)); + ebus = ebus->next; + ebus->next = 0; + ++num_ebus; + } + if (pdev) + pci_dev_put(pdev); +} diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S new file mode 100644 index 00000000000..b448166f5da --- /dev/null +++ b/arch/sparc/kernel/entry.S @@ -0,0 +1,1956 @@ +/* $Id: entry.S,v 1.170 2001/11/13 00:57:05 davem Exp $ + * arch/sparc/kernel/entry.S: Sparc trap low-level entry points. + * + * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) + * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) + * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) + * Copyright (C) 1996-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) + * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au) + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SUN4 +#include +#else +#include +#endif +#include +#include +#include +#include +#include +#include + +#include + +#define curptr g6 + +#define NR_SYSCALLS 284 /* Each OS is different... */ + +/* These are just handy. */ +#define _SV save %sp, -STACKFRAME_SZ, %sp +#define _RS restore + +#define FLUSH_ALL_KERNEL_WINDOWS \ + _SV; _SV; _SV; _SV; _SV; _SV; _SV; \ + _RS; _RS; _RS; _RS; _RS; _RS; _RS; + +/* First, KGDB low level things. This is a rewrite + * of the routines found in the sparc-stub.c asm() statement + * from the gdb distribution. This is also dual-purpose + * as a software trap for userlevel programs. + */ + .data + .align 4 + +in_trap_handler: + .word 0 + + .text + .align 4 + +#if 0 /* kgdb is dropped from 2.5.33 */ +! This function is called when any SPARC trap (except window overflow or +! underflow) occurs. It makes sure that the invalid register window is still +! available before jumping into C code. It will also restore the world if you +! return from handle_exception. + + .globl trap_low +trap_low: + rd %wim, %l3 + SAVE_ALL + + sethi %hi(in_trap_handler), %l4 + ld [%lo(in_trap_handler) + %l4], %l5 + inc %l5 + st %l5, [%lo(in_trap_handler) + %l4] + + /* Make sure kgdb sees the same state we just saved. */ + LOAD_PT_GLOBALS(sp) + LOAD_PT_INS(sp) + ld [%sp + STACKFRAME_SZ + PT_Y], %l4 + ld [%sp + STACKFRAME_SZ + PT_WIM], %l3 + ld [%sp + STACKFRAME_SZ + PT_PSR], %l0 + ld [%sp + STACKFRAME_SZ + PT_PC], %l1 + ld [%sp + STACKFRAME_SZ + PT_NPC], %l2 + rd %tbr, %l5 /* Never changes... */ + + /* Make kgdb exception frame. */ + sub %sp,(16+1+6+1+72)*4,%sp ! Make room for input & locals + ! + hidden arg + arg spill + ! + doubleword alignment + ! + registers[72] local var + SAVE_KGDB_GLOBALS(sp) + SAVE_KGDB_INS(sp) + SAVE_KGDB_SREGS(sp, l4, l0, l3, l5, l1, l2) + + /* We are increasing PIL, so two writes. */ + or %l0, PSR_PIL, %l0 + wr %l0, 0, %psr + WRITE_PAUSE + wr %l0, PSR_ET, %psr + WRITE_PAUSE + + call handle_exception + add %sp, STACKFRAME_SZ, %o0 ! Pass address of registers + + /* Load new kgdb register set. */ + LOAD_KGDB_GLOBALS(sp) + LOAD_KGDB_INS(sp) + LOAD_KGDB_SREGS(sp, l4, l0, l3, l5, l1, l2) + wr %l4, 0x0, %y + + sethi %hi(in_trap_handler), %l4 + ld [%lo(in_trap_handler) + %l4], %l5 + dec %l5 + st %l5, [%lo(in_trap_handler) + %l4] + + add %sp,(16+1+6+1+72)*4,%sp ! Undo the kgdb trap frame. + + /* Now take what kgdb did and place it into the pt_regs + * frame which SparcLinux RESTORE_ALL understands., + */ + STORE_PT_INS(sp) + STORE_PT_GLOBALS(sp) + STORE_PT_YREG(sp, g2) + STORE_PT_PRIV(sp, l0, l1, l2) + + RESTORE_ALL +#endif + +#ifdef CONFIG_BLK_DEV_FD + .text + .align 4 + .globl floppy_hardint +floppy_hardint: + /* + * This code cannot touch registers %l0 %l1 and %l2 + * because SAVE_ALL depends on their values. It depends + * on %l3 also, but we regenerate it before a call. + * Other registers are: + * %l3 -- base address of fdc registers + * %l4 -- pdma_vaddr + * %l5 -- scratch for ld/st address + * %l6 -- pdma_size + * %l7 -- scratch [floppy byte, ld/st address, aux. data] + */ + + /* Do we have work to do? */ + sethi %hi(doing_pdma), %l7 + ld [%l7 + %lo(doing_pdma)], %l7 + cmp %l7, 0 + be floppy_dosoftint + nop + + /* Load fdc register base */ + sethi %hi(fdc_status), %l3 + ld [%l3 + %lo(fdc_status)], %l3 + + /* Setup register addresses */ + sethi %hi(pdma_vaddr), %l5 ! transfer buffer + ld [%l5 + %lo(pdma_vaddr)], %l4 + sethi %hi(pdma_size), %l5 ! bytes to go + ld [%l5 + %lo(pdma_size)], %l6 +next_byte: + ldub [%l3], %l7 + + andcc %l7, 0x80, %g0 ! Does fifo still have data + bz floppy_fifo_emptied ! fifo has been emptied... + andcc %l7, 0x20, %g0 ! in non-dma mode still? + bz floppy_overrun ! nope, overrun + andcc %l7, 0x40, %g0 ! 0=write 1=read + bz floppy_write + sub %l6, 0x1, %l6 + + /* Ok, actually read this byte */ + ldub [%l3 + 1], %l7 + orcc %g0, %l6, %g0 + stb %l7, [%l4] + bne next_byte + add %l4, 0x1, %l4 + + b floppy_tdone + nop + +floppy_write: + /* Ok, actually write this byte */ + ldub [%l4], %l7 + orcc %g0, %l6, %g0 + stb %l7, [%l3 + 1] + bne next_byte + add %l4, 0x1, %l4 + + /* fall through... */ +floppy_tdone: + sethi %hi(pdma_vaddr), %l5 + st %l4, [%l5 + %lo(pdma_vaddr)] + sethi %hi(pdma_size), %l5 + st %l6, [%l5 + %lo(pdma_size)] + /* Flip terminal count pin */ + set auxio_register, %l7 + ld [%l7], %l7 + + set sparc_cpu_model, %l5 + ld [%l5], %l5 + subcc %l5, 1, %g0 /* enum { sun4c = 1 }; */ + be 1f + ldub [%l7], %l5 + + or %l5, 0xc2, %l5 + stb %l5, [%l7] + andn %l5, 0x02, %l5 + b 2f + nop + +1: + or %l5, 0xf4, %l5 + stb %l5, [%l7] + andn %l5, 0x04, %l5 + +2: + /* Kill some time so the bits set */ + WRITE_PAUSE + WRITE_PAUSE + + stb %l5, [%l7] + + /* Prevent recursion */ + sethi %hi(doing_pdma), %l7 + b floppy_dosoftint + st %g0, [%l7 + %lo(doing_pdma)] + + /* We emptied the FIFO, but we haven't read everything + * as of yet. Store the current transfer address and + * bytes left to read so we can continue when the next + * fast IRQ comes in. + */ +floppy_fifo_emptied: + sethi %hi(pdma_vaddr), %l5 + st %l4, [%l5 + %lo(pdma_vaddr)] + sethi %hi(pdma_size), %l7 + st %l6, [%l7 + %lo(pdma_size)] + + /* Restore condition codes */ + wr %l0, 0x0, %psr + WRITE_PAUSE + + jmp %l1 + rett %l2 + +floppy_overrun: + sethi %hi(pdma_vaddr), %l5 + st %l4, [%l5 + %lo(pdma_vaddr)] + sethi %hi(pdma_size), %l5 + st %l6, [%l5 + %lo(pdma_size)] + /* Prevent recursion */ + sethi %hi(doing_pdma), %l7 + st %g0, [%l7 + %lo(doing_pdma)] + + /* fall through... */ +floppy_dosoftint: + rd %wim, %l3 + SAVE_ALL + + /* Set all IRQs off. */ + or %l0, PSR_PIL, %l4 + wr %l4, 0x0, %psr + WRITE_PAUSE + wr %l4, PSR_ET, %psr + WRITE_PAUSE + + mov 11, %o0 ! floppy irq level (unused anyway) + mov %g0, %o1 ! devid is not used in fast interrupts + call sparc_floppy_irq + add %sp, STACKFRAME_SZ, %o2 ! struct pt_regs *regs + + RESTORE_ALL + +#endif /* (CONFIG_BLK_DEV_FD) */ + + /* Bad trap handler */ + .globl bad_trap_handler +bad_trap_handler: + SAVE_ALL + + wr %l0, PSR_ET, %psr + WRITE_PAUSE + + add %sp, STACKFRAME_SZ, %o0 ! pt_regs + call do_hw_interrupt + mov %l7, %o1 ! trap number + + RESTORE_ALL + +/* For now all IRQ's not registered get sent here. handler_irq() will + * see if a routine is registered to handle this interrupt and if not + * it will say so on the console. + */ + + .align 4 + .globl real_irq_entry, patch_handler_irq +real_irq_entry: + SAVE_ALL + +#ifdef CONFIG_SMP + .globl patchme_maybe_smp_msg + + cmp %l7, 12 +patchme_maybe_smp_msg: + bgu maybe_smp4m_msg + nop +#endif + +real_irq_continue: + or %l0, PSR_PIL, %g2 + wr %g2, 0x0, %psr + WRITE_PAUSE + wr %g2, PSR_ET, %psr + WRITE_PAUSE + mov %l7, %o0 ! irq level +patch_handler_irq: + call handler_irq + add %sp, STACKFRAME_SZ, %o1 ! pt_regs ptr + or %l0, PSR_PIL, %g2 ! restore PIL after handler_irq + wr %g2, PSR_ET, %psr ! keep ET up + WRITE_PAUSE + + RESTORE_ALL + +#ifdef CONFIG_SMP + /* SMP per-cpu ticker interrupts are handled specially. */ +smp4m_ticker: + bne real_irq_continue+4 + or %l0, PSR_PIL, %g2 + wr %g2, 0x0, %psr + WRITE_PAUSE + wr %g2, PSR_ET, %psr + WRITE_PAUSE + call smp4m_percpu_timer_interrupt + add %sp, STACKFRAME_SZ, %o0 + wr %l0, PSR_ET, %psr + WRITE_PAUSE + RESTORE_ALL + + /* Here is where we check for possible SMP IPI passed to us + * on some level other than 15 which is the NMI and only used + * for cross calls. That has a separate entry point below. + */ +maybe_smp4m_msg: + GET_PROCESSOR4M_ID(o3) + set sun4m_interrupts, %l5 + ld [%l5], %o5 + sethi %hi(0x40000000), %o2 + sll %o3, 12, %o3 + ld [%o5 + %o3], %o1 + andcc %o1, %o2, %g0 + be,a smp4m_ticker + cmp %l7, 14 + st %o2, [%o5 + 0x4] + WRITE_PAUSE + ld [%o5], %g0 + WRITE_PAUSE + or %l0, PSR_PIL, %l4 + wr %l4, 0x0, %psr + WRITE_PAUSE + wr %l4, PSR_ET, %psr + WRITE_PAUSE + call smp_reschedule_irq + nop + + RESTORE_ALL + + .align 4 + .globl linux_trap_ipi15_sun4m +linux_trap_ipi15_sun4m: + SAVE_ALL + sethi %hi(0x80000000), %o2 + GET_PROCESSOR4M_ID(o0) + set sun4m_interrupts, %l5 + ld [%l5], %o5 + sll %o0, 12, %o0 + add %o5, %o0, %o5 + ld [%o5], %o3 + andcc %o3, %o2, %g0 + be 1f ! Must be an NMI async memory error + st %o2, [%o5 + 4] + WRITE_PAUSE + ld [%o5], %g0 + WRITE_PAUSE + or %l0, PSR_PIL, %l4 + wr %l4, 0x0, %psr + WRITE_PAUSE + wr %l4, PSR_ET, %psr + WRITE_PAUSE + call smp4m_cross_call_irq + nop + b ret_trap_lockless_ipi + clr %l6 +1: + /* NMI async memory error handling. */ + sethi %hi(0x80000000), %l4 + sethi %hi(0x4000), %o3 + sub %o5, %o0, %o5 + add %o5, %o3, %l5 + st %l4, [%l5 + 0xc] + WRITE_PAUSE + ld [%l5], %g0 + WRITE_PAUSE + or %l0, PSR_PIL, %l4 + wr %l4, 0x0, %psr + WRITE_PAUSE + wr %l4, PSR_ET, %psr + WRITE_PAUSE + call sun4m_nmi + nop + st %l4, [%l5 + 0x8] + WRITE_PAUSE + ld [%l5], %g0 + WRITE_PAUSE + RESTORE_ALL + + .globl smp4d_ticker + /* SMP per-cpu ticker interrupts are handled specially. */ +smp4d_ticker: + SAVE_ALL + or %l0, PSR_PIL, %g2 + sethi %hi(CC_ICLR), %o0 + sethi %hi(1 << 14), %o1 + or %o0, %lo(CC_ICLR), %o0 + stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 14 in MXCC's ICLR */ + wr %g2, 0x0, %psr + WRITE_PAUSE + wr %g2, PSR_ET, %psr + WRITE_PAUSE + call smp4d_percpu_timer_interrupt + add %sp, STACKFRAME_SZ, %o0 + wr %l0, PSR_ET, %psr + WRITE_PAUSE + RESTORE_ALL + + .align 4 + .globl linux_trap_ipi15_sun4d +linux_trap_ipi15_sun4d: + SAVE_ALL + sethi %hi(CC_BASE), %o4 + sethi %hi(MXCC_ERR_ME|MXCC_ERR_PEW|MXCC_ERR_ASE|MXCC_ERR_PEE), %o2 + or %o4, (CC_EREG - CC_BASE), %o0 + ldda [%o0] ASI_M_MXCC, %o0 + andcc %o0, %o2, %g0 + bne 1f + sethi %hi(BB_STAT2), %o2 + lduba [%o2] ASI_M_CTL, %o2 + andcc %o2, BB_STAT2_MASK, %g0 + bne 2f + or %o4, (CC_ICLR - CC_BASE), %o0 + sethi %hi(1 << 15), %o1 + stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 15 in MXCC's ICLR */ + or %l0, PSR_PIL, %l4 + wr %l4, 0x0, %psr + WRITE_PAUSE + wr %l4, PSR_ET, %psr + WRITE_PAUSE + call smp4d_cross_call_irq + nop + b ret_trap_lockless_ipi + clr %l6 + +1: /* MXCC error */ +2: /* BB error */ + /* Disable PIL 15 */ + set CC_IMSK, %l4 + lduha [%l4] ASI_M_MXCC, %l5 + sethi %hi(1 << 15), %l7 + or %l5, %l7, %l5 + stha %l5, [%l4] ASI_M_MXCC + /* FIXME */ +1: b,a 1b + +#endif /* CONFIG_SMP */ + + /* This routine handles illegal instructions and privileged + * instruction attempts from user code. + */ + .align 4 + .globl bad_instruction +bad_instruction: + sethi %hi(0xc1f80000), %l4 + ld [%l1], %l5 + sethi %hi(0x81d80000), %l7 + and %l5, %l4, %l5 + cmp %l5, %l7 + be 1f + SAVE_ALL + + wr %l0, PSR_ET, %psr ! re-enable traps + WRITE_PAUSE + + add %sp, STACKFRAME_SZ, %o0 + mov %l1, %o1 + mov %l2, %o2 + call do_illegal_instruction + mov %l0, %o3 + + RESTORE_ALL + +1: /* unimplemented flush - just skip */ + jmpl %l2, %g0 + rett %l2 + 4 + + .align 4 + .globl priv_instruction +priv_instruction: + SAVE_ALL + + wr %l0, PSR_ET, %psr + WRITE_PAUSE + + add %sp, STACKFRAME_SZ, %o0 + mov %l1, %o1 + mov %l2, %o2 + call do_priv_instruction + mov %l0, %o3 + + RESTORE_ALL + + /* This routine handles unaligned data accesses. */ + .align 4 + .globl mna_handler +mna_handler: + andcc %l0, PSR_PS, %g0 + be mna_fromuser + nop + + SAVE_ALL + + wr %l0, PSR_ET, %psr + WRITE_PAUSE + + ld [%l1], %o1 + call kernel_unaligned_trap + add %sp, STACKFRAME_SZ, %o0 + + RESTORE_ALL + +mna_fromuser: + SAVE_ALL + + wr %l0, PSR_ET, %psr ! re-enable traps + WRITE_PAUSE + + ld [%l1], %o1 + call user_unaligned_trap + add %sp, STACKFRAME_SZ, %o0 + + RESTORE_ALL + + /* This routine handles floating point disabled traps. */ + .align 4 + .globl fpd_trap_handler +fpd_trap_handler: + SAVE_ALL + + wr %l0, PSR_ET, %psr ! re-enable traps + WRITE_PAUSE + + add %sp, STACKFRAME_SZ, %o0 + mov %l1, %o1 + mov %l2, %o2 + call do_fpd_trap + mov %l0, %o3 + + RESTORE_ALL + + /* This routine handles Floating Point Exceptions. */ + .align 4 + .globl fpe_trap_handler +fpe_trap_handler: + set fpsave_magic, %l5 + cmp %l1, %l5 + be 1f + sethi %hi(fpsave), %l5 + or %l5, %lo(fpsave), %l5 + cmp %l1, %l5 + bne 2f + sethi %hi(fpsave_catch2), %l5 + or %l5, %lo(fpsave_catch2), %l5 + wr %l0, 0x0, %psr + WRITE_PAUSE + jmp %l5 + rett %l5 + 4 +1: + sethi %hi(fpsave_catch), %l5 + or %l5, %lo(fpsave_catch), %l5 + wr %l0, 0x0, %psr + WRITE_PAUSE + jmp %l5 + rett %l5 + 4 + +2: + SAVE_ALL + + wr %l0, PSR_ET, %psr ! re-enable traps + WRITE_PAUSE + + add %sp, STACKFRAME_SZ, %o0 + mov %l1, %o1 + mov %l2, %o2 + call do_fpe_trap + mov %l0, %o3 + + RESTORE_ALL + + /* This routine handles Tag Overflow Exceptions. */ + .align 4 + .globl do_tag_overflow +do_tag_overflow: + SAVE_ALL + + wr %l0, PSR_ET, %psr ! re-enable traps + WRITE_PAUSE + + add %sp, STACKFRAME_SZ, %o0 + mov %l1, %o1 + mov %l2, %o2 + call handle_tag_overflow + mov %l0, %o3 + + RESTORE_ALL + + /* This routine handles Watchpoint Exceptions. */ + .align 4 + .globl do_watchpoint +do_watchpoint: + SAVE_ALL + + wr %l0, PSR_ET, %psr ! re-enable traps + WRITE_PAUSE + + add %sp, STACKFRAME_SZ, %o0 + mov %l1, %o1 + mov %l2, %o2 + call handle_watchpoint + mov %l0, %o3 + + RESTORE_ALL + + /* This routine handles Register Access Exceptions. */ + .align 4 + .globl do_reg_access +do_reg_access: + SAVE_ALL + + wr %l0, PSR_ET, %psr ! re-enable traps + WRITE_PAUSE + + add %sp, STACKFRAME_SZ, %o0 + mov %l1, %o1 + mov %l2, %o2 + call handle_reg_access + mov %l0, %o3 + + RESTORE_ALL + + /* This routine handles Co-Processor Disabled Exceptions. */ + .align 4 + .globl do_cp_disabled +do_cp_disabled: + SAVE_ALL + + wr %l0, PSR_ET, %psr ! re-enable traps + WRITE_PAUSE + + add %sp, STACKFRAME_SZ, %o0 + mov %l1, %o1 + mov %l2, %o2 + call handle_cp_disabled + mov %l0, %o3 + + RESTORE_ALL + + /* This routine handles Co-Processor Exceptions. */ + .align 4 + .globl do_cp_exception +do_cp_exception: + SAVE_ALL + + wr %l0, PSR_ET, %psr ! re-enable traps + WRITE_PAUSE + + add %sp, STACKFRAME_SZ, %o0 + mov %l1, %o1 + mov %l2, %o2 + call handle_cp_exception + mov %l0, %o3 + + RESTORE_ALL + + /* This routine handles Hardware Divide By Zero Exceptions. */ + .align 4 + .globl do_hw_divzero +do_hw_divzero: + SAVE_ALL + + wr %l0, PSR_ET, %psr ! re-enable traps + WRITE_PAUSE + + add %sp, STACKFRAME_SZ, %o0 + mov %l1, %o1 + mov %l2, %o2 + call handle_hw_divzero + mov %l0, %o3 + + RESTORE_ALL + + .align 4 + .globl do_flush_windows +do_flush_windows: + SAVE_ALL + + wr %l0, PSR_ET, %psr + WRITE_PAUSE + + andcc %l0, PSR_PS, %g0 + bne dfw_kernel + nop + + call flush_user_windows + nop + + /* Advance over the trap instruction. */ + ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 + add %l1, 0x4, %l2 + st %l1, [%sp + STACKFRAME_SZ + PT_PC] + st %l2, [%sp + STACKFRAME_SZ + PT_NPC] + + RESTORE_ALL + + .globl flush_patch_one + + /* We get these for debugging routines using __builtin_return_address() */ +dfw_kernel: +flush_patch_one: + FLUSH_ALL_KERNEL_WINDOWS + + /* Advance over the trap instruction. */ + ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 + add %l1, 0x4, %l2 + st %l1, [%sp + STACKFRAME_SZ + PT_PC] + st %l2, [%sp + STACKFRAME_SZ + PT_NPC] + + RESTORE_ALL + + /* The getcc software trap. The user wants the condition codes from + * the %psr in register %g1. + */ + + .align 4 + .globl getcc_trap_handler +getcc_trap_handler: + srl %l0, 20, %g1 ! give user + and %g1, 0xf, %g1 ! only ICC bits in %psr + jmp %l2 ! advance over trap instruction + rett %l2 + 0x4 ! like this... + + /* The setcc software trap. The user has condition codes in %g1 + * that it would like placed in the %psr. Be careful not to flip + * any unintentional bits! + */ + + .align 4 + .globl setcc_trap_handler +setcc_trap_handler: + sll %g1, 0x14, %l4 + set PSR_ICC, %l5 + andn %l0, %l5, %l0 ! clear ICC bits in %psr + and %l4, %l5, %l4 ! clear non-ICC bits in user value + or %l4, %l0, %l4 ! or them in... mix mix mix + + wr %l4, 0x0, %psr ! set new %psr + WRITE_PAUSE ! TI scumbags... + + jmp %l2 ! advance over trap instruction + rett %l2 + 0x4 ! like this... + + .align 4 + .globl linux_trap_nmi_sun4c +linux_trap_nmi_sun4c: + SAVE_ALL + + /* Ugh, we need to clear the IRQ line. This is now + * a very sun4c specific trap handler... + */ + sethi %hi(interrupt_enable), %l5 + ld [%l5 + %lo(interrupt_enable)], %l5 + ldub [%l5], %l6 + andn %l6, INTS_ENAB, %l6 + stb %l6, [%l5] + + /* Now it is safe to re-enable traps without recursion. */ + or %l0, PSR_PIL, %l0 + wr %l0, PSR_ET, %psr + WRITE_PAUSE + + /* Now call the c-code with the pt_regs frame ptr and the + * memory error registers as arguments. The ordering chosen + * here is due to unlatching semantics. + */ + sethi %hi(AC_SYNC_ERR), %o0 + add %o0, 0x4, %o0 + lda [%o0] ASI_CONTROL, %o2 ! sync vaddr + sub %o0, 0x4, %o0 + lda [%o0] ASI_CONTROL, %o1 ! sync error + add %o0, 0xc, %o0 + lda [%o0] ASI_CONTROL, %o4 ! async vaddr + sub %o0, 0x4, %o0 + lda [%o0] ASI_CONTROL, %o3 ! async error + call sparc_lvl15_nmi + add %sp, STACKFRAME_SZ, %o0 + + RESTORE_ALL + + .align 4 + .globl invalid_segment_patch1_ff + .globl invalid_segment_patch2_ff +invalid_segment_patch1_ff: cmp %l4, 0xff +invalid_segment_patch2_ff: mov 0xff, %l3 + + .align 4 + .globl invalid_segment_patch1_1ff + .globl invalid_segment_patch2_1ff +invalid_segment_patch1_1ff: cmp %l4, 0x1ff +invalid_segment_patch2_1ff: mov 0x1ff, %l3 + + .align 4 + .globl num_context_patch1_16, num_context_patch2_16 +num_context_patch1_16: mov 0x10, %l7 +num_context_patch2_16: mov 0x10, %l7 + + .align 4 + .globl vac_linesize_patch_32 +vac_linesize_patch_32: subcc %l7, 32, %l7 + + .align 4 + .globl vac_hwflush_patch1_on, vac_hwflush_patch2_on + +/* + * Ugly, but we cant use hardware flushing on the sun4 and we'd require + * two instructions (Anton) + */ +#ifdef CONFIG_SUN4 +vac_hwflush_patch1_on: nop +#else +vac_hwflush_patch1_on: addcc %l7, -PAGE_SIZE, %l7 +#endif + +vac_hwflush_patch2_on: sta %g0, [%l3 + %l7] ASI_HWFLUSHSEG + + .globl invalid_segment_patch1, invalid_segment_patch2 + .globl num_context_patch1 + .globl vac_linesize_patch, vac_hwflush_patch1 + .globl vac_hwflush_patch2 + + .align 4 + .globl sun4c_fault + +! %l0 = %psr +! %l1 = %pc +! %l2 = %npc +! %l3 = %wim +! %l7 = 1 for textfault +! We want error in %l5, vaddr in %l6 +sun4c_fault: +#ifdef CONFIG_SUN4 + sethi %hi(sun4c_memerr_reg), %l4 + ld [%l4+%lo(sun4c_memerr_reg)], %l4 ! memerr ctrl reg addr + ld [%l4], %l6 ! memerr ctrl reg + ld [%l4 + 4], %l5 ! memerr vaddr reg + andcc %l6, 0x80, %g0 ! check for error type + st %g0, [%l4 + 4] ! clear the error + be 0f ! normal error + sethi %hi(AC_BUS_ERROR), %l4 ! bus err reg addr + + call prom_halt ! something weird happened + ! what exactly did happen? + ! what should we do here? + +0: or %l4, %lo(AC_BUS_ERROR), %l4 ! bus err reg addr + lduba [%l4] ASI_CONTROL, %l6 ! bus err reg + + cmp %l7, 1 ! text fault? + be 1f ! yes + nop + + ld [%l1], %l4 ! load instruction that caused fault + srl %l4, 21, %l4 + andcc %l4, 1, %g0 ! store instruction? + + be 1f ! no + sethi %hi(SUN4C_SYNC_BADWRITE), %l4 ! yep + ! %lo(SUN4C_SYNC_BADWRITE) = 0 + or %l4, %l6, %l6 ! set write bit to emulate sun4c +1: +#else + sethi %hi(AC_SYNC_ERR), %l4 + add %l4, 0x4, %l6 ! AC_SYNC_VA in %l6 + lda [%l6] ASI_CONTROL, %l5 ! Address + lda [%l4] ASI_CONTROL, %l6 ! Error, retained for a bit +#endif + + andn %l5, 0xfff, %l5 ! Encode all info into l7 + srl %l6, 14, %l4 + + and %l4, 2, %l4 + or %l5, %l4, %l4 + + or %l4, %l7, %l7 ! l7 = [addr,write,txtfault] + + andcc %l0, PSR_PS, %g0 + be sun4c_fault_fromuser + andcc %l7, 1, %g0 ! Text fault? + + be 1f + sethi %hi(KERNBASE), %l4 + + mov %l1, %l5 ! PC + +1: + cmp %l5, %l4 + blu sun4c_fault_fromuser + sethi %hi(~((1 << SUN4C_REAL_PGDIR_SHIFT) - 1)), %l4 + + /* If the kernel references a bum kernel pointer, or a pte which + * points to a non existant page in ram, we will run this code + * _forever_ and lock up the machine!!!!! So we must check for + * this condition, the AC_SYNC_ERR bits are what we must examine. + * Also a parity error would make this happen as well. So we just + * check that we are in fact servicing a tlb miss and not some + * other type of fault for the kernel. + */ + andcc %l6, 0x80, %g0 + be sun4c_fault_fromuser + and %l5, %l4, %l5 + + /* Test for NULL pte_t * in vmalloc area. */ + sethi %hi(VMALLOC_START), %l4 + cmp %l5, %l4 + blu,a invalid_segment_patch1 + lduXa [%l5] ASI_SEGMAP, %l4 + + sethi %hi(swapper_pg_dir), %l4 + srl %l5, SUN4C_PGDIR_SHIFT, %l6 + or %l4, %lo(swapper_pg_dir), %l4 + sll %l6, 2, %l6 + ld [%l4 + %l6], %l4 +#ifdef CONFIG_SUN4 + sethi %hi(PAGE_MASK), %l6 + andcc %l4, %l6, %g0 +#else + andcc %l4, PAGE_MASK, %g0 +#endif + be sun4c_fault_fromuser + lduXa [%l5] ASI_SEGMAP, %l4 + +invalid_segment_patch1: + cmp %l4, 0x7f + bne 1f + sethi %hi(sun4c_kfree_ring), %l4 + or %l4, %lo(sun4c_kfree_ring), %l4 + ld [%l4 + 0x18], %l3 + deccc %l3 ! do we have a free entry? + bcs,a 2f ! no, unmap one. + sethi %hi(sun4c_kernel_ring), %l4 + + st %l3, [%l4 + 0x18] ! sun4c_kfree_ring.num_entries-- + + ld [%l4 + 0x00], %l6 ! entry = sun4c_kfree_ring.ringhd.next + st %l5, [%l6 + 0x08] ! entry->vaddr = address + + ld [%l6 + 0x00], %l3 ! next = entry->next + ld [%l6 + 0x04], %l7 ! entry->prev + + st %l7, [%l3 + 0x04] ! next->prev = entry->prev + st %l3, [%l7 + 0x00] ! entry->prev->next = next + + sethi %hi(sun4c_kernel_ring), %l4 + or %l4, %lo(sun4c_kernel_ring), %l4 + ! head = &sun4c_kernel_ring.ringhd + + ld [%l4 + 0x00], %l7 ! head->next + + st %l4, [%l6 + 0x04] ! entry->prev = head + st %l7, [%l6 + 0x00] ! entry->next = head->next + st %l6, [%l7 + 0x04] ! head->next->prev = entry + + st %l6, [%l4 + 0x00] ! head->next = entry + + ld [%l4 + 0x18], %l3 + inc %l3 ! sun4c_kernel_ring.num_entries++ + st %l3, [%l4 + 0x18] + b 4f + ld [%l6 + 0x08], %l5 + +2: + or %l4, %lo(sun4c_kernel_ring), %l4 + ! head = &sun4c_kernel_ring.ringhd + + ld [%l4 + 0x04], %l6 ! entry = head->prev + + ld [%l6 + 0x08], %l3 ! tmp = entry->vaddr + + ! Flush segment from the cache. +#ifdef CONFIG_SUN4 + sethi %hi((128 * 1024)), %l7 +#else + sethi %hi((64 * 1024)), %l7 +#endif +9: +vac_hwflush_patch1: +vac_linesize_patch: + subcc %l7, 16, %l7 + bne 9b +vac_hwflush_patch2: + sta %g0, [%l3 + %l7] ASI_FLUSHSEG + + st %l5, [%l6 + 0x08] ! entry->vaddr = address + + ld [%l6 + 0x00], %l5 ! next = entry->next + ld [%l6 + 0x04], %l7 ! entry->prev + + st %l7, [%l5 + 0x04] ! next->prev = entry->prev + st %l5, [%l7 + 0x00] ! entry->prev->next = next + st %l4, [%l6 + 0x04] ! entry->prev = head + + ld [%l4 + 0x00], %l7 ! head->next + + st %l7, [%l6 + 0x00] ! entry->next = head->next + st %l6, [%l7 + 0x04] ! head->next->prev = entry + st %l6, [%l4 + 0x00] ! head->next = entry + + mov %l3, %l5 ! address = tmp + +4: +num_context_patch1: + mov 0x08, %l7 + + ld [%l6 + 0x08], %l4 + ldub [%l6 + 0x0c], %l3 + or %l4, %l3, %l4 ! encode new vaddr/pseg into l4 + + sethi %hi(AC_CONTEXT), %l3 + lduba [%l3] ASI_CONTROL, %l6 + + /* Invalidate old mapping, instantiate new mapping, + * for each context. Registers l6/l7 are live across + * this loop. + */ +3: deccc %l7 + sethi %hi(AC_CONTEXT), %l3 + stba %l7, [%l3] ASI_CONTROL +invalid_segment_patch2: + mov 0x7f, %l3 + stXa %l3, [%l5] ASI_SEGMAP + andn %l4, 0x1ff, %l3 + bne 3b + stXa %l4, [%l3] ASI_SEGMAP + + sethi %hi(AC_CONTEXT), %l3 + stba %l6, [%l3] ASI_CONTROL + + andn %l4, 0x1ff, %l5 + +1: + sethi %hi(VMALLOC_START), %l4 + cmp %l5, %l4 + + bgeu 1f + mov 1 << (SUN4C_REAL_PGDIR_SHIFT - PAGE_SHIFT), %l7 + + sethi %hi(KERNBASE), %l6 + + sub %l5, %l6, %l4 + srl %l4, PAGE_SHIFT, %l4 + sethi %hi((SUN4C_PAGE_KERNEL & 0xf4000000)), %l3 + or %l3, %l4, %l3 + + sethi %hi(PAGE_SIZE), %l4 + +2: + sta %l3, [%l5] ASI_PTE + deccc %l7 + inc %l3 + bne 2b + add %l5, %l4, %l5 + + b 7f + sethi %hi(sun4c_kernel_faults), %l4 + +1: + srl %l5, SUN4C_PGDIR_SHIFT, %l3 + sethi %hi(swapper_pg_dir), %l4 + or %l4, %lo(swapper_pg_dir), %l4 + sll %l3, 2, %l3 + ld [%l4 + %l3], %l4 +#ifndef CONFIG_SUN4 + and %l4, PAGE_MASK, %l4 +#else + sethi %hi(PAGE_MASK), %l6 + and %l4, %l6, %l4 +#endif + + srl %l5, (PAGE_SHIFT - 2), %l6 + and %l6, ((SUN4C_PTRS_PER_PTE - 1) << 2), %l6 + add %l6, %l4, %l6 + + sethi %hi(PAGE_SIZE), %l4 + +2: + ld [%l6], %l3 + deccc %l7 + sta %l3, [%l5] ASI_PTE + add %l6, 0x4, %l6 + bne 2b + add %l5, %l4, %l5 + + sethi %hi(sun4c_kernel_faults), %l4 +7: + ld [%l4 + %lo(sun4c_kernel_faults)], %l3 + inc %l3 + st %l3, [%l4 + %lo(sun4c_kernel_faults)] + + /* Restore condition codes */ + wr %l0, 0x0, %psr + WRITE_PAUSE + jmp %l1 + rett %l2 + +sun4c_fault_fromuser: + SAVE_ALL + nop + + mov %l7, %o1 ! Decode the info from %l7 + mov %l7, %o2 + and %o1, 1, %o1 ! arg2 = text_faultp + mov %l7, %o3 + and %o2, 2, %o2 ! arg3 = writep + andn %o3, 0xfff, %o3 ! arg4 = faulting address + + wr %l0, PSR_ET, %psr + WRITE_PAUSE + + call do_sun4c_fault + add %sp, STACKFRAME_SZ, %o0 ! arg1 = pt_regs ptr + + RESTORE_ALL + + .align 4 + .globl srmmu_fault +srmmu_fault: + mov 0x400, %l5 + mov 0x300, %l4 + + lda [%l5] ASI_M_MMUREGS, %l6 ! read sfar first + lda [%l4] ASI_M_MMUREGS, %l5 ! read sfsr last + + andn %l6, 0xfff, %l6 + srl %l5, 6, %l5 ! and encode all info into l7 + + and %l5, 2, %l5 + or %l5, %l6, %l6 + + or %l6, %l7, %l7 ! l7 = [addr,write,txtfault] + + SAVE_ALL + + mov %l7, %o1 + mov %l7, %o2 + and %o1, 1, %o1 ! arg2 = text_faultp + mov %l7, %o3 + and %o2, 2, %o2 ! arg3 = writep + andn %o3, 0xfff, %o3 ! arg4 = faulting address + + wr %l0, PSR_ET, %psr + WRITE_PAUSE + + call do_sparc_fault + add %sp, STACKFRAME_SZ, %o0 ! arg1 = pt_regs ptr + + RESTORE_ALL + +#ifdef CONFIG_SUNOS_EMUL + /* SunOS uses syscall zero as the 'indirect syscall' it looks + * like indir_syscall(scall_num, arg0, arg1, arg2...); etc. + * This is complete brain damage. + */ + .globl sunos_indir +sunos_indir: + mov %o7, %l4 + cmp %o0, NR_SYSCALLS + blu,a 1f + sll %o0, 0x2, %o0 + + sethi %hi(sunos_nosys), %l6 + b 2f + or %l6, %lo(sunos_nosys), %l6 + +1: + set sunos_sys_table, %l7 + ld [%l7 + %o0], %l6 + +2: + mov %o1, %o0 + mov %o2, %o1 + mov %o3, %o2 + mov %o4, %o3 + mov %o5, %o4 + call %l6 + mov %l4, %o7 +#endif + + .align 4 + .globl sys_nis_syscall +sys_nis_syscall: + mov %o7, %l5 + add %sp, STACKFRAME_SZ, %o0 ! pt_regs *regs arg + call c_sys_nis_syscall + mov %l5, %o7 + + .align 4 + .globl sys_ptrace +sys_ptrace: + call do_ptrace + add %sp, STACKFRAME_SZ, %o0 + + ld [%curptr + TI_FLAGS], %l5 + andcc %l5, _TIF_SYSCALL_TRACE, %g0 + be 1f + nop + + call syscall_trace + nop + +1: + RESTORE_ALL + + .align 4 + .globl sys_execve +sys_execve: + mov %o7, %l5 + add %sp, STACKFRAME_SZ, %o0 ! pt_regs *regs arg + call sparc_execve + mov %l5, %o7 + + .align 4 + .globl sys_pipe +sys_pipe: + mov %o7, %l5 + add %sp, STACKFRAME_SZ, %o0 ! pt_regs *regs arg + call sparc_pipe + mov %l5, %o7 + + .align 4 + .globl sys_sigaltstack +sys_sigaltstack: + mov %o7, %l5 + mov %fp, %o2 + call do_sigaltstack + mov %l5, %o7 + + .align 4 + .globl sys_sigstack +sys_sigstack: + mov %o7, %l5 + mov %fp, %o2 + call do_sys_sigstack + mov %l5, %o7 + + .align 4 + .globl sys_sigpause +sys_sigpause: + /* Note: %o0 already has correct value... */ + call do_sigpause + add %sp, STACKFRAME_SZ, %o1 + + ld [%curptr + TI_FLAGS], %l5 + andcc %l5, _TIF_SYSCALL_TRACE, %g0 + be 1f + nop + + call syscall_trace + nop + +1: + /* We are returning to a signal handler. */ + RESTORE_ALL + + .align 4 + .globl sys_sigsuspend +sys_sigsuspend: + call do_sigsuspend + add %sp, STACKFRAME_SZ, %o0 + + ld [%curptr + TI_FLAGS], %l5 + andcc %l5, _TIF_SYSCALL_TRACE, %g0 + be 1f + nop + + call syscall_trace + nop + +1: + /* We are returning to a signal handler. */ + RESTORE_ALL + + .align 4 + .globl sys_rt_sigsuspend +sys_rt_sigsuspend: + /* Note: %o0, %o1 already have correct value... */ + call do_rt_sigsuspend + add %sp, STACKFRAME_SZ, %o2 + + ld [%curptr + TI_FLAGS], %l5 + andcc %l5, _TIF_SYSCALL_TRACE, %g0 + be 1f + nop + + call syscall_trace + nop + +1: + /* We are returning to a signal handler. */ + RESTORE_ALL + + .align 4 + .globl sys_sigreturn +sys_sigreturn: + call do_sigreturn + add %sp, STACKFRAME_SZ, %o0 + + ld [%curptr + TI_FLAGS], %l5 + andcc %l5, _TIF_SYSCALL_TRACE, %g0 + be 1f + nop + + call syscall_trace + nop + +1: + /* We don't want to muck with user registers like a + * normal syscall, just return. + */ + RESTORE_ALL + + .align 4 + .globl sys_rt_sigreturn +sys_rt_sigreturn: + call do_rt_sigreturn + add %sp, STACKFRAME_SZ, %o0 + + ld [%curptr