From 4508dc21feb189159d4cc1d5b79c5a55fad5f2ed Mon Sep 17 00:00:00 2001 From: David Gibson Date: Wed, 13 Jun 2007 14:52:57 +1000 Subject: [POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson Signed-off-by: Paul Mackerras --- arch/ppc/kernel/misc.S | 8 ++++---- arch/ppc/kernel/setup.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S index d319f9ba237..0da55368655 100644 --- a/arch/ppc/kernel/misc.S +++ b/arch/ppc/kernel/misc.S @@ -328,7 +328,7 @@ BEGIN_FTR_SECTION mtspr SPRN_L1CSR0,r3 isync blr -END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) +END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE) mfspr r3,SPRN_L1CSR1 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR mtspr SPRN_L1CSR1,r3 @@ -355,7 +355,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) _GLOBAL(__flush_icache_range) BEGIN_FTR_SECTION blr /* for 601, do nothing */ -END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) +END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 @@ -472,7 +472,7 @@ _GLOBAL(flush_dcache_all) _GLOBAL(__flush_dcache_icache) BEGIN_FTR_SECTION blr /* for 601, do nothing */ -END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) +END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) rlwinm r3,r3,0,0,19 /* Get page base address */ li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ mtctr r4 @@ -500,7 +500,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) _GLOBAL(__flush_dcache_icache_phys) BEGIN_FTR_SECTION blr /* for 601, do nothing */ -END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) +END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) mfmsr r10 rlwinm r0,r10,0,28,26 /* clear DR */ mtmsr r0 diff --git a/arch/ppc/kernel/setup.c b/arch/ppc/kernel/setup.c index c79704f5409..967c1ef59a6 100644 --- a/arch/ppc/kernel/setup.c +++ b/arch/ppc/kernel/setup.c @@ -526,7 +526,7 @@ void __init setup_arch(char **cmdline_p) * Systems with OF can look in the properties on the cpu node(s) * for a possibly more accurate value. */ - if (cpu_has_feature(CPU_FTR_SPLIT_ID_CACHE)) { + if (! cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) { dcache_bsize = cur_cpu_spec->dcache_bsize; icache_bsize = cur_cpu_spec->icache_bsize; ucache_bsize = 0; -- cgit v1.2.3-18-g5258 From ea1a734ad73478dace97e9712101029f536d10a3 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Wed, 27 Jun 2007 16:54:58 +1000 Subject: [POWERPC] Abolish unused ucBoardRev variables asm-powerpc/processor.h declares, and arch/ppc/platforms/prep_setup.c defines variables ucBoardRev, ucBoardRevMaj and ucBoardRevMin which are used nowhere in the current kernel (neither in arch/ppc nor arch/powerpc). This removes them. Signed-off-by: David Gibson Signed-off-by: Paul Mackerras --- arch/ppc/platforms/prep_setup.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/platforms/prep_setup.c b/arch/ppc/platforms/prep_setup.c index 6f21110a974..3c56654bfc6 100644 --- a/arch/ppc/platforms/prep_setup.c +++ b/arch/ppc/platforms/prep_setup.c @@ -69,9 +69,6 @@ TODC_ALLOC(); -unsigned char ucBoardRev; -unsigned char ucBoardRevMaj, ucBoardRevMin; - extern unsigned char prep_nvram_read_val(int addr); extern void prep_nvram_write_val(int addr, unsigned char val); -- cgit v1.2.3-18-g5258 From 7d52c7b0cd46f42ae2c9df37f1a385d9aaf95842 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 22 Jun 2007 00:23:57 -0500 Subject: [POWERPC] Pass the pci_controller into pci_exclude_device There are times that we need to know which controller we are on to decide how to exclude devices properly. We now pass the pci_controller that we are going to use down to the pci_exclude_device function. This will greatly simplify being able to exclude the PHBs in multiple controller setups. Signed-off-by: Kumar Gala --- arch/ppc/syslib/Makefile | 1 + arch/ppc/syslib/indirect_pci.c | 134 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 135 insertions(+) create mode 100644 arch/ppc/syslib/indirect_pci.c (limited to 'arch/ppc') diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile index 95694159b22..543795be58c 100644 --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile @@ -7,6 +7,7 @@ CFLAGS_btext.o += -fPIC wdt-mpc8xx-$(CONFIG_8xx_WDT) += m8xx_wdt.o +obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram.o obj-$(CONFIG_PPC_OCP) += ocp.o obj-$(CONFIG_IBM_OCP) += ibm_ocp.o diff --git a/arch/ppc/syslib/indirect_pci.c b/arch/ppc/syslib/indirect_pci.c new file mode 100644 index 00000000000..83b323a7d02 --- /dev/null +++ b/arch/ppc/syslib/indirect_pci.c @@ -0,0 +1,134 @@ +/* + * Support for indirect PCI bridges. + * + * Copyright (C) 1998 Gabriel Paubert. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_PPC_INDIRECT_PCI_BE +#define PCI_CFG_OUT out_be32 +#else +#define PCI_CFG_OUT out_le32 +#endif + +static int +indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, + int len, u32 *val) +{ + struct pci_controller *hose = bus->sysdata; + volatile void __iomem *cfg_data; + u8 cfg_type = 0; + + if (ppc_md.pci_exclude_device) + if (ppc_md.pci_exclude_device(bus->number, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (hose->set_cfg_type) + if (bus->number != hose->first_busno) + cfg_type = 1; + + PCI_CFG_OUT(hose->cfg_addr, + (0x80000000 | ((bus->number - hose->bus_offset) << 16) + | (devfn << 8) | ((offset & 0xfc) | cfg_type))); + + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + cfg_data = hose->cfg_data + (offset & 3); + switch (len) { + case 1: + *val = in_8(cfg_data); + break; + case 2: + *val = in_le16(cfg_data); + break; + default: + *val = in_le32(cfg_data); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +static int +indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, + int len, u32 val) +{ + struct pci_controller *hose = bus->sysdata; + volatile void __iomem *cfg_data; + u8 cfg_type = 0; + + if (ppc_md.pci_exclude_device) + if (ppc_md.pci_exclude_device(bus->number, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (hose->set_cfg_type) + if (bus->number != hose->first_busno) + cfg_type = 1; + + PCI_CFG_OUT(hose->cfg_addr, + (0x80000000 | ((bus->number - hose->bus_offset) << 16) + | (devfn << 8) | ((offset & 0xfc) | cfg_type))); + + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + cfg_data = hose->cfg_data + (offset & 3); + switch (len) { + case 1: + out_8(cfg_data, val); + break; + case 2: + out_le16(cfg_data, val); + break; + default: + out_le32(cfg_data, val); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops indirect_pci_ops = +{ + indirect_read_config, + indirect_write_config +}; + +void __init +setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem * cfg_addr, + void __iomem * cfg_data) +{ + hose->cfg_addr = cfg_addr; + hose->cfg_data = cfg_data; + hose->ops = &indirect_pci_ops; +} + +void __init +setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) +{ + unsigned long base = cfg_addr & PAGE_MASK; + void __iomem *mbase, *addr, *data; + + mbase = ioremap(base, PAGE_SIZE); + addr = mbase + (cfg_addr & ~PAGE_MASK); + if ((cfg_data & PAGE_MASK) != base) + mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); + data = mbase + (cfg_data & ~PAGE_MASK); + setup_indirect_pci_nomap(hose, addr, data); +} -- cgit v1.2.3-18-g5258 From cef1a3a5b8697ad76a6d18753e418cfe6a897030 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 9 Jul 2007 14:58:18 +0200 Subject: [PPC] Add linux/pagemap.h to arch/ppc/mm/tlb.c When compiled without swap support, arch/mm/tlb.c complains about missing function declarations. This patch fixes the warnings. Signed-off-by: Laurent Pinchart Signed-off-by: Kumar Gala --- arch/ppc/mm/tlb.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/ppc') diff --git a/arch/ppc/mm/tlb.c b/arch/ppc/mm/tlb.c index fa29740a28f..4ff260bc9dd 100644 --- a/arch/ppc/mm/tlb.c +++ b/arch/ppc/mm/tlb.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3-18-g5258 From ca747ddf29773d552fc0e0dcde0d92b807cd6b85 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 29 May 2007 21:49:01 +1000 Subject: [POWERPC] Remove unused do_signal export do_signal is never used in modular code (obviously), and no other architecture exports it either. Signed-off-by: Christoph Hellwig Signed-off-by: Paul Mackerras --- arch/ppc/kernel/ppc_ksyms.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/ppc') diff --git a/arch/ppc/kernel/ppc_ksyms.c b/arch/ppc/kernel/ppc_ksyms.c index a4165209ac7..63f0a987139 100644 --- a/arch/ppc/kernel/ppc_ksyms.c +++ b/arch/ppc/kernel/ppc_ksyms.c @@ -64,7 +64,6 @@ extern unsigned long mm_ptov (unsigned long paddr); EXPORT_SYMBOL(clear_pages); EXPORT_SYMBOL(clear_user_page); -EXPORT_SYMBOL(do_signal); EXPORT_SYMBOL(transfer_to_handler); EXPORT_SYMBOL(do_IRQ); EXPORT_SYMBOL(machine_check_exception); -- cgit v1.2.3-18-g5258 From a527ad88a2f11f7ccab3038608e5c50ceae570a3 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 10 Jul 2007 09:51:05 +1000 Subject: [POWERPC] xilinxfb: Parameterize xilinxfb platform device registration This allows multiple xilinxfb devices to be registered and used. Signed-off-by: Grant Likely cc: Andrei Konovalov Signed-off-by: Paul Mackerras --- arch/ppc/syslib/virtex_devices.c | 38 +++++++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 13 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/syslib/virtex_devices.c b/arch/ppc/syslib/virtex_devices.c index 16546788e23..ace4ec08de5 100644 --- a/arch/ppc/syslib/virtex_devices.c +++ b/arch/ppc/syslib/virtex_devices.c @@ -71,6 +71,21 @@ }, \ } +/* + * ML300/ML403 Video Device: shortcut macro for single instance + */ +#define XPAR_TFT(num) { \ + .name = "xilinxfb", \ + .id = num, \ + .num_resources = 1, \ + .resource = (struct resource[]) { \ + { \ + .start = XPAR_TFT_##num##_BASEADDR, \ + .end = XPAR_TFT_##num##_BASEADDR+7, \ + .flags = IORESOURCE_IO, \ + }, \ + }, \ +} /* UART 8250 driver platform data table */ struct plat_serial8250_port virtex_serial_platform_data[] = { @@ -146,20 +161,17 @@ struct platform_device virtex_platform_devices[] = { XPAR_SYSACE(1), #endif - /* ML300/403 reference design framebuffer */ #if defined(XPAR_TFT_0_BASEADDR) - { - .name = "xilinxfb", - .id = 0, - .num_resources = 1, - .resource = (struct resource[]) { - { - .start = XPAR_TFT_0_BASEADDR, - .end = XPAR_TFT_0_BASEADDR+7, - .flags = IORESOURCE_IO, - }, - }, - }, + XPAR_TFT(0), +#endif +#if defined(XPAR_TFT_1_BASEADDR) + XPAR_TFT(1), +#endif +#if defined(XPAR_TFT_2_BASEADDR) + XPAR_TFT(2), +#endif +#if defined(XPAR_TFT_3_BASEADDR) + XPAR_TFT(3), #endif }; -- cgit v1.2.3-18-g5258