From f10e2e5b4b4c9937de596f96ffe028be3a565598 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Wed, 10 Feb 2010 01:04:06 +0000 Subject: powerpc: Rename LWSYNC_ON_SMP to PPC_RELEASE_BARRIER, ISYNC_ON_SMP to PPC_ACQUIRE_BARRIER For performance reasons we are about to change ISYNC_ON_SMP to sometimes be lwsync. Now that the macro name doesn't make sense, change it and LWSYNC_ON_SMP to better explain what the barriers are doing. Signed-off-by: Anton Blanchard Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/futex.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/powerpc/include/asm/futex.h') diff --git a/arch/powerpc/include/asm/futex.h b/arch/powerpc/include/asm/futex.h index 9696cc36d2d..7c589ef81fb 100644 --- a/arch/powerpc/include/asm/futex.h +++ b/arch/powerpc/include/asm/futex.h @@ -11,7 +11,7 @@ #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ __asm__ __volatile ( \ - LWSYNC_ON_SMP \ + PPC_RELEASE_BARRIER \ "1: lwarx %0,0,%2\n" \ insn \ PPC405_ERR77(0, %2) \ @@ -90,14 +90,14 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) return -EFAULT; __asm__ __volatile__ ( - LWSYNC_ON_SMP + PPC_RELEASE_BARRIER "1: lwarx %0,0,%2 # futex_atomic_cmpxchg_inatomic\n\ cmpw 0,%0,%3\n\ bne- 3f\n" PPC405_ERR77(0,%2) "2: stwcx. %4,0,%2\n\ bne- 1b\n" - ISYNC_ON_SMP + PPC_ACQUIRE_BARRIER "3: .section .fixup,\"ax\"\n\ 4: li %0,%5\n\ b 3b\n\ -- cgit v1.2.3-18-g5258