From f80658137fc8b789a71953adeca194a5a4747427 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 2 Mar 2006 22:41:59 +0000 Subject: [ARM] Move HZ definition into Kconfig Move the HZ definition into Kconfig, and set appropriate defaults for platforms. Remove mostly empty asm/arch/param.h include file. Signed-off-by: Russell King --- arch/arm/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 32ba00bd0a2..2c63228b4ab 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -434,6 +434,13 @@ config NO_IDLE_HZ Currently at least OMAP, PXA2xx and SA11x0 platforms are known to have accurate timekeeping with dynamic tick. +config HZ + int + default 128 if ARCH_L7200 + default 200 if ARCH_EBSA110 || ARCH_S3C2410 + default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER_HZ != 0 + default 100 + config AEABI bool "Use the ARM EABI to compile the kernel" help -- cgit v1.2.3-18-g5258 From 411ef7f4cf1684ca7977c7917fd841ea091c5b26 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Mar 2006 10:37:07 +0000 Subject: [ARM] Remove asm/arch/irq.h asm/arch/irq.h used to be included from asm/irq.h, but was removed from the ARM kernel a long time ago. Consequently, the contents of asm/arch/irq.h (which mostly contain a definition for fixup_irq()) have not been used. Hence, remove asm/arch/irq.h. Some machine support files incorrectly included this file, making little or no use of the contents. Move the contents to a local include file, and remove those include statements as well. Signed-off-by: Russell King --- arch/arm/mach-lh7a40x/common.h | 1 + arch/arm/mach-lh7a40x/irq-kev7a400.c | 1 + arch/arm/mach-lh7a40x/irq-lh7a400.c | 2 +- arch/arm/mach-lh7a40x/irq-lh7a404.c | 3 ++- arch/arm/mach-lh7a40x/irq-lpd7a40x.c | 1 + arch/arm/mach-pxa/corgi.c | 1 - arch/arm/mach-pxa/poodle.c | 1 - arch/arm/mach-pxa/spitz.c | 1 - arch/arm/mach-pxa/tosa.c | 1 - 9 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-lh7a40x/common.h b/arch/arm/mach-lh7a40x/common.h index 578a52461fd..ea8de7e3ab1 100644 --- a/arch/arm/mach-lh7a40x/common.h +++ b/arch/arm/mach-lh7a40x/common.h @@ -12,5 +12,6 @@ extern struct sys_timer lh7a40x_timer; extern void lh7a400_init_irq (void); extern void lh7a404_init_irq (void); +extern void lh7a40x_init_board_irq (void); #define IRQ_DISPATCH(irq) desc_handle_irq((irq),(irq_desc + irq), regs) diff --git a/arch/arm/mach-lh7a40x/irq-kev7a400.c b/arch/arm/mach-lh7a40x/irq-kev7a400.c index 691bb09232a..8535764d89c 100644 --- a/arch/arm/mach-lh7a40x/irq-kev7a400.c +++ b/arch/arm/mach-lh7a40x/irq-kev7a400.c @@ -16,6 +16,7 @@ #include #include +#include "common.h" /* KEV7a400 CPLD IRQ handling */ diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c index f334d81c2cd..f9fdefef6d6 100644 --- a/arch/arm/mach-lh7a40x/irq-lh7a400.c +++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c @@ -16,9 +16,9 @@ #include #include #include -#include #include +#include "common.h" /* CPU IRQ handling */ diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c index 122fadabc97..e902e3d87da 100644 --- a/arch/arm/mach-lh7a40x/irq-lh7a404.c +++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c @@ -16,9 +16,10 @@ #include #include #include -#include #include +#include "common.h" + #define USE_PRIORITIES /* See Documentation/arm/Sharp-LH/VectoredInterruptController for more diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c index 6262d449120..dcb4e17b941 100644 --- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c +++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c @@ -19,6 +19,7 @@ #include #include +#include "common.h" static void lh7a40x_ack_cpld_irq (u32 irq) { diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 7ffd2de8f2f..68923b1d2b6 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -32,7 +32,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 911e6ff5a9b..b45560a8f6c 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -29,7 +29,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index c094d99ebf5..30ec317bbb9 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -33,7 +33,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index d168286ed47..66ec71756d0 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -34,7 +34,6 @@ #include #include -#include #include #include -- cgit v1.2.3-18-g5258 From bfe65704812f82751470106ea50aeb7e7d37cc3f Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Mar 2006 11:01:53 +0000 Subject: [ARM] Fix HZ definition for OMAP without 32K timer Unfortunately, OMAP platforms without the 32K timer left HZ set to an empty value. Fix this by making the dependency on OMAP_32K_TIMER rather than OMAP_32K_TIMER_HZ. Signed-off-by: Russell King --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c63228b4ab..6e9e8cedd72 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -438,7 +438,7 @@ config HZ int default 128 if ARCH_L7200 default 200 if ARCH_EBSA110 || ARCH_S3C2410 - default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER_HZ != 0 + default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER default 100 config AEABI -- cgit v1.2.3-18-g5258 From f78f10436806660f39440a729acbaf03e3a01023 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Mar 2006 11:04:12 +0000 Subject: [ARM] Remove unnecessary asm/hardware.h includes asm/hardware.h is not required for the majority of processor support files, ioremap support, mm initialisation, acorn IO support, nor the debug code (which picks up its machine specific includes via debug-macros.S) Signed-off-by: Russell King --- arch/arm/kernel/debug.S | 1 - arch/arm/lib/io-acorn.S | 1 - arch/arm/mm/init.c | 1 - arch/arm/mm/ioremap.c | 1 - arch/arm/mm/proc-arm1020.S | 1 - arch/arm/mm/proc-arm1020e.S | 1 - arch/arm/mm/proc-arm720.S | 1 - arch/arm/mm/proc-arm920.S | 1 - arch/arm/mm/proc-arm922.S | 1 - arch/arm/mm/proc-arm925.S | 1 - arch/arm/mm/proc-arm926.S | 1 - arch/arm/mm/proc-xscale.S | 1 - 12 files changed, 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index caaa919ab47..da280bae3d0 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -11,7 +11,6 @@ */ #include #include -#include .text diff --git a/arch/arm/lib/io-acorn.S b/arch/arm/lib/io-acorn.S index b153523631c..1b197ea7aab 100644 --- a/arch/arm/lib/io-acorn.S +++ b/arch/arm/lib/io-acorn.S @@ -12,7 +12,6 @@ */ #include #include -#include .text .align diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 8b276ee38ac..efda9710ee6 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -19,7 +19,6 @@ #include #include -#include #include #include diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index da9b3597411..25e0ca3e598 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -26,7 +26,6 @@ #include #include -#include #include #include diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 82ec954e45b..3aa80094012 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -32,7 +32,6 @@ #include #include #include -#include /* * This is the maximum size of an area which will be invalidated diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 7375fe930f7..767d158f211 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -32,7 +32,6 @@ #include #include #include -#include /* * This is the maximum size of an area which will be invalidated diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index a13e0184d34..471286fdf78 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -37,7 +37,6 @@ #include #include #include -#include /* * Function: arm720_proc_init (void) diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index d1651389999..950d3b664c1 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include "proc-macros.S" diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index 23b8ed97f4e..410b032faa3 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include "proc-macros.S" diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index ee95c52db51..6dd2be7cd05 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -53,7 +53,6 @@ #include #include #include -#include #include #include #include "proc-macros.S" diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 7d042dc20c4..022e8684204 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include "proc-macros.S" diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 2d3823ec315..b50f87a0ee7 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include -- cgit v1.2.3-18-g5258 From 5d25ac038a317d454a4321cba955f756400835a5 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 15 Mar 2006 12:33:43 +0000 Subject: [ARM] Move IRQ enable after coprocessor number decode Allow the individual coprocessor handlers to decide when to enable interrupts, rather than unconditionally enabling them. Signed-off-by: Russell King --- arch/arm/kernel/entry-armv.S | 2 +- arch/arm/vfp/entry.S | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index ec48d70c6d8..355914ffb19 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -484,7 +484,6 @@ call_fpe: movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) bcs iwmmxt_task_enable #endif - enable_irq add pc, pc, r8, lsr #6 mov r0, r0 @@ -511,6 +510,7 @@ call_fpe: mov pc, lr @ CP#15 (Control) do_fpe: + enable_irq ldr r4, .LCfp add r10, r10, #TI_FPSTATE @ r10 = workspace ldr pc, [r4] @ Call FP module USR entry point diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index 6f17187ab32..9ab1abfbe7a 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -22,6 +22,7 @@ .globl do_vfp do_vfp: + enable_irq ldr r4, .LCvfp add r10, r10, #TI_VFPSTATE @ r10 = workspace ldr pc, [r4] @ call VFP entry point -- cgit v1.2.3-18-g5258 From 548153663bbf33ca7c244a6bbddd82c26a17c331 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 15 Mar 2006 15:43:04 +0000 Subject: [ARM] Rename chipdata to 'base' and make it an iomem pointer In all current use cases, "chipdata" is used to store an iomem address. Mark it with __iomem, and rename it to 'base'. Leave the accessor macros alone. Signed-off-by: Russell King --- arch/arm/common/locomo.c | 42 ++++++++++++++++++++--------------------- arch/arm/mach-at91rm9200/gpio.c | 4 ++-- 2 files changed, 23 insertions(+), 23 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index 23609400a8e..787e0d027f0 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -60,7 +60,7 @@ struct locomo { unsigned long phys; unsigned int irq; spinlock_t lock; - void *base; + void __iomem *base; }; struct locomo_dev_info { @@ -162,7 +162,7 @@ static void locomo_handler(unsigned int irq, struct irqdesc *desc, { int req, i; struct irqdesc *d; - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); /* Acknowledge the parent IRQ */ desc->chip->ack(irq); @@ -189,7 +189,7 @@ static void locomo_ack_irq(unsigned int irq) static void locomo_mask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_ICR); r &= ~(0x0010 << (irq - LOCOMO_IRQ_START)); @@ -198,7 +198,7 @@ static void locomo_mask_irq(unsigned int irq) static void locomo_unmask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_ICR); r |= (0x0010 << (irq - LOCOMO_IRQ_START)); @@ -215,7 +215,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) { struct irqdesc *d; - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) { d = irq_desc + LOCOMO_IRQ_KEY_START; @@ -225,7 +225,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc, static void locomo_key_ack_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START)); @@ -234,7 +234,7 @@ static void locomo_key_ack_irq(unsigned int irq) static void locomo_key_mask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START)); @@ -243,7 +243,7 @@ static void locomo_key_mask_irq(unsigned int irq) static void locomo_key_unmask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START)); @@ -261,7 +261,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc, { int req, i; struct irqdesc *d; - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); req = locomo_readl(mapbase + LOCOMO_GIR) & locomo_readl(mapbase + LOCOMO_GPD) & @@ -280,7 +280,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc, static void locomo_gpio_ack_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_GWE); r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); @@ -297,7 +297,7 @@ static void locomo_gpio_ack_irq(unsigned int irq) static void locomo_gpio_mask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_GIE); r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); @@ -306,7 +306,7 @@ static void locomo_gpio_mask_irq(unsigned int irq) static void locomo_gpio_unmask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_GIE); r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); @@ -323,7 +323,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) { struct irqdesc *d; - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) { d = irq_desc + LOCOMO_IRQ_LT_START; @@ -333,7 +333,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc, static void locomo_lt_ack_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_LTINT); r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START)); @@ -342,7 +342,7 @@ static void locomo_lt_ack_irq(unsigned int irq) static void locomo_lt_mask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_LTINT); r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START)); @@ -351,7 +351,7 @@ static void locomo_lt_mask_irq(unsigned int irq) static void locomo_lt_unmask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_LTINT); r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START)); @@ -369,7 +369,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc, { int req, i; struct irqdesc *d; - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); req = locomo_readl(mapbase + LOCOMO_SPIIR) & 0x000F; if (req) { @@ -386,7 +386,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc, static void locomo_spi_ack_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_SPIWE); r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); @@ -403,7 +403,7 @@ static void locomo_spi_ack_irq(unsigned int irq) static void locomo_spi_mask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_SPIIE); r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); @@ -412,7 +412,7 @@ static void locomo_spi_mask_irq(unsigned int irq) static void locomo_spi_unmask_irq(unsigned int irq) { - void *mapbase = get_irq_chipdata(irq); + void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; r = locomo_readl(mapbase + LOCOMO_SPIIE); r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); @@ -428,7 +428,7 @@ static struct irqchip locomo_spi_chip = { static void locomo_setup_irq(struct locomo *lchip) { int irq; - void *irqbase = lchip->base; + void __iomem *irqbase = lchip->base; /* * Install handler for IRQ_LOCOMO_HW. diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c index 0e396feec46..5ab46274e1a 100644 --- a/arch/arm/mach-at91rm9200/gpio.c +++ b/arch/arm/mach-at91rm9200/gpio.c @@ -261,7 +261,7 @@ static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs void __iomem *pio; u32 isr; - pio = (void __force __iomem *) desc->chipdata; + pio = desc->base; /* temporarily mask (level sensitive) parent IRQ */ desc->chip->ack(irq); @@ -312,7 +312,7 @@ void __init at91_gpio_irq_setup(unsigned banks) __raw_writel(~0, controller + PIO_IDR); set_irq_data(id, (void *) pin); - set_irq_chipdata(id, (void __force *) controller); + set_irq_chipdata(id, controller); for (i = 0; i < 32; i++, pin++) { set_irq_chip(pin, &gpio_irqchip); -- cgit v1.2.3-18-g5258 From 824b5b5e59472c89bc508afa5c453547c91ed53b Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 15 Mar 2006 15:44:29 +0000 Subject: [ARM] Adapt vic.c to allow for multiple VICs in a system. Some SoCs have multiple VIC devices. Adapt the generic vic code to allow multiple implementations to be handled. Signed-off-by: Russell King --- arch/arm/common/vic.c | 49 +++++++++++++++++++++++------------------- arch/arm/mach-versatile/core.c | 2 +- 2 files changed, 28 insertions(+), 23 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index a45ed1687a5..a19bc4a6196 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -22,22 +22,21 @@ #include #include -#include #include #include -static void __iomem *vic_base; - static void vic_mask_irq(unsigned int irq) { - irq -= IRQ_VIC_START; - writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR); + void __iomem *base = get_irq_chipdata(irq); + irq &= 31; + writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); } static void vic_unmask_irq(unsigned int irq) { - irq -= IRQ_VIC_START; - writel(1 << irq, vic_base + VIC_INT_ENABLE); + void __iomem *base = get_irq_chipdata(irq); + irq &= 31; + writel(1 << irq, base + VIC_INT_ENABLE); } static struct irqchip vic_chip = { @@ -46,43 +45,49 @@ static struct irqchip vic_chip = { .unmask = vic_unmask_irq, }; -void __init vic_init(void __iomem *base, u32 vic_sources) +/** + * vic_init - initialise a vectored interrupt controller + * @base: iomem base address + * @irq_start: starting interrupt number, must be muliple of 32 + * @vic_sources: bitmask of interrupt sources to allow + */ +void __init vic_init(void __iomem *base, unsigned int irq_start, + u32 vic_sources) { unsigned int i; - vic_base = base; - /* Disable all interrupts initially. */ - writel(0, vic_base + VIC_INT_SELECT); - writel(0, vic_base + VIC_INT_ENABLE); - writel(~0, vic_base + VIC_INT_ENABLE_CLEAR); - writel(0, vic_base + VIC_IRQ_STATUS); - writel(0, vic_base + VIC_ITCR); - writel(~0, vic_base + VIC_INT_SOFT_CLEAR); + writel(0, base + VIC_INT_SELECT); + writel(0, base + VIC_INT_ENABLE); + writel(~0, base + VIC_INT_ENABLE_CLEAR); + writel(0, base + VIC_IRQ_STATUS); + writel(0, base + VIC_ITCR); + writel(~0, base + VIC_INT_SOFT_CLEAR); /* * Make sure we clear all existing interrupts */ - writel(0, vic_base + VIC_VECT_ADDR); + writel(0, base + VIC_VECT_ADDR); for (i = 0; i < 19; i++) { unsigned int value; - value = readl(vic_base + VIC_VECT_ADDR); - writel(value, vic_base + VIC_VECT_ADDR); + value = readl(base + VIC_VECT_ADDR); + writel(value, base + VIC_VECT_ADDR); } for (i = 0; i < 16; i++) { - void __iomem *reg = vic_base + VIC_VECT_CNTL0 + (i * 4); + void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); writel(VIC_VECT_CNTL_ENABLE | i, reg); } - writel(32, vic_base + VIC_DEF_VECT_ADDR); + writel(32, base + VIC_DEF_VECT_ADDR); for (i = 0; i < 32; i++) { - unsigned int irq = IRQ_VIC_START + i; + unsigned int irq = irq_start + i; set_irq_chip(irq, &vic_chip); + set_irq_chipdata(irq, base); if (vic_sources & (1 << i)) { set_irq_handler(irq, do_level_IRQ); diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 9ebbe808b41..799697d32de 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -112,7 +112,7 @@ void __init versatile_init_irq(void) { unsigned int i; - vic_init(VA_VIC_BASE, ~(1 << 31)); + vic_init(VA_VIC_BASE, IRQ_VIC_START, ~(1 << 31)); set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq); enable_irq(IRQ_VICSOURCE31); -- cgit v1.2.3-18-g5258 From 97d654f8eb4b8fbb6e1afef076429a4235a3a3ad Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 15 Mar 2006 15:54:37 +0000 Subject: [ARM] Convert SA1111 to use clock architecture Signed-off-by: Russell King --- arch/arm/common/sa1111.c | 41 +++++++------ arch/arm/mach-pxa/Makefile | 2 +- arch/arm/mach-pxa/clock.c | 124 +++++++++++++++++++++++++++++++++++++++ arch/arm/mach-sa1100/Makefile | 2 +- arch/arm/mach-sa1100/clock.c | 132 ++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 278 insertions(+), 23 deletions(-) create mode 100644 arch/arm/mach-pxa/clock.c create mode 100644 arch/arm/mach-sa1100/clock.c (limited to 'arch/arm') diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 93352f6097c..5ba1ee04234 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -36,10 +37,6 @@ #include -#ifdef CONFIG_ARCH_PXA -#include -#endif - extern void __init sa1110_mb_enable(void); /* @@ -51,6 +48,7 @@ extern void __init sa1110_mb_enable(void); */ struct sa1111 { struct device *dev; + struct clk *clk; unsigned long phys; int irq; spinlock_t lock; @@ -451,19 +449,7 @@ static void sa1111_wake(struct sa1111 *sachip) spin_lock_irqsave(&sachip->lock, flags); -#ifdef CONFIG_ARCH_SA1100 - /* - * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: - * (SA-1110 Developer's Manual, section 9.1.2.1) - */ - GAFR |= GPIO_32_768kHz; - GPDR |= GPIO_32_768kHz; - TUCR = TUCR_3_6864MHz; -#elif CONFIG_ARCH_PXA - pxa_gpio_mode(GPIO11_3_6MHz_MD); -#else -#error missing clock setup -#endif + clk_enable(sachip->clk); /* * Turn VCO on, and disable PLL Bypass. @@ -641,6 +627,12 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) memset(sachip, 0, sizeof(struct sa1111)); + sachip->clk = clk_get(me, "GPIO27_CLK"); + if (!sachip->clk) { + ret = PTR_ERR(sachip->clk); + goto err_free; + } + spin_lock_init(&sachip->lock); sachip->dev = me; @@ -656,7 +648,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) sachip->base = ioremap(mem->start, PAGE_SIZE * 2); if (!sachip->base) { ret = -ENOMEM; - goto out; + goto err_clkput; } /* @@ -666,7 +658,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id); ret = -ENODEV; - goto unmap; + goto err_unmap; } printk(KERN_INFO "SA1111 Microprocessor Companion Chip: " @@ -726,9 +718,11 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) return 0; - unmap: + err_unmap: iounmap(sachip->base); - out: + err_clkput: + clk_put(sachip->clk); + err_free: kfree(sachip); return ret; } @@ -751,6 +745,8 @@ static void __sa1111_remove(struct sa1111 *sachip) sa1111_writel(0, irqbase + SA1111_WAKEEN0); sa1111_writel(0, irqbase + SA1111_WAKEEN1); + clk_disable(sachip->clk); + if (sachip->irq != NO_IRQ) { set_irq_chained_handler(sachip->irq, NULL); set_irq_data(sachip->irq, NULL); @@ -759,6 +755,7 @@ static void __sa1111_remove(struct sa1111 *sachip) } iounmap(sachip->base); + clk_put(sachip->clk); kfree(sachip); } @@ -857,6 +854,8 @@ static int sa1111_suspend(struct platform_device *dev, pm_message_t state) sa1111_writel(0, sachip->base + SA1111_SKPWM0); sa1111_writel(0, sachip->base + SA1111_SKPWM1); + clk_disable(sachip->clk); + spin_unlock_irqrestore(&sachip->lock, flags); return 0; diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 32526a0a6f8..382644401a4 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -3,7 +3,7 @@ # # Common support (must be linked before board specific support) -obj-y += generic.o irq.o dma.o time.o +obj-y += clock.o generic.o irq.o dma.o time.o obj-$(CONFIG_PXA25x) += pxa25x.o obj-$(CONFIG_PXA27x) += pxa27x.o diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c new file mode 100644 index 00000000000..8f7c90a0593 --- /dev/null +++ b/arch/arm/mach-pxa/clock.c @@ -0,0 +1,124 @@ +/* + * linux/arch/arm/mach-sa1100/clock.c + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +struct clk { + struct list_head node; + unsigned long rate; + struct module *owner; + const char *name; + unsigned int enabled; + void (*enable)(void); + void (*disable)(void); +}; + +static LIST_HEAD(clocks); +static DECLARE_MUTEX(clocks_sem); +static DEFINE_SPINLOCK(clocks_lock); + +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *p, *clk = ERR_PTR(-ENOENT); + + down(&clocks_sem); + list_for_each_entry(p, &clocks, node) { + if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { + clk = p; + break; + } + } + up(&clocks_sem); + + return clk; +} +EXPORT_SYMBOL(clk_get); + +void clk_put(struct clk *clk) +{ + module_put(clk->owner); +} +EXPORT_SYMBOL(clk_put); + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + if (clk->enabled++ == 0) + clk->enable(); + spin_unlock_irqrestore(&clocks_lock, flags); + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + WARN_ON(clk->enabled == 0); + + spin_lock_irqsave(&clocks_lock, flags); + if (--clk->enabled == 0) + clk->disable(); + spin_unlock_irqrestore(&clocks_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + + +static void clk_gpio27_enable(void) +{ + pxa_gpio_mode(GPIO11_3_6MHz_MD); +} + +static void clk_gpio27_disable(void) +{ +} + +static struct clk clk_gpio27 = { + .name = "GPIO27_CLK", + .rate = 3686400, + .enable = clk_gpio27_enable, + .disable = clk_gpio27_disable, +}; + +int clk_register(struct clk *clk) +{ + down(&clocks_sem); + list_add(&clk->node, &clocks); + up(&clocks_sem); + return 0; +} +EXPORT_SYMBOL(clk_register); + +void clk_unregister(struct clk *clk) +{ + down(&clocks_sem); + list_del(&clk->node); + up(&clocks_sem); +} +EXPORT_SYMBOL(clk_unregister); + +static int __init clk_init(void) +{ + clk_register(&clk_gpio27); + return 0; +} +arch_initcall(clk_init); diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index e4a4a3e8aa8..e27f15042a2 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := generic.o irq.o dma.o time.o +obj-y := clock.o generic.o irq.o dma.o time.o #nmi-oopser.o obj-m := obj-n := obj- := diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c new file mode 100644 index 00000000000..b1e8fd766c1 --- /dev/null +++ b/arch/arm/mach-sa1100/clock.c @@ -0,0 +1,132 @@ +/* + * linux/arch/arm/mach-sa1100/clock.c + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct clk { + struct list_head node; + unsigned long rate; + struct module *owner; + const char *name; + unsigned int enabled; + void (*enable)(void); + void (*disable)(void); +}; + +static LIST_HEAD(clocks); +static DECLARE_MUTEX(clocks_sem); +static DEFINE_SPINLOCK(clocks_lock); + +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *p, *clk = ERR_PTR(-ENOENT); + + down(&clocks_sem); + list_for_each_entry(p, &clocks, node) { + if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { + clk = p; + break; + } + } + up(&clocks_sem); + + return clk; +} +EXPORT_SYMBOL(clk_get); + +void clk_put(struct clk *clk) +{ + module_put(clk->owner); +} +EXPORT_SYMBOL(clk_put); + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + if (clk->enabled++ == 0) + clk->enable(); + spin_unlock_irqrestore(&clocks_lock, flags); + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + WARN_ON(clk->enabled == 0); + + spin_lock_irqsave(&clocks_lock, flags); + if (--clk->enabled == 0) + clk->disable(); + spin_unlock_irqrestore(&clocks_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + + +static void clk_gpio27_enable(void) +{ + /* + * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: + * (SA-1110 Developer's Manual, section 9.1.2.1) + */ + GAFR |= GPIO_32_768kHz; + GPDR |= GPIO_32_768kHz; + TUCR = TUCR_3_6864MHz; +} + +static void clk_gpio27_disable(void) +{ + TUCR = 0; + GPDR &= ~GPIO_32_768kHz; + GAFR &= ~GPIO_32_768kHz; +} + +static struct clk clk_gpio27 = { + .name = "GPIO27_CLK", + .rate = 3686400, + .enable = clk_gpio27_enable, + .disable = clk_gpio27_disable, +}; + +int clk_register(struct clk *clk) +{ + down(&clocks_sem); + list_add(&clk->node, &clocks); + up(&clocks_sem); + return 0; +} +EXPORT_SYMBOL(clk_register); + +void clk_unregister(struct clk *clk) +{ + down(&clocks_sem); + list_del(&clk->node); + up(&clocks_sem); +} +EXPORT_SYMBOL(clk_unregister); + +static int __init clk_init(void) +{ + clk_register(&clk_gpio27); + return 0; +} +arch_initcall(clk_init); -- cgit v1.2.3-18-g5258 From a61ea9326d9ba94bcdc21f36bb74aa203657c58f Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Mon, 20 Mar 2006 17:10:01 +0000 Subject: [ARM] 3261/2: remove phys_ram from struct machine_desc (part 3) Patch from Nicolas Pitre This field is redundent since it must be equal to PHYS_OFFSET anyway. There is no reference to it anymore so remove it at last. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/kernel/head.S | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 1aca1775b28..84277fe818a 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -28,10 +28,9 @@ #define PROCINFO_INITFUNC 12 #define MACHINFO_TYPE 0 -#define MACHINFO_PHYSRAM 4 -#define MACHINFO_PHYSIO 8 -#define MACHINFO_PGOFFIO 12 -#define MACHINFO_NAME 16 +#define MACHINFO_PHYSIO 4 +#define MACHINFO_PGOFFIO 8 +#define MACHINFO_NAME 12 #define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET) -- cgit v1.2.3-18-g5258 From 110d322b29c08d8cf1dba599fd45ad2b9752a4bb Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 20 Mar 2006 17:10:02 +0000 Subject: [ARM] 3327/1: S3C2410 - add osiris machine support Patch from Ben Dooks Support for Simtec IM2440D20 CPU modules (Osiris) Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/Kconfig | 7 + arch/arm/mach-s3c2410/Makefile | 1 + arch/arm/mach-s3c2410/mach-osiris.c | 290 ++++++++++++++++++++++++++++++++++++ 3 files changed, 298 insertions(+) create mode 100644 arch/arm/mach-s3c2410/mach-osiris.c (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 0b9d7ca49ec..ed07c4149d8 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -9,6 +9,13 @@ config MACH_ANUBIS Say Y gere if you are using the Simtec Electronics ANUBIS development system +config MACH_OSIRIS + bool "Simtec IM2440D20 (OSIRIS) module" + select CPU_S3C2440 + help + Say Y here if you are using the Simtec IM2440D20 module, also + known as the Osiris. + config ARCH_BAST bool "Simtec Electronics BAST (EB2410ITX)" select CPU_S3C2410 diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 1217bf00309..1b3b476e563 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o # machine specific support obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o +obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o obj-$(CONFIG_ARCH_H1940) += mach-h1940.o obj-$(CONFIG_MACH_N30) += mach-n30.o diff --git a/arch/arm/mach-s3c2410/mach-osiris.c b/arch/arm/mach-s3c2410/mach-osiris.c new file mode 100644 index 00000000000..72083e645e7 --- /dev/null +++ b/arch/arm/mach-s3c2410/mach-osiris.c @@ -0,0 +1,290 @@ +/* linux/arch/arm/mach-s3c2410/mach-osiris.c + * + * Copyright (c) 2005 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "clock.h" +#include "devs.h" +#include "cpu.h" + +/* onboard perihpheral map */ + +static struct map_desc osiris_iodesc[] __initdata = { + /* ISA IO areas (may be over-written later) */ + + { + .virtual = (u32)S3C24XX_VA_ISA_BYTE, + .pfn = __phys_to_pfn(S3C2410_CS5), + .length = SZ_16M, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_WORD, + .pfn = __phys_to_pfn(S3C2410_CS5), + .length = SZ_16M, + .type = MT_DEVICE, + }, + + /* CPLD control registers */ + + { + .virtual = (u32)OSIRIS_VA_CTRL1, + .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1), + .length = SZ_16K, + .type = MT_DEVICE + }, { + .virtual = (u32)OSIRIS_VA_CTRL2, + .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2), + .length = SZ_16K, + .type = MT_DEVICE + }, +}; + +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + +static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = { + [0] = { + .name = "uclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, + [1] = { + .name = "pclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0. + } +}; + + +static struct s3c2410_uartcfg osiris_uartcfgs[] = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + .clocks = osiris_serial_clocks, + .clocks_size = ARRAY_SIZE(osiris_serial_clocks) + }, + [1] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + .clocks = osiris_serial_clocks, + .clocks_size = ARRAY_SIZE(osiris_serial_clocks) + }, +}; + +/* NAND Flash on Osiris board */ + +static int external_map[] = { 2 }; +static int chip0_map[] = { 0 }; +static int chip1_map[] = { 1 }; + +struct mtd_partition osiris_default_nand_part[] = { + [0] = { + .name = "Boot Agent", + .size = SZ_16K, + .offset = 0 + }, + [1] = { + .name = "/boot", + .size = SZ_4M - SZ_16K, + .offset = SZ_16K, + }, + [2] = { + .name = "user1", + .offset = SZ_4M, + .size = SZ_32M - SZ_4M, + }, + [3] = { + .name = "user2", + .offset = SZ_32M, + .size = MTDPART_SIZ_FULL, + } +}; + +/* the Osiris has 3 selectable slots for nand-flash, the two + * on-board chip areas, as well as the external slot. + * + * Note, there is no current hot-plug support for the External + * socket. +*/ + +static struct s3c2410_nand_set osiris_nand_sets[] = { + [1] = { + .name = "External", + .nr_chips = 1, + .nr_map = external_map, + .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), + .partitions = osiris_default_nand_part + }, + [0] = { + .name = "chip0", + .nr_chips = 1, + .nr_map = chip0_map, + .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), + .partitions = osiris_default_nand_part + }, + [2] = { + .name = "chip1", + .nr_chips = 1, + .nr_map = chip1_map, + .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), + .partitions = osiris_default_nand_part + }, +}; + +static void osiris_nand_select(struct s3c2410_nand_set *set, int slot) +{ + unsigned int tmp; + + slot = set->nr_map[slot] & 3; + + pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n", + slot, set, set->nr_map); + + tmp = __raw_readb(OSIRIS_VA_CTRL1); + tmp &= ~OSIRIS_CTRL1_NANDSEL; + tmp |= slot; + + pr_debug("osiris_nand: ctrl1 now %02x\n", tmp); + + __raw_writeb(tmp, OSIRIS_VA_CTRL1); +} + +static struct s3c2410_platform_nand osiris_nand_info = { + .tacls = 25, + .twrph0 = 60, + .twrph1 = 60, + .nr_sets = ARRAY_SIZE(osiris_nand_sets), + .sets = osiris_nand_sets, + .select_chip = osiris_nand_select, +}; + +/* PCMCIA control and configuration */ + +static struct resource osiris_pcmcia_resource[] = { + [0] = { + .start = 0x0f000000, + .end = 0x0f100000, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0x0c000000, + .end = 0x0c100000, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device osiris_pcmcia = { + .name = "osiris-pcmcia", + .id = -1, + .num_resources = ARRAY_SIZE(osiris_pcmcia_resource), + .resource = osiris_pcmcia_resource, +}; + +/* Standard Osiris devices */ + +static struct platform_device *osiris_devices[] __initdata = { + &s3c_device_i2c, + &s3c_device_nand, + &osiris_pcmcia, +}; + +static struct clk *osiris_clocks[] = { + &s3c24xx_dclk0, + &s3c24xx_dclk1, + &s3c24xx_clkout0, + &s3c24xx_clkout1, + &s3c24xx_uclk, +}; + +static struct s3c24xx_board osiris_board __initdata = { + .devices = osiris_devices, + .devices_count = ARRAY_SIZE(osiris_devices), + .clocks = osiris_clocks, + .clocks_count = ARRAY_SIZE(osiris_clocks) +}; + +void __init osiris_map_io(void) +{ + /* initialise the clocks */ + + s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.rate = 12*1000*1000; + + s3c24xx_dclk1.parent = NULL; + s3c24xx_dclk1.rate = 24*1000*1000; + + s3c24xx_clkout0.parent = &s3c24xx_dclk0; + s3c24xx_clkout1.parent = &s3c24xx_dclk1; + + s3c24xx_uclk.parent = &s3c24xx_clkout1; + + s3c_device_nand.dev.platform_data = &osiris_nand_info; + + s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); + s3c24xx_init_clocks(0); + s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); + s3c24xx_set_board(&osiris_board); + + /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */ + __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON); + + /* write-protect line to the NAND */ + s3c2410_gpio_setpin(S3C2410_GPA0, 1); +} + +MACHINE_START(OSIRIS, "Simtec-OSIRIS") + /* Maintainer: Ben Dooks */ + .phys_ram = S3C2410_SDRAM_PA, + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = osiris_map_io, + .init_irq = s3c24xx_init_irq, + .timer = &s3c24xx_timer, +MACHINE_END -- cgit v1.2.3-18-g5258 From 766636cc3630ae3b9827e7b4b1f566572963f1ef Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 20 Mar 2006 17:10:03 +0000 Subject: [ARM] 3329/1: S3C24XX - fix time for osiris machine Patch from Ben Dooks Add selection for timer code for the Simtec Osiris Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/time.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c2410/time.c b/arch/arm/mach-s3c2410/time.c index 10a2976aefd..9d7b799ea4a 100644 --- a/arch/arm/mach-s3c2410/time.c +++ b/arch/arm/mach-s3c2410/time.c @@ -142,6 +142,12 @@ static struct irqaction s3c2410_timer_irq = { .handler = s3c2410_timer_interrupt, }; +#define use_tclk1_12() ( \ + machine_is_bast() || \ + machine_is_vr1000() || \ + machine_is_anubis() || \ + machine_is_osiris() ) + /* * Set up timer interrupt, and return the current time in seconds. * @@ -165,7 +171,7 @@ static void s3c2410_timer_setup (void) /* configure the system for whichever machine is in use */ - if (machine_is_bast() || machine_is_vr1000() || machine_is_anubis()) { + if (use_tclk1_12()) { /* timer is at 12MHz, scaler is 1 */ timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); tcnt = 12000000 / HZ; -- cgit v1.2.3-18-g5258 From 8e40a2f91c6e73726a75381e4438478eb5964cb7 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 20 Mar 2006 17:10:04 +0000 Subject: [ARM] 3330/1: S3C24XX - move UPLL to main clock Patch from Ben Dooks Move the UPLL clock registration to the central clock file, and add an enable method Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/clock.c | 38 ++++++++++++++++++++++++++++++++++- arch/arm/mach-s3c2410/s3c2440-clock.c | 19 +----------------- 2 files changed, 38 insertions(+), 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c index 08489efdaf0..aaada9e3d67 100644 --- a/arch/arm/mach-s3c2410/clock.c +++ b/arch/arm/mach-s3c2410/clock.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include @@ -200,6 +201,28 @@ EXPORT_SYMBOL(clk_round_rate); EXPORT_SYMBOL(clk_set_rate); EXPORT_SYMBOL(clk_get_parent); +/* base clock enable */ + +static int s3c24xx_upll_enable(struct clk *clk, int enable) +{ + unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); + unsigned long orig = clkslow; + + if (enable) + clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF; + else + clkslow |= S3C2410_CLKSLOW_UCLK_OFF; + + __raw_writel(clkslow, S3C2410_CLKSLOW); + + /* if we started the UPLL, then allow to settle */ + + if (enable && !(orig & S3C2410_CLKSLOW_UCLK_OFF)) + udelay(200); + + return 0; +} + /* base clocks */ static struct clk clk_xtal = { @@ -210,6 +233,14 @@ static struct clk clk_xtal = { .ctrlbit = 0, }; +static struct clk clk_upll = { + .name = "upll", + .id = -1, + .parent = NULL, + .enable = s3c24xx_upll_enable, + .ctrlbit = 0, +}; + static struct clk clk_f = { .name = "fclk", .id = -1, @@ -262,7 +293,7 @@ struct clk s3c24xx_uclk = { }; -/* clock definitions */ +/* standard clock definitions */ static struct clk init_clocks[] = { { @@ -396,6 +427,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, unsigned long hclk, unsigned long pclk) { + unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); struct clk *clkp = init_clocks; int ptr; @@ -406,6 +438,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, /* initialise the main system clocks */ clk_xtal.rate = xtal; + clk_upll.rate = s3c2410_get_pll(upllcon, xtal); clk_h.rate = hclk; clk_p.rate = pclk; @@ -439,6 +472,9 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, if (s3c24xx_register_clock(&clk_xtal) < 0) printk(KERN_ERR "failed to register master xtal\n"); + if (s3c24xx_register_clock(&clk_upll) < 0) + printk(KERN_ERR "failed to register upll clock\n"); + if (s3c24xx_register_clock(&clk_f) < 0) printk(KERN_ERR "failed to register cpu fclk\n"); diff --git a/arch/arm/mach-s3c2410/s3c2440-clock.c b/arch/arm/mach-s3c2410/s3c2440-clock.c index b557a2be8a0..2d0fa03a257 100644 --- a/arch/arm/mach-s3c2410/s3c2440-clock.c +++ b/arch/arm/mach-s3c2410/s3c2440-clock.c @@ -45,11 +45,6 @@ /* S3C2440 extended clock support */ -static struct clk s3c2440_clk_upll = { - .name = "upll", - .id = -1, -}; - static struct clk s3c2440_clk_cam = { .name = "camif", .id = -1, @@ -66,22 +61,11 @@ static struct clk s3c2440_clk_ac97 = { static int s3c2440_clk_add(struct sys_device *sysdev) { - unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); struct clk *clk_h; struct clk *clk_p; - struct clk *clk_xtal; - - clk_xtal = clk_get(NULL, "xtal"); - if (IS_ERR(clk_xtal)) { - printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n"); - return -EINVAL; - } - - s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate); - printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n", - print_mhz(s3c2440_clk_upll.rate), + printk("S3C2440: Clock Support, DVS %s\n", (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); clk_p = clk_get(NULL, "pclk"); @@ -97,7 +81,6 @@ static int s3c2440_clk_add(struct sys_device *sysdev) s3c24xx_register_clock(&s3c2440_clk_ac97); s3c24xx_register_clock(&s3c2440_clk_cam); - s3c24xx_register_clock(&s3c2440_clk_upll); clk_disable(&s3c2440_clk_ac97); clk_disable(&s3c2440_clk_cam); -- cgit v1.2.3-18-g5258 From d3468daab82d5195fe85322235896797d5581720 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 20 Mar 2006 17:10:04 +0000 Subject: [ARM] 3331/1: S3C24XX - add clk_set_parent() to clock code Patch from Ben Dooks Add clk_set_parent() call to clock code Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/clock.c | 18 ++++++++++++++++++ arch/arm/mach-s3c2410/clock.h | 2 ++ 2 files changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c index aaada9e3d67..773b7aec3e9 100644 --- a/arch/arm/mach-s3c2410/clock.c +++ b/arch/arm/mach-s3c2410/clock.c @@ -192,6 +192,23 @@ struct clk *clk_get_parent(struct clk *clk) return clk->parent; } +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = 0; + + if (IS_ERR(clk)) + return -EINVAL; + + mutex_lock(&clocks_mutex); + + if (clk->set_parent) + ret = (clk->set_parent)(clk, parent); + + mutex_unlock(&clocks_mutex); + + return ret; +} + EXPORT_SYMBOL(clk_get); EXPORT_SYMBOL(clk_put); EXPORT_SYMBOL(clk_enable); @@ -200,6 +217,7 @@ EXPORT_SYMBOL(clk_get_rate); EXPORT_SYMBOL(clk_round_rate); EXPORT_SYMBOL(clk_set_rate); EXPORT_SYMBOL(clk_get_parent); +EXPORT_SYMBOL(clk_set_parent); /* base clock enable */ diff --git a/arch/arm/mach-s3c2410/clock.h b/arch/arm/mach-s3c2410/clock.h index eb5c95d1e7f..c4f36f00649 100644 --- a/arch/arm/mach-s3c2410/clock.h +++ b/arch/arm/mach-s3c2410/clock.h @@ -19,7 +19,9 @@ struct clk { int usage; unsigned long rate; unsigned long ctrlbit; + int (*enable)(struct clk *, int enable); + int (*set_parent)(struct clk *c, struct clk *parent); }; /* other clocks which may be registered by board support */ -- cgit v1.2.3-18-g5258 From 3fc3e1c0640887f883c28330e9d35145d23b2696 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 20 Mar 2006 17:10:07 +0000 Subject: [ARM] 3333/1: S3C2XX - add dclk and clkout clock support Patch from Ben Dooks Add enable and set_parent calls for the dclk and clkout clocks. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/clock.c | 94 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 93 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c index 773b7aec3e9..e205a6316b0 100644 --- a/arch/arm/mach-s3c2410/clock.c +++ b/arch/arm/mach-s3c2410/clock.c @@ -45,6 +45,7 @@ #include #include +#include #include "clock.h" #include "cpu.h" @@ -285,24 +286,115 @@ static struct clk clk_p = { /* clocks that could be registered by external code */ +static int s3c24xx_dclk_enable(struct clk *clk, int enable) +{ + unsigned long dclkcon = __raw_readl(S3C2410_DCLKCON); + + if (enable) + dclkcon |= clk->ctrlbit; + else + dclkcon &= ~clk->ctrlbit; + + __raw_writel(dclkcon, S3C2410_DCLKCON); + + return 0; +} + +static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) +{ + unsigned long dclkcon; + unsigned int uclk; + + if (parent == &clk_upll) + uclk = 1; + else if (parent == &clk_p) + uclk = 0; + else + return -EINVAL; + + clk->parent = parent; + + dclkcon = __raw_readl(S3C2410_DCLKCON); + + if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) { + if (uclk) + dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK; + else + dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK; + } else { + if (uclk) + dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK; + else + dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK; + } + + __raw_writel(dclkcon, S3C2410_DCLKCON); + + return 0; +} + + +static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) +{ + unsigned long mask; + unsigned long source; + + /* calculate the MISCCR setting for the clock */ + + if (parent == &clk_xtal) + source = S3C2410_MISCCR_CLK0_MPLL; + else if (parent == &clk_upll) + source = S3C2410_MISCCR_CLK0_UPLL; + else if (parent == &clk_f) + source = S3C2410_MISCCR_CLK0_FCLK; + else if (parent == &clk_p) + source = S3C2410_MISCCR_CLK0_PCLK; + else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) + source = S3C2410_MISCCR_CLK0_DCLK0; + else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) + source = S3C2410_MISCCR_CLK0_DCLK0; + else + return -EINVAL; + + if (clk == &s3c24xx_dclk0) + mask = S3C2410_MISCCR_CLK0_MASK; + else { + source <<= 4; + mask = S3C2410_MISCCR_CLK1_MASK; + } + + s3c2410_modify_misccr(mask, source); + return 0; +} + +/* external clock definitions */ + struct clk s3c24xx_dclk0 = { .name = "dclk0", .id = -1, + .ctrlbit = S3C2410_DCLKCON_DCLK0EN, + .enable = s3c24xx_dclk_enable, + .set_parent = s3c24xx_dclk_setparent, }; struct clk s3c24xx_dclk1 = { .name = "dclk1", .id = -1, + .ctrlbit = S3C2410_DCLKCON_DCLK0EN, + .enable = s3c24xx_dclk_enable, + .set_parent = s3c24xx_dclk_setparent, }; struct clk s3c24xx_clkout0 = { .name = "clkout0", .id = -1, + .set_parent = s3c24xx_clkout_setparent, }; struct clk s3c24xx_clkout1 = { .name = "clkout1", .id = -1, + .set_parent = s3c24xx_clkout_setparent, }; struct clk s3c24xx_uclk = { @@ -423,7 +515,7 @@ int s3c24xx_register_clock(struct clk *clk) /* if this is a standard clock, set the usage state */ - if (clk->ctrlbit) { + if (clk->ctrlbit && clk->enable == s3c24xx_clkcon_enable) { unsigned long clkcon = __raw_readl(S3C2410_CLKCON); clk->usage = (clkcon & clk->ctrlbit) ? 1 : 0; -- cgit v1.2.3-18-g5258 From 0328ad23cfd8a0501f44a1b83e49d5b0e47e2b3c Mon Sep 17 00:00:00 2001 From: Deepak Saxena Date: Mon, 20 Mar 2006 17:10:08 +0000 Subject: [ARM] 3334/1: Add support for IXDP28x5 platforms Patch from Deepak Saxena This patch adds support for Intel's IXDP28x5 platform. This is just and IXDP2801 with a new CPU rev but the bootloader has been updated to reflect a new machine ID so we just build support for it by default when we build IXDP2801. Signed-off-by: Deepak Saxena Signed-off-by: Russell King --- arch/arm/mach-ixp2000/Kconfig | 9 +++++++-- arch/arm/mach-ixp2000/ixdp2x01.c | 20 ++++++++++++++++++-- 2 files changed, 25 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ixp2000/Kconfig b/arch/arm/mach-ixp2000/Kconfig index ecb58d83478..86f53f8ccbf 100644 --- a/arch/arm/mach-ixp2000/Kconfig +++ b/arch/arm/mach-ixp2000/Kconfig @@ -43,12 +43,17 @@ config ARCH_IXDP2401 this platform, see . config ARCH_IXDP2801 - bool "Support Intel IXDP2801" + bool "Support Intel IXDP2801 and IXDP28x5" help Say 'Y' here if you want your kernel to support the Intel - IXDP2801 reference platform. For more information on + IXDP2801/2805/2855 reference platforms. For more information on this platform, see . +config MACH_IXDP28X5 + bool + depends on ARCH_IXDP2801 + default y + config ARCH_IXDP2X01 bool depends on ARCH_IXDP2401 || ARCH_IXDP2801 diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 150519fb38e..f9d4968c1d6 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -284,7 +284,7 @@ static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys) { sys->mem_offset = 0xe0000000; - if (machine_is_ixdp2801()) + if (machine_is_ixdp2801() || machine_is_ixdp28x5()) sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16); return ixp2000_pci_setup(nr, sys); @@ -300,7 +300,8 @@ struct hw_pci ixdp2x01_pci __initdata = { int __init ixdp2x01_pci_init(void) { - if (machine_is_ixdp2401() || machine_is_ixdp2801()) + if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\ + machine_is_ixdp28x5()) pci_common_init(&ixdp2x01_pci); return 0; @@ -400,6 +401,21 @@ MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform") .timer = &ixdp2x01_timer, .init_machine = ixdp2x01_init_machine, MACHINE_END + +/* + * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel + * changed the machine ID in the bootloader + */ +MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform") + /* Maintainer: MontaVista Software, Inc. */ + .phys_io = IXP2000_UART_PHYS_BASE, + .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = ixdp2x01_map_io, + .init_irq = ixdp2x01_init_irq, + .timer = &ixdp2x01_timer, + .init_machine = ixdp2x01_init_machine, +MACHINE_END #endif -- cgit v1.2.3-18-g5258 From 6d4518d76f9612d580f9423cc0c3364a06b69588 Mon Sep 17 00:00:00 2001 From: Peter Teichmann Date: Mon, 20 Mar 2006 17:10:09 +0000 Subject: [ARM] 3346/1: Fix udelay() for HZ values different from 100 Patch from Peter Teichmann Currently, if the kernels HZ value is greater than 100, delays with the udelay function are too short. This can cause trouble for instance with the zd1201 usb wlan driver. This patch suggests a solution that keeps the overhead small and maintains (hopefully) sufficient resolution. Signed-off-by: Peter Teichmann Signed-off-by: Russell King --- arch/arm/lib/delay.S | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/lib/delay.S b/arch/arm/lib/delay.S index b3fb475b412..9183b06c0e2 100644 --- a/arch/arm/lib/delay.S +++ b/arch/arm/lib/delay.S @@ -9,28 +9,32 @@ */ #include #include +#include .text .LC0: .word loops_per_jiffy +.LC1: .word (2199023*HZ)>>11 /* - * 0 <= r0 <= 2000 + * r0 <= 2000 + * lpj <= 0x01ffffff (max. 3355 bogomips) + * HZ <= 1000 */ + ENTRY(__udelay) - mov r2, #0x6800 - orr r2, r2, #0x00db + ldr r2, .LC1 mul r0, r2, r0 -ENTRY(__const_udelay) @ 0 <= r0 <= 0x01ffffff +ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06 ldr r2, .LC0 - ldr r2, [r2] @ max = 0x0fffffff - mov r0, r0, lsr #11 @ max = 0x00003fff - mov r2, r2, lsr #11 @ max = 0x0003ffff + ldr r2, [r2] @ max = 0x01ffffff + mov r0, r0, lsr #14 @ max = 0x0001ffff + mov r2, r2, lsr #10 @ max = 0x00007fff mul r0, r2, r0 @ max = 2^32-1 movs r0, r0, lsr #6 RETINSTR(moveq,pc,lr) /* - * loops = (r0 * 0x10c6 * 100 * loops_per_jiffy) / 2^32 + * loops = r0 * HZ * loops_per_jiffy / 1000000 * * Oh, if only we had a cycle counter... */ -- cgit v1.2.3-18-g5258 From 73deb7dc05b4cf968e506e7b18345bc65bcbc0f3 Mon Sep 17 00:00:00 2001 From: Alessandro Zummo Date: Mon, 20 Mar 2006 17:10:12 +0000 Subject: [ARM] 3368/1: ixp4xx: set gpio direction in ixp4xx_config_irq Patch from Alessandro Zummo ixp4xx_config_irq did not configure the gpio line as an input. As an added bonus, the irq2gpio array has been converted from int to char. Signed-off-by: Alessandro Zummo Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/common.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index fbadf3021b9..a0888e160e3 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -91,7 +91,7 @@ static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type); /* * IRQ -> GPIO mapping table */ -static int irq2gpio[32] = { +static char irq2gpio[32] = { -1, -1, -1, -1, -1, -1, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, 3, 4, 5, 6, @@ -153,6 +153,9 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) /* Set the new style */ *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); + /* Configure the line as an input */ + gpio_line_config(line, IXP4XX_GPIO_IN); + return 0; } -- cgit v1.2.3-18-g5258 From e7736d47a11a771ba87314be563b2cb6b8d11d14 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 20 Mar 2006 17:10:13 +0000 Subject: [ARM] 3369/1: ep93xx: add core cirrus ep93xx support Patch from Lennert Buytenhek This patch adds support for the Cirrus ep93xx series of CPUs. The ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs, IrDA, MaverickCrunch floating point coprocessor, between 24 and 64 GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster engine, graphics accelerator, IDE controller and a bunch of other stuff. This patch adds the core ep93xx support code, and support for the Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/Kconfig | 9 ++ arch/arm/Makefile | 1 + arch/arm/mach-ep93xx/Kconfig | 21 +++++ arch/arm/mach-ep93xx/Makefile | 10 +++ arch/arm/mach-ep93xx/Makefile.boot | 2 + arch/arm/mach-ep93xx/core.c | 173 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-ep93xx/gesbc9312.c | 40 +++++++++ arch/arm/mach-ep93xx/ts72xx.c | 118 +++++++++++++++++++++++++ arch/arm/mm/Kconfig | 2 +- 9 files changed, 375 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-ep93xx/Kconfig create mode 100644 arch/arm/mach-ep93xx/Makefile create mode 100644 arch/arm/mach-ep93xx/Makefile.boot create mode 100644 arch/arm/mach-ep93xx/core.c create mode 100644 arch/arm/mach-ep93xx/gesbc9312.c create mode 100644 arch/arm/mach-ep93xx/ts72xx.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6e9e8cedd72..0dd24ebdf6a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -108,6 +108,13 @@ config ARCH_EBSA110 Ethernet interface, two PCMCIA sockets, two serial ports and a parallel port. +config ARCH_EP93XX + bool "EP93xx-based" + select A