From 367afaf83b0a8886ea566638a865701c54710af9 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 20 Jul 2007 11:42:51 +0100 Subject: [ARM] 4501/1: nommu: Select TLS register emulation if ARMv6 and not v6K If not MMU and not v6K, access to the TLS register has to be emulated. MMU-less systems do not provide a high page for kuser helpers. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mm/Kconfig') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index e7904bc92c7..cccacd9c95a 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -405,6 +405,7 @@ config CPU_32v5 config CPU_32v6 bool + select TLS_REG_EMUL if !CPU_32v6K && !MMU config CPU_32v7 bool -- cgit v1.2.3-18-g5258 From 7b4c965a0b74748269d05185a394c9dc121dd558 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 20 Jul 2007 11:42:57 +0100 Subject: [ARM] 4504/1: nommu: Fix the ARMv6 support for MMU-less platforms With this patch, Kconfig only selects CPU_HAS_ASID for the MMU case. It also corrects the typo in the v6wbi_tlb_fns definition in pgtable-nommu.h. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mm/Kconfig') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index cccacd9c95a..d377376d6ee 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -351,7 +351,7 @@ config CPU_V6 select CPU_CACHE_V6 select CPU_CACHE_VIPT select CPU_CP15_MMU - select CPU_HAS_ASID + select CPU_HAS_ASID if MMU select CPU_COPY_V6 if MMU select CPU_TLB_V6 if MMU -- cgit v1.2.3-18-g5258 From 7092fc38ee770251aed361572bf6bed05fcf3ee2 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 20 Jul 2007 11:42:29 +0100 Subject: [ARM] 4498/1: ARMv7: Remove the L2 cache configuration via the aux ctrl register The auxiliary control and the L2 auxiliary control registers are Cortex-A8 specific. They need to be removed from the generic ARMv7 support code. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm/mm/Kconfig') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index d377376d6ee..7cc32b70711 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -612,12 +612,6 @@ config CPU_CACHE_ROUND_ROBIN Say Y here to use the predictable round-robin cache replacement policy. Unless you specifically require this or are unsure, say N. -config CPU_L2CACHE_DISABLE - bool "Disable level 2 cache" - depends on CPU_V7 - help - Say Y here to disable the level 2 cache. If unsure, say N. - config CPU_BPREDICT_DISABLE bool "Disable branch prediction" depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 -- cgit v1.2.3-18-g5258 From 2eb8c82bc492d5f185150e63eba5eac4dff24178 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 20 Jul 2007 11:43:02 +0100 Subject: [ARM] 4503/1: nommu: Add noMMU support for ARMv7 This patch adds the necessary ifdef's to the proc-v7.S code and defines the v7wbi_tlb_fns macro in pgtable-nommu.h Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mm/Kconfig') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 7cc32b70711..58109ae3470 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -377,7 +377,7 @@ config CPU_V7 select CPU_CACHE_V7 select CPU_CACHE_VIPT select CPU_CP15_MMU - select CPU_HAS_ASID + select CPU_HAS_ASID if MMU select CPU_COPY_V6 if MMU select CPU_TLB_V7 if MMU -- cgit v1.2.3-18-g5258 From 11179d8ca28d669e3d4cc7573a5f5fdda3e6f02d Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 20 Jul 2007 11:42:24 +0100 Subject: [ARM] 4497/1: Only allow safe cache configurations on ARMv6 and later Currently, Linux doesn't generate correct page tables for ARMv6 and later cores if the cache policy is different from the default one (it may lead to strongly ordered or shared device mappings). This patch disallows cache policies other than writeback and the CPU_[ID]CACHE_DISABLE options only affect the CP15 system control register rather than the page tables. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mm/Kconfig') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 58109ae3470..76a3ba668e2 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -599,7 +599,7 @@ config CPU_DCACHE_SIZE config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" - depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE + depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you -- cgit v1.2.3-18-g5258 From 52c543f90c4095dff71dc125017594b61a753069 Mon Sep 17 00:00:00 2001 From: Quinn Jensen Date: Mon, 9 Jul 2007 22:06:53 +0100 Subject: [ARM] 4461/1: MXC platform and i.MX31ADS core support This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen Acked-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm/mm/Kconfig') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index e7904bc92c7..699b899214a 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -345,7 +345,8 @@ config CPU_XSC3 # ARMv6 config CPU_V6 bool "Support ARM V6 processor" - depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 + depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 + default y if ARCH_MX3 select CPU_32v6 select CPU_ABRT_EV6 select CPU_CACHE_V6 @@ -359,7 +360,7 @@ config CPU_V6 config CPU_32v6K bool "Support ARM V6K processor extensions" if !SMP depends on CPU_V6 - default y if SMP + default y if SMP && !ARCH_MX3 help Say Y here if your ARMv6 processor supports the 'K' extension. This enables the kernel to use some instructions not present -- cgit v1.2.3-18-g5258