From 911bd7395c4aa4e74b13aab790ca1500c59fae02 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 8 Dec 2009 18:47:17 -0700 Subject: ARM: OMAP4: PM: Add init api for DPLL nodes An api at init for all dpll nodes seem to be needed to reparent the dpll clk node to its bypass clk in case the dpll is in bypass. If not done this causes sequencing issues at init during propogate_rate. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley Cc: Benoit Cousson --- arch/arm/mach-omap2/clock.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 61ee23596ea..759c72a48f7 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -70,9 +70,41 @@ u8 cpu_mask; /*------------------------------------------------------------------------- - * OMAP2/3 specific clock functions + * OMAP2/3/4 specific clock functions *-------------------------------------------------------------------------*/ +void omap2_init_dpll_parent(struct clk *clk) +{ + u32 v; + struct dpll_data *dd; + + dd = clk->dpll_data; + if (!dd) + return; + + /* Return bypass rate if DPLL is bypassed */ + v = __raw_readl(dd->control_reg); + v &= dd->enable_mask; + v >>= __ffs(dd->enable_mask); + + /* Reparent in case the dpll is in bypass */ + if (cpu_is_omap24xx()) { + if (v == OMAP2XXX_EN_DPLL_LPBYPASS || + v == OMAP2XXX_EN_DPLL_FRBYPASS) + clk_reparent(clk, dd->clk_bypass); + } else if (cpu_is_omap34xx()) { + if (v == OMAP3XXX_EN_DPLL_LPBYPASS || + v == OMAP3XXX_EN_DPLL_FRBYPASS) + clk_reparent(clk, dd->clk_bypass); + } else if (cpu_is_omap44xx()) { + if (v == OMAP4XXX_EN_DPLL_LPBYPASS || + v == OMAP4XXX_EN_DPLL_FRBYPASS || + v == OMAP4XXX_EN_DPLL_MNBYPASS) + clk_reparent(clk, dd->clk_bypass); + } + return; +} + /** * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware * @clk: struct clk * -- cgit v1.2.3-18-g5258