From ebf30dc91cc8592cd72b004219cfc276b3ad2854 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 31 May 2011 16:10:00 -0700 Subject: msm: timer: Fix SMP build error Fix build breakage on SMP=y builds due to 0f7b332 (ARM: consolidate SMP cross call implementation, 2011-04-03) arch/arm/mach-msm/timer.c: In function 'local_timer_setup': arch/arm/mach-msm/timer.c:295: error: implicit declaration of function 'gic_enable_ppi' Signed-off-by: Stephen Boyd Signed-off-by: David Brown --- arch/arm/mach-msm/timer.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-msm') diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 38b95e949d1..9bfdd5ad244 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -23,6 +23,8 @@ #include #include +#include + #include #include -- cgit v1.2.3-18-g5258 From 650f156775c2638cc02ed7df31186a09ba79666a Mon Sep 17 00:00:00 2001 From: Jeff Ohlstein Date: Fri, 17 Jun 2011 13:55:38 -0700 Subject: msm: timer: compensate for timer shift in msm_read_timer_count Some msm targets have timers whose lower bits are unreliable. So, we present our timers as lower frequency than they actually are, and ignore the bottom 5 bits on such targets. This compensation was erroneously removed from the msm_read_timer_count function, so restore it. This was broken by 94790ec25 "msm: timer: SMP timer support for msm". Signed-off-by: Jeff Ohlstein --- arch/arm/mach-msm/timer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-msm') diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 9bfdd5ad244..2232032181b 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -102,7 +102,11 @@ static cycle_t msm_read_timer_count(struct clocksource *cs) { struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource); - return readl(clk->global_counter); + /* + * Shift timer count down by a constant due to unreliable lower bits + * on some targets. + */ + return readl(clk->global_counter) >> clk->shift; } static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt) -- cgit v1.2.3-18-g5258 From fdb9c3cd5124c9a6e4c824ed2bca5b4602e84a1a Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 21 Apr 2011 23:09:11 +0000 Subject: msm: timer: Fix DGT rate on 8960 and 8660 The DGT runs at 27 MHz divided by 4 on 8660 and 8960. Signed-off-by: Stephen Boyd Signed-off-by: David Brown --- arch/arm/mach-msm/timer.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-msm') diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 2232032181b..63621f152c9 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -57,10 +57,12 @@ enum timer_location { #if defined(CONFIG_ARCH_QSD8X50) #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ #define MSM_DGT_SHIFT (0) -#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \ - defined(CONFIG_ARCH_MSM8960) +#elif defined(CONFIG_ARCH_MSM7X30) #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */ #define MSM_DGT_SHIFT (0) +#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960) +#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */ +#define MSM_DGT_SHIFT (0) #else #define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */ #define MSM_DGT_SHIFT (5) -- cgit v1.2.3-18-g5258 From 7fa22bd5460bb2021729fa5a1012c60b9b3a56e2 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 7 Jul 2011 01:56:51 +0100 Subject: ARM: 6993/1: platsmp: Allow secondary cpu hotplug with maxcpus=1 If an ARM system has multiple cpus in the same socket and the kernel is booted with maxcpus=1, secondary cpus are possible but not present due to how platform_smp_prepare_cpus() is called. Since most typical ARM processors don't actually support physical hotplug, initialize the present map to be equal to the possible map in generic ARM SMP code. Also, always call platform_smp_prepare_cpus() as long as max_cpus is non-zero (0 means no SMP) to allow platform code to do any SMP setup. After applying this patch it's possible to boot an ARM system with maxcpus=1 on the command line and then hotplug in secondary cpus via sysfs. This is more in line with how x86 does things. Signed-off-by: Stephen Boyd Cc: Paul Mundt Cc: Kukjin Kim Cc: David Brown Cc: Tony Lindgren Cc: Srinidhi Kasagar Cc: Linus Walleij Signed-off-by: Russell King --- arch/arm/mach-msm/platsmp.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch/arm/mach-msm') diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 2034098cf01..315b9f36532 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -157,12 +157,4 @@ void __init smp_init_cpus(void) void __init platform_smp_prepare_cpus(unsigned int max_cpus) { - int i; - - /* - * Initialise the present map, which describes the set of CPUs - * actually populated at the present time. - */ - for (i = 0; i < max_cpus; i++) - set_cpu_present(i, true); } -- cgit v1.2.3-18-g5258