From 651c74c74bf84ba966b52588ba3329606f3fd8d4 Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Sun, 22 Jun 2008 22:45:06 +0200 Subject: [ARM] add Marvell Kirkwood (88F6000) SoC support The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface, a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS interface, and IDMA/XOR engines, and depending on the model, also features one or two Gigabit Ethernet interfaces, two SATA II interfaces, one or two TWSI interfaces, one or two UARTs, a TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and an SDIO interface. This patch adds supports for the Marvell DB-88F6281-BP Development Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs, enabling support for the PCIe interface, the USB interface, the ethernet interfaces, the SATA interfaces, the TWSI interfaces, the UARTs, and the NAND controller. Signed-off-by: Saeed Bishara Signed-off-by: Lennert Buytenhek --- arch/arm/mach-kirkwood/Kconfig | 25 ++ arch/arm/mach-kirkwood/Makefile | 5 + arch/arm/mach-kirkwood/Makefile.boot | 3 + arch/arm/mach-kirkwood/addr-map.c | 139 ++++++++++++ arch/arm/mach-kirkwood/common.c | 326 +++++++++++++++++++++++++++ arch/arm/mach-kirkwood/common.h | 42 ++++ arch/arm/mach-kirkwood/db88f6281-bp-setup.c | 68 ++++++ arch/arm/mach-kirkwood/irq.c | 22 ++ arch/arm/mach-kirkwood/pcie.c | 180 +++++++++++++++ arch/arm/mach-kirkwood/rd88f6192-nas-setup.c | 69 ++++++ arch/arm/mach-kirkwood/rd88f6281-setup.c | 112 +++++++++ 11 files changed, 991 insertions(+) create mode 100644 arch/arm/mach-kirkwood/Kconfig create mode 100644 arch/arm/mach-kirkwood/Makefile create mode 100644 arch/arm/mach-kirkwood/Makefile.boot create mode 100644 arch/arm/mach-kirkwood/addr-map.c create mode 100644 arch/arm/mach-kirkwood/common.c create mode 100644 arch/arm/mach-kirkwood/common.h create mode 100644 arch/arm/mach-kirkwood/db88f6281-bp-setup.c create mode 100644 arch/arm/mach-kirkwood/irq.c create mode 100644 arch/arm/mach-kirkwood/pcie.c create mode 100644 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c create mode 100644 arch/arm/mach-kirkwood/rd88f6281-setup.c (limited to 'arch/arm/mach-kirkwood') diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig new file mode 100644 index 00000000000..3600cd9f051 --- /dev/null +++ b/arch/arm/mach-kirkwood/Kconfig @@ -0,0 +1,25 @@ +if ARCH_KIRKWOOD + +menu "Marvell Kirkwood Implementations" + +config MACH_DB88F6281_BP + bool "Marvell DB-88F6281-BP Development Board" + help + Say 'Y' here if you want your kernel to support the + Marvell DB-88F6281-BP Development Board. + +config MACH_RD88F6192_NAS + bool "Marvell RD-88F6192-NAS Reference Board" + help + Say 'Y' here if you want your kernel to support the + Marvell RD-88F6192-NAS Reference Board. + +config MACH_RD88F6281 + bool "Marvell RD-88F6281 Reference Board" + help + Say 'Y' here if you want your kernel to support the + Marvell RD-88F6281 Reference Board. + +endmenu + +endif diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile new file mode 100644 index 00000000000..e14bf40bfb0 --- /dev/null +++ b/arch/arm/mach-kirkwood/Makefile @@ -0,0 +1,5 @@ +obj-y += common.o addr-map.o irq.o pcie.o + +obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o +obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o +obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6281-setup.o diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot new file mode 100644 index 00000000000..67039c3e0c4 --- /dev/null +++ b/arch/arm/mach-kirkwood/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c new file mode 100644 index 00000000000..a39f0f3c473 --- /dev/null +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -0,0 +1,139 @@ +/* + * arch/arm/mach-kirkwood/addr-map.c + * + * Address map functions for Marvell Kirkwood SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include "common.h" + +/* + * Generic Address Decode Windows bit settings + */ +#define TARGET_DDR 0 +#define TARGET_DEV_BUS 1 +#define TARGET_PCIE 4 +#define ATTR_DEV_SPI_ROM 0x1e +#define ATTR_DEV_BOOT 0x1d +#define ATTR_DEV_NAND 0x2f +#define ATTR_DEV_CS3 0x37 +#define ATTR_DEV_CS2 0x3b +#define ATTR_DEV_CS1 0x3d +#define ATTR_DEV_CS0 0x3e +#define ATTR_PCIE_IO 0xe0 +#define ATTR_PCIE_MEM 0xe8 + +/* + * Helpers to get DDR bank info + */ +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) + +/* + * CPU Address Decode Windows registers + */ +#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) +#define WIN_CTRL_OFF 0x0000 +#define WIN_BASE_OFF 0x0004 +#define WIN_REMAP_LO_OFF 0x0008 +#define WIN_REMAP_HI_OFF 0x000c + + +struct mbus_dram_target_info kirkwood_mbus_dram_info; + +static int __init cpu_win_can_remap(int win) +{ + if (win < 4) + return 1; + + return 0; +} + +static void __init setup_cpu_win(int win, u32 base, u32 size, + u8 target, u8 attr, int remap) +{ + void __iomem *addr = (void __iomem *)WIN_OFF(win); + u32 ctrl; + + base &= 0xffff0000; + ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; + + writel(base, addr + WIN_BASE_OFF); + writel(ctrl, addr + WIN_CTRL_OFF); + if (cpu_win_can_remap(win)) { + if (remap < 0) + remap = base; + + writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } +} + +void __init kirkwood_setup_cpu_mbus(void) +{ + void __iomem *addr; + int i; + int cs; + + /* + * First, disable and clear windows. + */ + for (i = 0; i < 8; i++) { + addr = (void __iomem *)WIN_OFF(i); + + writel(0, addr + WIN_BASE_OFF); + writel(0, addr + WIN_CTRL_OFF); + if (cpu_win_can_remap(i)) { + writel(0, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } + } + + /* + * Setup windows for PCIe IO+MEM space. + */ + setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); + setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE_MEM, -1); + + /* + * Setup window for NAND controller. + */ + setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, + TARGET_DEV_BUS, ATTR_DEV_NAND, -1); + + /* + * Setup MBUS dram target info. + */ + kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + addr = (void __iomem *)DDR_WINDOW_CPU_BASE; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(addr + DDR_BASE_CS_OFF(i)); + u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); + + /* + * Chip select enabled? + */ + if (size & 1) { + struct mbus_dram_window *w; + + w = &kirkwood_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); + w->base = base & 0xffff0000; + w->size = (size | 0x0000ffff) + 1; + } + } + kirkwood_mbus_dram_info.num_cs = cs; +} diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c new file mode 100644 index 00000000000..e73384fbbba --- /dev/null +++ b/arch/arm/mach-kirkwood/common.c @@ -0,0 +1,326 @@ +/* + * arch/arm/mach-kirkwood/common.c + * + * Core functions for Marvell Kirkwood SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * I/O Address Mapping + ****************************************************************************/ +static struct map_desc kirkwood_io_desc[] __initdata = { + { + .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, + .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), + .length = KIRKWOOD_PCIE_IO_SIZE, + .type = MT_DEVICE, + }, { + .virtual = KIRKWOOD_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), + .length = KIRKWOOD_REGS_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init kirkwood_map_io(void) +{ + iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); +} + + +/***************************************************************************** + * EHCI + ****************************************************************************/ +static struct orion_ehci_data kirkwood_ehci_data = { + .dram = &kirkwood_mbus_dram_info, +}; + +static u64 ehci_dmamask = 0xffffffffUL; + + +/***************************************************************************** + * EHCI0 + ****************************************************************************/ +static struct resource kirkwood_ehci_resources[] = { + { + .start = USB_PHYS_BASE, + .end = USB_PHYS_BASE + 0x0fff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_KIRKWOOD_USB, + .end = IRQ_KIRKWOOD_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_ehci = { + .name = "orion-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &kirkwood_ehci_data, + }, + .resource = kirkwood_ehci_resources, + .num_resources = ARRAY_SIZE(kirkwood_ehci_resources), +}; + +void __init kirkwood_ehci_init(void) +{ + platform_device_register(&kirkwood_ehci); +} + + +/***************************************************************************** + * GE00 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = { + .t_clk = KIRKWOOD_TCLK, + .dram = &kirkwood_mbus_dram_info, +}; + +static struct resource kirkwood_ge00_shared_resources[] = { + { + .name = "ge00 base", + .start = GE00_PHYS_BASE + 0x2000, + .end = GE00_PHYS_BASE + 0x3fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device kirkwood_ge00_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &kirkwood_ge00_shared_data, + }, + .num_resources = 1, + .resource = kirkwood_ge00_shared_resources, +}; + +static struct resource kirkwood_ge00_resources[] = { + { + .name = "ge00 irq", + .start = IRQ_KIRKWOOD_GE00_SUM, + .end = IRQ_KIRKWOOD_GE00_SUM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_ge00 = { + .name = MV643XX_ETH_NAME, + .id = 0, + .num_resources = 1, + .resource = kirkwood_ge00_resources, +}; + +void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) +{ + eth_data->shared = &kirkwood_ge00_shared; + kirkwood_ge00.dev.platform_data = eth_data; + + platform_device_register(&kirkwood_ge00_shared); + platform_device_register(&kirkwood_ge00); +} + + +/***************************************************************************** + * SoC RTC + ****************************************************************************/ +static struct resource kirkwood_rtc_resource = { + .start = RTC_PHYS_BASE, + .end = RTC_PHYS_BASE + SZ_16 - 1, + .flags = IORESOURCE_MEM, +}; + +void __init kirkwood_rtc_init(void) +{ + platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1); +} + + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct resource kirkwood_sata_resources[] = { + { + .name = "sata base", + .start = SATA_PHYS_BASE, + .end = SATA_PHYS_BASE + 0x5000 - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "sata irq", + .start = IRQ_KIRKWOOD_SATA, + .end = IRQ_KIRKWOOD_SATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_sata = { + .name = "sata_mv", + .id = 0, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(kirkwood_sata_resources), + .resource = kirkwood_sata_resources, +}; + +void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) +{ + sata_data->dram = &kirkwood_mbus_dram_info; + kirkwood_sata.dev.platform_data = sata_data; + platform_device_register(&kirkwood_sata); +} + + +/***************************************************************************** + * UART0 + ****************************************************************************/ +static struct plat_serial8250_port kirkwood_uart0_data[] = { + { + .mapbase = UART0_PHYS_BASE, + .membase = (char *)UART0_VIRT_BASE, + .irq = IRQ_KIRKWOOD_UART_0, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = KIRKWOOD_TCLK, + }, { + }, +}; + +static struct resource kirkwood_uart0_resources[] = { + { + .start = UART0_PHYS_BASE, + .end = UART0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_KIRKWOOD_UART_0, + .end = IRQ_KIRKWOOD_UART_0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_uart0 = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = kirkwood_uart0_data, + }, + .resource = kirkwood_uart0_resources, + .num_resources = ARRAY_SIZE(kirkwood_uart0_resources), +}; + +void __init kirkwood_uart0_init(void) +{ + platform_device_register(&kirkwood_uart0); +} + + +/***************************************************************************** + * UART1 + ****************************************************************************/ +static struct plat_serial8250_port kirkwood_uart1_data[] = { + { + .mapbase = UART1_PHYS_BASE, + .membase = (char *)UART1_VIRT_BASE, + .irq = IRQ_KIRKWOOD_UART_1, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = KIRKWOOD_TCLK, + }, { + }, +}; + +static struct resource kirkwood_uart1_resources[] = { + { + .start = UART1_PHYS_BASE, + .end = UART1_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_KIRKWOOD_UART_1, + .end = IRQ_KIRKWOOD_UART_1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_uart1 = { + .name = "serial8250", + .id = 1, + .dev = { + .platform_data = kirkwood_uart1_data, + }, + .resource = kirkwood_uart1_resources, + .num_resources = ARRAY_SIZE(kirkwood_uart1_resources), +}; + +void __init kirkwood_uart1_init(void) +{ + platform_device_register(&kirkwood_uart1); +} + + +/***************************************************************************** + * Time handling + ****************************************************************************/ +static void kirkwood_timer_init(void) +{ + orion_time_init(IRQ_KIRKWOOD_BRIDGE, KIRKWOOD_TCLK); +} + +struct sys_timer kirkwood_timer = { + .init = kirkwood_timer_init, +}; + + +/***************************************************************************** + * General + ****************************************************************************/ +static char * __init kirkwood_id(void) +{ + switch (readl(DEVICE_ID) & 0x3) { + case 0: + return "88F6180"; + case 1: + return "88F6192"; + case 2: + return "88F6281"; + } + + return "unknown 88F6000 variant"; +} + +void __init kirkwood_init(void) +{ + printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", + kirkwood_id(), KIRKWOOD_TCLK); + + kirkwood_setup_cpu_mbus(); + +#ifdef CONFIG_CACHE_FEROCEON_L2 + feroceon_l2_init(1); +#endif +} diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h new file mode 100644 index 00000000000..5dee2f6b40a --- /dev/null +++ b/arch/arm/mach-kirkwood/common.h @@ -0,0 +1,42 @@ +/* + * arch/arm/mach-kirkwood/common.h + * + * Core functions for Marvell Kirkwood SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_KIRKWOOD_COMMON_H +#define __ARCH_KIRKWOOD_COMMON_H + +struct mv643xx_eth_platform_data; +struct mv_sata_platform_data; + +/* + * Basic Kirkwood init functions used early by machine-setup. + */ +void kirkwood_map_io(void); +void kirkwood_init(void); +void kirkwood_init_irq(void); + +extern struct mbus_dram_target_info kirkwood_mbus_dram_info; +void kirkwood_setup_cpu_mbus(void); +void kirkwood_setup_pcie_io_win(int window, u32 base, u32 size, + int maj, int min); +void kirkwood_setup_pcie_mem_win(int window, u32 base, u32 size, + int maj, int min); + +void kirkwood_ehci_init(void); +void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data); +void kirkwood_pcie_init(void); +void kirkwood_rtc_init(void); +void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); +void kirkwood_uart0_init(void); +void kirkwood_uart1_init(void); + +extern struct sys_timer kirkwood_timer; + + +#endif diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c new file mode 100644 index 00000000000..d5c482c628e --- /dev/null +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c @@ -0,0 +1,68 @@ +/* + * arch/arm/mach-kirkwood/db88f6281-bp-setup.c + * + * Marvell DB-88F6281-BP Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +static struct mv643xx_eth_platform_data db88f6281_ge00_data = { + .phy_addr = 8, +}; + +static struct mv_sata_platform_data db88f6281_sata_data = { + .n_ports = 2, +}; + +static void __init db88f6281_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + + kirkwood_ehci_init(); + kirkwood_ge00_init(&db88f6281_ge00_data); + kirkwood_rtc_init(); + kirkwood_sata_init(&db88f6281_sata_data); + kirkwood_uart0_init(); + kirkwood_uart1_init(); +} + +static int __init db88f6281_pci_init(void) +{ + if (machine_is_db88f6281_bp()) + kirkwood_pcie_init(); + + return 0; +} +subsys_initcall(db88f6281_pci_init); + +MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board") + /* Maintainer: Saeed Bishara */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = db88f6281_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c new file mode 100644 index 00000000000..302bb2cf666 --- /dev/null +++ b/arch/arm/mach-kirkwood/irq.c @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-kirkwood/irq.c + * + * Kirkwood IRQ handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include "common.h" + +void __init kirkwood_init_irq(void) +{ + orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); + orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); +} diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c new file mode 100644 index 00000000000..8282d0ff84b --- /dev/null +++ b/arch/arm/mach-kirkwood/pcie.c @@ -0,0 +1,180 @@ +/* + * arch/arm/mach-kirkwood/pcie.c + * + * PCIe functions for Marvell Kirkwood SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include "common.h" + + +#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE) + +static int pcie_valid_config(int bus, int dev) +{ + /* + * Don't go out when trying to access -- + * 1. nonexisting device on local bus + * 2. where there's no device connected (no link) + */ + if (bus == 0 && dev == 0) + return 1; + + if (!orion_pcie_link_up(PCIE_BASE)) + return 0; + + if (bus == 0 && dev != 1) + return 0; + + return 1; +} + + +/* + * PCIe config cycles are done by programming the PCIE_CONF_ADDR register + * and then reading the PCIE_CONF_DATA register. Need to make sure these + * transactions are atomic. + */ +static DEFINE_SPINLOCK(kirkwood_pcie_lock); + +static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + unsigned long flags; + int ret; + + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + spin_lock_irqsave(&kirkwood_pcie_lock, flags); + ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); + spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); + + return ret; +} + +static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) +{ + unsigned long flags; + int ret; + + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + spin_lock_irqsave(&kirkwood_pcie_lock, flags); + ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); + spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); + + return ret; +} + +static struct pci_ops pcie_ops = { + .read = pcie_rd_conf, + .write = pcie_wr_conf, +}; + + +static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) +{ + struct resource *res; + + /* + * Generic PCIe unit setup. + */ + orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info); + + /* + * Request resources. + */ + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("pcie_setup unable to alloc resources"); + + /* + * IORESOURCE_IO + */ + res[0].name = "PCIe I/O Space"; + res[0].flags = IORESOURCE_IO; + res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE; + res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCIe IO resource failed\n"); + sys->resource[0] = &res[0]; + + /* + * IORESOURCE_MEM + */ + res[1].name = "PCIe Memory Space"; + res[1].flags = IORESOURCE_MEM; + res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; + res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) + panic("Request PCIe Memory resource failed\n"); + sys->resource[1] = &res[1]; + + sys->resource[2] = NULL; + sys->io_offset = 0; + + return 1; +} + +static void __devinit rc_pci_fixup(struct pci_dev *dev) +{ + /* + * Prevent enumeration of root complex. + */ + if (dev->bus->parent == NULL && dev->devfn == 0) { + int i; + + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); + +static struct pci_bus __init * +kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct pci_bus *bus; + + if (nr == 0) { + bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); + } else { + bus = NULL; + BUG(); + } + + return bus; +} + +static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + return IRQ_KIRKWOOD_PCIE; +} + +static struct hw_pci kirkwood_pci __initdata = { + .nr_controllers = 1, + .swizzle = pci_std_swizzle, + .setup = kirkwood_pcie_setup, + .scan = kirkwood_pcie_scan_bus, + .map_irq = kirkwood_pcie_map_irq, +}; + +void __init kirkwood_pcie_init(void) +{ + pci_common_init(&kirkwood_pci); +} diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c new file mode 100644 index 00000000000..6cf642c504d --- /dev/null +++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c @@ -0,0 +1,69 @@ +/* + * arch/arm/mach-kirkwood/rd88f6192-nas-setup.c + * + * Marvell RD-88F6192-NAS Reference Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +#define RD88F6192_GPIO_USB_VBUS 10 + +static struct mv643xx_eth_platform_data rd88f6192_ge00_data = { + .phy_addr = 8, +}; + +static struct mv_sata_platform_data rd88f6192_sata_data = { + .n_ports = 2, +}; + +static void __init rd88f6192_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + + kirkwood_ehci_init(); + kirkwood_ge00_init(&rd88f6192_ge00_data); + kirkwood_rtc_init(); + kirkwood_sata_init(&rd88f6192_sata_data); + kirkwood_uart0_init(); +} + +static int __init rd88f6192_pci_init(void) +{ + if (machine_is_rd88f6192_nas()) + kirkwood_pcie_init(); + + return 0; +} +subsys_initcall(rd88f6192_pci_init); + +MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board") + /* Maintainer: Saeed Bishara */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = rd88f6192_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c new file mode 100644 index 00000000000..fe8b242d206 --- /dev/null +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -0,0 +1,112 @@ +/* + * arch/arm/mach-kirkwood/rd88f6281-setup.c + * + * Marvell RD-88F6281 Reference Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +static struct mtd_partition rd88f6281_nand_parts[] = { + { + .name = "u-boot", + .offset = 0, + .size = SZ_1M + }, { + .name = "uImage", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_2M + }, { + .name = "root", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL + }, +}; + +static struct resource rd88f6281_nand_resource = { + .flags = IORESOURCE_MEM, + .start = KIRKWOOD_NAND_MEM_PHYS_BASE, + .end = KIRKWOOD_NAND_MEM_PHYS_BASE + + KIRKWOOD_NAND_MEM_SIZE - 1, +}; + +static struct orion_nand_data rd88f6281_nand_data = { + .parts = rd88f6281_nand_parts, + .nr_parts = ARRAY_SIZE(rd88f6281_nand_parts), + .cle = 0, + .ale = 1, + .width = 8, +}; + +static struct platform_device rd88f6281_nand_flash = { + .name = "orion_nand", + .id = -1, + .dev = { + .platform_data = &rd88f6281_nand_data, + }, + .resource = &rd88f6281_nand_resource, + .num_resources = 1, +}; + +static struct mv643xx_eth_platform_data rd88f6281_ge00_data = { + .phy_addr = -1, +}; + +static struct mv_sata_platform_data rd88f6281_sata_data = { + .n_ports = 2, +}; + +static void __init rd88f6281_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + + kirkwood_ehci_init(); + kirkwood_ge00_init(&rd88f6281_ge00_data); + kirkwood_rtc_init(); + kirkwood_sata_init(&rd88f6281_sata_data); + kirkwood_uart0_init(); + kirkwood_uart1_init(); + + platform_device_register(&rd88f6281_nand_flash); +} + +static int __init rd88f6281_pci_init(void) +{ + if (machine_is_rd88f6281()) + kirkwood_pcie_init(); + + return 0; +} +subsys_initcall(rd88f6281_pci_init); + +MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board") + /* Maintainer: Saeed Bishara */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = rd88f6281_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END -- cgit v1.2.3-18-g5258 From 1338760329c586e0141831099e15f5c336dd9c1d Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Mon, 23 Jun 2008 01:05:08 -1100 Subject: [ARM] Kirkwood: support L2 writeback mode This patch allows booting Kirkwood with the L2 in writeback mode, by reading the WT override bit from the L2 config register and passing that into the Feroceon L2 init routine, instead of assuming that the WT override bit will always be set Signed-off-by: Saeed Bishara Signed-off-by: Lennert Buytenhek --- arch/arm/mach-kirkwood/common.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-kirkwood') diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index e73384fbbba..5938a3b33cd 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -313,6 +313,11 @@ static char * __init kirkwood_id(void) return "unknown 88F6000 variant"; } +static int __init is_l2_writethrough(void) +{ + return !!(readl(L2_CONFIG_REG) & L2_WRITETHROUGH); +} + void __init kirkwood_init(void) { printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", @@ -321,6 +326,6 @@ void __init kirkwood_init(void) kirkwood_setup_cpu_mbus(); #ifdef CONFIG_CACHE_FEROCEON_L2 - feroceon_l2_init(1); + feroceon_l2_init(is_l2_writethrough()); #endif } -- cgit v1.2.3-18-g5258 From 5b2353859f87748f0707cec57c3953022a3321f3 Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Thu, 5 Jun 2008 13:19:30 +0200 Subject: [ARM] Kirkwood: use chip_delay Signed-off-by: Saeed Bishara Signed-off-by: Lennert Buytenhek --- arch/arm/mach-kirkwood/rd88f6281-setup.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-kirkwood') diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c index fe8b242d206..e1f8de2c74a 100644 --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -54,6 +54,7 @@ static struct orion_nand_data rd88f6281_nand_data = { .cle = 0, .ale = 1, .width = 8, + .chip_delay = 25, }; static struct platform_device rd88f6281_nand_flash = { -- cgit v1.2.3-18-g5258