From cd7201f477b965f6c0220b798813c7000bc603c5 Mon Sep 17 00:00:00 2001 From: Giuseppe CAVALLARO Date: Wed, 4 Apr 2012 04:33:27 +0000 Subject: stmmac: MDC clock dynamically based on the csr clock input If a specific clk_csr value is passed from the platform this means that the CSR Clock Range selection cannot be changed at run-time and it is fixed (as reported in the driver documentation). Viceversa the driver will try to set the MDC clock dynamically according to the actual clock input. Signed-off-by: Deepak Sikri Signed-off-by: Giuseppe Cavallaro Reviewed-by: Francesco Virlinzi Reviewed-by: David Laight Signed-off-by: David S. Miller --- Documentation/networking/stmmac.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/networking') diff --git a/Documentation/networking/stmmac.txt b/Documentation/networking/stmmac.txt index eacb640286b..ab1e8d7004c 100644 --- a/Documentation/networking/stmmac.txt +++ b/Documentation/networking/stmmac.txt @@ -137,7 +137,7 @@ Where: o pbl: the Programmable Burst Length is maximum number of beats to be transferred in one DMA transaction. GMAC also enables the 4xPBL by default. - o clk_csr: CSR Clock range selection. + o clk_csr: fixed CSR Clock range selection. o has_gmac: uses the GMAC core. o enh_desc: if sets the MAC will use the enhanced descriptor structure. o tx_coe: core is able to perform the tx csum in HW. -- cgit v1.2.3-18-g5258