From ed54fcfd785e8fecfbd8b129466235fc4ab0a402 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Mon, 16 Jul 2007 11:55:42 +0100 Subject: [ARM] 4479/1: AT91: Define new MMC register bits Add definitions for RDPROOF, WRPROOF and PDCFBYTE bits of the Mode Register in the updated MMC controller found on the AT91SAM9260 and AT91SAM9263 processors. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91_mci.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h index 40a9876b661..c2e11cc374b 100644 --- a/include/asm-arm/arch-at91/at91_mci.h +++ b/include/asm-arm/arch-at91/at91_mci.h @@ -26,6 +26,9 @@ #define AT91_MCI_MR 0x04 /* Mode Register */ #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ +#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ +#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ +#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ -- cgit v1.2.3-18-g5258