From 9a9943575ade643368849e2c963094ac637867e0 Mon Sep 17 00:00:00 2001 From: Mark Mason Date: Fri, 13 Apr 2007 10:32:25 -0700 Subject: [MIPS] Add missing silicon revisions for BCM112x Recent versions of the BCM112X processors aren't recognized by Linux (preventing Linux from booting on those processors). This patch adds support for those that are missing. Signed-off-by: Mark Mason Signed-off-by: Ralf Baechle --- arch/mips/sibyte/sb1250/setup.c | 12 ++++++++++++ include/asm-mips/sibyte/sb1250_scd.h | 1 + 2 files changed, 13 insertions(+) diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c index 87188f0f6fb..f4a6169aa0a 100644 --- a/arch/mips/sibyte/sb1250/setup.c +++ b/arch/mips/sibyte/sb1250/setup.c @@ -141,6 +141,18 @@ static int __init setup_bcm112x(void) periph_rev = 3; pass_str = "A2"; break; + case K_SYS_REVISION_BCM112x_A3: + periph_rev = 3; + pass_str = "A3"; + break; + case K_SYS_REVISION_BCM112x_A4: + periph_rev = 3; + pass_str = "A4"; + break; + case K_SYS_REVISION_BCM112x_B0: + periph_rev = 3; + pass_str = "B0"; + break; default: printk("Unknown %s rev %x\n", soc_str, soc_pass); ret = 1; diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h index 7ed0bb611e5..b6a7d8f6ced 100644 --- a/include/asm-mips/sibyte/sb1250_scd.h +++ b/include/asm-mips/sibyte/sb1250_scd.h @@ -84,6 +84,7 @@ #define K_SYS_REVISION_BCM112x_A2 0x21 #define K_SYS_REVISION_BCM112x_A3 0x22 #define K_SYS_REVISION_BCM112x_A4 0x23 +#define K_SYS_REVISION_BCM112x_B0 0x30 #define K_SYS_REVISION_BCM1480_S0 0x01 #define K_SYS_REVISION_BCM1480_A1 0x02 -- cgit v1.2.3-18-g5258 From 5323180db75d562a287cb2020b07c9422df13df6 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sat, 14 Apr 2007 02:37:26 +0900 Subject: [MIPS] Disallow CpU exception in kernel again. The commit 4d40bff7110e9e1a97ff8c01bdd6350e9867cc10 ("Allow CpU exception in kernel partially") was broken. The commit was to fix theoretical problem but broke usual case. Revert it for now. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/kernel/r2300_switch.S | 10 ++++------ arch/mips/kernel/r4k_switch.S | 10 ++++------ arch/mips/kernel/signal.c | 10 +++++----- arch/mips/kernel/signal32.c | 10 +++++----- arch/mips/kernel/traps.c | 21 +++------------------ include/asm-mips/fpu.h | 16 ---------------- include/asm-mips/thread_info.h | 1 - 7 files changed, 21 insertions(+), 57 deletions(-) diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S index 28c2e2e6af7..656bde2e11b 100644 --- a/arch/mips/kernel/r2300_switch.S +++ b/arch/mips/kernel/r2300_switch.S @@ -49,7 +49,8 @@ LEAF(resume) #ifndef CONFIG_CPU_HAS_LLSC sw zero, ll_bit #endif - mfc0 t2, CP0_STATUS + mfc0 t1, CP0_STATUS + sw t1, THREAD_STATUS(a0) cpu_save_nonscratch a0 sw ra, THREAD_REG31(a0) @@ -59,8 +60,8 @@ LEAF(resume) lw t3, TASK_THREAD_INFO(a0) lw t0, TI_FLAGS(t3) li t1, _TIF_USEDFPU - and t1, t0 - beqz t1, 1f + and t2, t0, t1 + beqz t2, 1f nor t1, zero, t1 and t0, t0, t1 @@ -73,13 +74,10 @@ LEAF(resume) li t1, ~ST0_CU1 and t0, t0, t1 sw t0, ST_OFF(t3) - /* clear thread_struct CU1 bit */ - and t2, t1 fpu_save_single a0, t0 # clobbers t0 1: - sw t2, THREAD_STATUS(a0) /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index c7698fd9955..cc566cf1224 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -48,7 +48,8 @@ #ifndef CONFIG_CPU_HAS_LLSC sw zero, ll_bit #endif - mfc0 t2, CP0_STATUS + mfc0 t1, CP0_STATUS + LONG_S t1, THREAD_STATUS(a0) cpu_save_nonscratch a0 LONG_S ra, THREAD_REG31(a0) @@ -58,8 +59,8 @@ PTR_L t3, TASK_THREAD_INFO(a0) LONG_L t0, TI_FLAGS(t3) li t1, _TIF_USEDFPU - and t1, t0 - beqz t1, 1f + and t2, t0, t1 + beqz t2, 1f nor t1, zero, t1 and t0, t0, t1 @@ -72,13 +73,10 @@ li t1, ~ST0_CU1 and t0, t0, t1 LONG_S t0, ST_OFF(t3) - /* clear thread_struct CU1 bit */ - and t2, t1 fpu_save_double a0 t0 t1 # c0_status passed in t0 # clobbers t1 1: - LONG_S t2, THREAD_STATUS(a0) /* * The order of restoring the registers takes care of the race diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 8c3c5a5789b..fa581192de2 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -113,10 +113,10 @@ int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ + preempt_disable(); own_fpu(1); - enable_fp_in_kernel(); err |= save_fp_context(sc); - disable_fp_in_kernel(); + preempt_enable(); } return err; } @@ -148,7 +148,10 @@ check_and_restore_fp_context(struct sigcontext __user *sc) err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; + preempt_disable(); + own_fpu(0); err |= restore_fp_context(sc); + preempt_enable(); return err ?: sig; } @@ -187,11 +190,8 @@ int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) if (used_math) { /* restore fpu context if we have used it before */ - own_fpu(0); - enable_fp_in_kernel(); if (!err) err = check_and_restore_fp_context(sc); - disable_fp_in_kernel(); } else { /* signal handler may have used FPU. Give it up. */ lose_fpu(0); diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 151fd2f0893..53a337cfeb6 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -209,10 +209,10 @@ static int setup_sigcontext32(struct pt_regs *regs, * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ + preempt_disable(); own_fpu(1); - enable_fp_in_kernel(); err |= save_fp_context32(sc); - disable_fp_in_kernel(); + preempt_enable(); } return err; } @@ -225,7 +225,10 @@ check_and_restore_fp_context32(struct sigcontext32 __user *sc) err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; + preempt_disable(); + own_fpu(0); err |= restore_fp_context32(sc); + preempt_enable(); return err ?: sig; } @@ -261,11 +264,8 @@ static int restore_sigcontext32(struct pt_regs *regs, if (used_math) { /* restore fpu context if we have used it before */ - own_fpu(0); - enable_fp_in_kernel(); if (!err) err = check_and_restore_fp_context32(sc); - disable_fp_in_kernel(); } else { /* signal handler may have used FPU. Give it up. */ lose_fpu(0); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 7d76a85422b..6b356f62289 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -757,11 +757,12 @@ asmlinkage void do_cpu(struct pt_regs *regs) { unsigned int cpid; + die_if_kernel("do_cpu invoked from kernel context!", regs); + cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; switch (cpid) { case 0: - die_if_kernel("do_cpu invoked from kernel context!", regs); if (!cpu_has_llsc) if (!simulate_llsc(regs)) return; @@ -772,9 +773,6 @@ asmlinkage void do_cpu(struct pt_regs *regs) break; case 1: - if (!test_thread_flag(TIF_ALLOW_FP_IN_KERNEL)) - die_if_kernel("do_cpu invoked from kernel context!", - regs); if (used_math()) /* Using the FPU again. */ own_fpu(1); else { /* First time FPU user. */ @@ -782,19 +780,7 @@ asmlinkage void do_cpu(struct pt_regs *regs) set_used_math(); } - if (raw_cpu_has_fpu) { - if (test_thread_flag(TIF_ALLOW_FP_IN_KERNEL)) { - local_irq_disable(); - if (cpu_has_fpu) - regs->cp0_status |= ST0_CU1; - /* - * We must return without enabling - * interrupts to ensure keep FPU - * ownership until resume. - */ - return; - } - } else { + if (!raw_cpu_has_fpu) { int sig; sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0); @@ -836,7 +822,6 @@ asmlinkage void do_cpu(struct pt_regs *regs) case 2: case 3: - die_if_kernel("do_cpu invoked from kernel context!", regs); break; } diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 4e12d1f9534..71436f90203 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -68,8 +68,6 @@ do { \ /* We don't care about the c0 hazard here */ \ } while (0) -#define __fpu_enabled() (read_c0_status() & ST0_CU1) - #define enable_fpu() \ do { \ if (cpu_has_fpu) \ @@ -162,18 +160,4 @@ static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) return tsk->thread.fpu.fpr; } -static inline void enable_fp_in_kernel(void) -{ - set_thread_flag(TIF_ALLOW_FP_IN_KERNEL); - /* make sure CU1 and FPU ownership are consistent */ - if (!__is_fpu_owner() && __fpu_enabled()) - __disable_fpu(); -} - -static inline void disable_fp_in_kernel(void) -{ - BUG_ON(!__is_fpu_owner() && __fpu_enabled()); - clear_thread_flag(TIF_ALLOW_FP_IN_KERNEL); -} - #endif /* _ASM_FPU_H */ diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index 6cf05f4a4e7..fbcda820447 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -119,7 +119,6 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 18 #define TIF_FREEZE 19 -#define TIF_ALLOW_FP_IN_KERNEL 20 #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ #define _TIF_SYSCALL_TRACE (1< Date: Mon, 16 Apr 2007 23:19:44 +0900 Subject: [MIPS] Retry {save,restore}_fp_context if failed in atomic context. The save_fp_context()/restore_fp_context() might sleep on accessing user stack and therefore might lose FPU ownership in middle of them. If these function failed due to "in_atomic" test in do_page_fault, touch the sigcontext area in non-atomic context and retry these save/restore operation. This is a replacement of a (broken) fix which was titled "Allow CpU exception in kernel partially". Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/kernel/signal-common.h | 9 +++++++ arch/mips/kernel/signal.c | 52 +++++++++++++++++++++++++++++++++------- arch/mips/kernel/signal32.c | 52 +++++++++++++++++++++++++++++++++------- include/asm-mips/fpu.h | 9 +++++-- 4 files changed, 102 insertions(+), 20 deletions(-) diff --git a/arch/mips/kernel/signal-common.h b/arch/mips/kernel/signal-common.h index 297dfcb9752..c0faabd5201 100644 --- a/arch/mips/kernel/signal-common.h +++ b/arch/mips/kernel/signal-common.h @@ -34,4 +34,13 @@ extern int install_sigtramp(unsigned int __user *tramp, unsigned int syscall); /* Check and clear pending FPU exceptions in saved CSR */ extern int fpcsr_pending(unsigned int __user *fpcsr); +/* Make sure we will not lose FPU ownership */ +#ifdef CONFIG_PREEMPT +#define lock_fpu_owner() preempt_disable() +#define unlock_fpu_owner() preempt_enable() +#else +#define lock_fpu_owner() pagefault_disable() +#define unlock_fpu_owner() pagefault_enable() +#endif + #endif /* __SIGNAL_COMMON_H */ diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index fa581192de2..07d67309451 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -27,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -78,6 +78,46 @@ struct rt_sigframe { /* * Helper routines */ +static int protected_save_fp_context(struct sigcontext __user *sc) +{ + int err; + while (1) { + lock_fpu_owner(); + own_fpu_inatomic(1); + err = save_fp_context(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __put_user(0, &sc->sc_fpregs[0]) | + __put_user(0, &sc->sc_fpregs[31]) | + __put_user(0, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + +static int protected_restore_fp_context(struct sigcontext __user *sc) +{ + int err, tmp; + while (1) { + lock_fpu_owner(); + own_fpu_inatomic(0); + err = restore_fp_context(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __get_user(tmp, &sc->sc_fpregs[0]) | + __get_user(tmp, &sc->sc_fpregs[31]) | + __get_user(tmp, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { int err = 0; @@ -113,10 +153,7 @@ int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ - preempt_disable(); - own_fpu(1); - err |= save_fp_context(sc); - preempt_enable(); + err |= protected_save_fp_context(sc); } return err; } @@ -148,10 +185,7 @@ check_and_restore_fp_context(struct sigcontext __user *sc) err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; - preempt_disable(); - own_fpu(0); - err |= restore_fp_context(sc); - preempt_enable(); + err |= protected_restore_fp_context(sc); return err ?: sig; } diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 53a337cfeb6..b9a014411f8 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -29,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -176,6 +176,46 @@ struct rt_sigframe32 { /* * sigcontext handlers */ +static int protected_save_fp_context32(struct sigcontext32 __user *sc) +{ + int err; + while (1) { + lock_fpu_owner(); + own_fpu_inatomic(1); + err = save_fp_context32(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __put_user(0, &sc->sc_fpregs[0]) | + __put_user(0, &sc->sc_fpregs[31]) | + __put_user(0, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + +static int protected_restore_fp_context32(struct sigcontext32 __user *sc) +{ + int err, tmp; + while (1) { + lock_fpu_owner(); + own_fpu_inatomic(0); + err = restore_fp_context32(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __get_user(tmp, &sc->sc_fpregs[0]) | + __get_user(tmp, &sc->sc_fpregs[31]) | + __get_user(tmp, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + static int setup_sigcontext32(struct pt_regs *regs, struct sigcontext32 __user *sc) { @@ -209,10 +249,7 @@ static int setup_sigcontext32(struct pt_regs *regs, * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ - preempt_disable(); - own_fpu(1); - err |= save_fp_context32(sc); - preempt_enable(); + err |= protected_save_fp_context32(sc); } return err; } @@ -225,10 +262,7 @@ check_and_restore_fp_context32(struct sigcontext32 __user *sc) err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; - preempt_disable(); - own_fpu(0); - err |= restore_fp_context32(sc); - preempt_enable(); + err |= protected_restore_fp_context32(sc); return err ?: sig; } diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 71436f90203..b414a7d9db4 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -100,14 +100,19 @@ static inline void __own_fpu(void) set_thread_flag(TIF_USEDFPU); } -static inline void own_fpu(int restore) +static inline void own_fpu_inatomic(int restore) { - preempt_disable(); if (cpu_has_fpu && !__is_fpu_owner()) { __own_fpu(); if (restore) _restore_fp(current); } +} + +static inline void own_fpu(int restore) +{ + preempt_disable(); + own_fpu_inatomic(restore); preempt_enable(); } -- cgit v1.2.3-18-g5258 From ba755f8ec80fdbf2b5212622eabf7355464c6327 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Thu, 12 Apr 2007 20:02:54 +0900 Subject: [MIPS] Fix BUG(), BUG_ON() handling With commit 63dc68a8cf60cb110b147dab1704d990808b39e2, kernel can not handle BUG() and BUG_ON() properly since get_user() returns false for kernel code. Use __get_user() to skip unnecessary access_ok(). This patch also make BRK_BUG code encoded in the TNE instruction. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 4 ++-- include/asm-mips/bug.h | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 6b356f62289..493cb29b8a4 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -650,7 +650,7 @@ asmlinkage void do_bp(struct pt_regs *regs) unsigned int opcode, bcode; siginfo_t info; - if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) + if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) goto out_sigsegv; /* @@ -700,7 +700,7 @@ asmlinkage void do_tr(struct pt_regs *regs) unsigned int opcode, tcode = 0; siginfo_t info; - if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) + if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) goto out_sigsegv; /* Immediate versions don't provide a code. */ diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h index 4d560a53394..7eb63de808b 100644 --- a/include/asm-mips/bug.h +++ b/include/asm-mips/bug.h @@ -18,7 +18,8 @@ do { \ #define BUG_ON(condition) \ do { \ - __asm__ __volatile__("tne $0, %0" : : "r" (condition)); \ + __asm__ __volatile__("tne $0, %0, %1" \ + : : "r" (condition), "i" (BRK_BUG)); \ } while (0) #define HAVE_ARCH_BUG_ON -- cgit v1.2.3-18-g5258 From 1d464c26b5625215c4b35fb336c8f3c57d248c2e Mon Sep 17 00:00:00 2001 From: Dave Johnson Date: Wed, 18 Apr 2007 10:39:41 -0400 Subject: [MIPS] Fix wrong checksum for split TCP packets on 64-bit MIPS I've traced down an off-by-one TCP checksum calculation error under the following conditions: 1) The TCP code needs to split a full-sized packet due to a reduced MSS (typically due to the addition of TCP options mid-stream like SACK). _AND_ 2) The checksum of the 2nd fragment is larger than the checksum of the original packet. After subtraction this results in a checksum for the 1st fragment with bits 16..31 set to 1. (this is ok) _AND_ 3) The checksum of the 1st fragment's TCP header plus the previously 32bit checksum of the 1st fragment DOES NOT cause a 32bit overflow when added together. This results in a checksum of the TCP header plus TCP data that still has the upper 16 bits as 1's. _THEN_ 4) The TCP+data checksum is added to the checksum of the pseudo IP header with csum_tcpudp_nofold() incorrectly (the bug). The problem is the checksum of the TCP+data is passed to csum_tcpudp_nofold() as an 32bit unsigned value, however the assembly code acts on it as if it is a 64bit unsigned value. This causes an incorrect 32->64bit extension if the sum has bit 31 set. The resulting checksum is off by one. This problems is data and TCP header dependent due to #2 and #3 above so it doesn't occur on every TCP packet split. Signed-off-by: Dave Johnson Signed-off-by: Ralf Baechle --- include/asm-mips/checksum.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h index 20a81e1548f..290485ac540 100644 --- a/include/asm-mips/checksum.h +++ b/include/asm-mips/checksum.h @@ -166,7 +166,7 @@ static inline __wsum csum_tcpudp_nofold(__be32 saddr, #else "r" (proto + len), #endif - "r" (sum)); + "r" ((__force unsigned long)sum)); return sum; } -- cgit v1.2.3-18-g5258