From 727b0f71a56de64c0994e24f2504b1b954fd6f93 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 16 Jan 2014 15:36:53 +0000 Subject: pinctrl: st: Add Interrupt support This patch add interrupt support to the pincontroller driver. ST Pincontroller GPIO bank can have one of the two possible types of interrupt-wirings. First type is via irqmux, single interrupt is used by multiple gpio banks. This reduces number of overall interrupts numbers required. All these banks belong to a single pincontroller. _________ | |----> [gpio-bank (n) ] | |----> [gpio-bank (n + 1)] [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] | |----> [gpio-bank (... )] |_________|----> [gpio-bank (n + 7)] Second type has a dedicated interrupt per gpio bank. [irqN]----> [gpio-bank (n)] Signed-off-by: Srinivas Kandagatla Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-st.txt | 73 ++++++- drivers/pinctrl/pinctrl-st.c | 225 ++++++++++++++++++++- 2 files changed, 290 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt index 05bf82a07df..4bd5be0e5e7 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt @@ -11,18 +11,68 @@ Pull Up (PU) are driven by the related PIO block. ST pinctrl driver controls PIO multiplexing block and also interacts with gpio driver to configure a pin. -Required properties: (PIO multiplexing block) +GPIO bank can have one of the two possible types of interrupt-wirings. + +First type is via irqmux, single interrupt is used by multiple gpio banks. This +reduces number of overall interrupts numbers required. All these banks belong to +a single pincontroller. + _________ + | |----> [gpio-bank (n) ] + | |----> [gpio-bank (n + 1)] + [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] + | |----> [gpio-bank (... )] + |_________|----> [gpio-bank (n + 7)] + +Second type has a dedicated interrupt per gpio bank. + + [irqN]----> [gpio-bank (n)] + + +Pin controller node: +Required properties: - compatible : should be "st,--pinctrl" like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on. -- gpio-controller : Indicates this device is a GPIO controller -- #gpio-cells : Should be one. The first cell is the pin number. +- st,syscfg : Should be a phandle of the syscfg node. - st,retime-pin-mask : Should be mask to specify which pins can be retimed. If the property is not present, it is assumed that all the pins in the bank are capable of retiming. Retiming is mainly used to improve the IO timing margins of external synchronous interfaces. -- st,bank-name : Should be a name string for this bank as - specified in datasheet. -- st,syscfg : Should be a phandle of the syscfg node. +- ranges : defines mapping between pin controller node (parent) to gpio-bank + node (children). + +Optional properties: +- interrupts : Interrupt number of the irqmux. If the interrupt is shared + with other gpio banks via irqmux. + a irqline and gpio banks. +- reg : irqmux memory resource. If irqmux is present. +- reg-names : irqmux resource should be named as "irqmux". + +GPIO controller/bank node. +Required properties: +- gpio-controller : Indicates this device is a GPIO controller +- #gpio-cells : Should be one. The first cell is the pin number. +- st,bank-name : Should be a name string for this bank as specified in + datasheet. + +Optional properties: +- interrupts : Interrupt number for this gpio bank. If there is a dedicated + interrupt wired up for this gpio bank. + +- interrupt-controller : Indicates this device is a interrupt controller. GPIO + bank can be an interrupt controller iff one of the interrupt type either via +irqmux or a dedicated interrupt per bank is specified. + +- #interrupt-cells: the value of this property should be 2. + - First Cell: represents the external gpio interrupt number local to the + gpio interrupt space of the controller. + - Second Cell: flags to identify the type of the interrupt + - 1 = rising edge triggered + - 2 = falling edge triggered + - 3 = rising and falling edge triggered + - 4 = high level triggered + - 8 = low level triggered +for related macros look in: +include/dt-bindings/interrupt-controller/irq.h Example: pin-controller-sbc { @@ -30,10 +80,17 @@ Example: #size-cells = <1>; compatible = "st,stih415-sbc-pinctrl"; st,syscfg = <&syscfg_sbc>; + reg = <0xfe61f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupts-names = "irqmux"; ranges = <0 0xfe610000 0x5000>; + PIO0: gpio@fe610000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0 0x100>; st,bank-name = "PIO0"; }; @@ -105,6 +162,10 @@ pin-controller { sdhci0:sdhci@fe810000{ ... + interrupt-parent = <&PIO3>; + #interrupt-cells = <2>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */ + interrupts-names = "card-detect"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc>; }; diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 320c27363cc..51e4f3a1d24 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -13,7 +13,12 @@ #include #include #include +#include +#include +#include +#include #include +#include #include #include #include @@ -271,6 +276,7 @@ struct st_gpio_bank { struct pinctrl_gpio_range range; void __iomem *base; struct st_pio_control pc; + struct irq_domain *domain; }; struct st_pinctrl { @@ -284,6 +290,7 @@ struct st_pinctrl { int ngroups; struct regmap *regmap; const struct st_pctl_data *data; + void __iomem *irqmux_base; }; /* SOC specific data */ @@ -1200,6 +1207,130 @@ static int st_pctl_parse_functions(struct device_node *np, return 0; } +static int st_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct st_gpio_bank *bank = gpio_chip_to_bank(chip); + int irq = -ENXIO; + + if (offset < chip->ngpio) + irq = irq_find_mapping(bank->domain, offset); + + dev_info(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", + chip->label, offset + chip->base, irq); + return irq; +} + +static void st_gpio_irq_mask(struct irq_data *d) +{ + struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); + + writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); +} + +static void st_gpio_irq_unmask(struct irq_data *d) +{ + struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); + + writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); +} + +static unsigned int st_gpio_irq_startup(struct irq_data *d) +{ + struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); + + if (gpio_lock_as_irq(&bank->gpio_chip, d->hwirq)) + dev_err(bank->gpio_chip.dev, + "unable to lock HW IRQ %lu for IRQ\n", + d->hwirq); + + st_gpio_irq_unmask(d); + + return 0; +} + +static void st_gpio_irq_shutdown(struct irq_data *d) +{ + struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); + + st_gpio_irq_mask(d); + gpio_unlock_as_irq(&bank->gpio_chip, d->hwirq); +} + +static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) +{ + struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); + unsigned long flags; + int comp, pin = d->hwirq; + u32 val; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + comp = 0; + break; + case IRQ_TYPE_LEVEL_LOW: + comp = 1; + break; + default: + return -EINVAL; + } + + val = readl(bank->base + REG_PIO_PCOMP); + val &= ~BIT(pin); + val |= (comp << pin); + writel(val, bank->base + REG_PIO_PCOMP); + + return 0; +} + +static void __gpio_irq_handler(struct st_gpio_bank *bank) +{ + unsigned long port_in, port_mask, port_comp, active_irqs; + int n; + + for (;;) { + port_in = readl(bank->base + REG_PIO_PIN); + port_comp = readl(bank->base + REG_PIO_PCOMP); + port_mask = readl(bank->base + REG_PIO_PMASK); + + active_irqs = (port_in ^ port_comp) & port_mask; + + if (active_irqs == 0) + break; + + for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { + generic_handle_irq(irq_find_mapping(bank->domain, n)); + } + } +} + +static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc) +{ + /* interrupt dedicated per bank */ + struct irq_chip *chip = irq_get_chip(irq); + struct st_gpio_bank *bank = irq_get_handler_data(irq); + + chained_irq_enter(chip, desc); + __gpio_irq_handler(bank); + chained_irq_exit(chip, desc); +} + +static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct st_pinctrl *info = irq_get_handler_data(irq); + unsigned long status; + int n; + + chained_irq_enter(chip, desc); + + status = readl(info->irqmux_base); + + for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK) + __gpio_irq_handler(&info->banks[n]); + + chained_irq_exit(chip, desc); +} + static struct gpio_chip st_gpio_template = { .request = st_gpio_request, .free = st_gpio_free, @@ -1210,6 +1341,34 @@ static struct gpio_chip st_gpio_template = { .ngpio = ST_GPIO_PINS_PER_BANK, .of_gpio_n_cells = 1, .of_xlate = st_gpio_xlate, + .to_irq = st_gpio_to_irq, +}; + +static struct irq_chip st_gpio_irqchip = { + .name = "GPIO", + .irq_mask = st_gpio_irq_mask, + .irq_unmask = st_gpio_irq_unmask, + .irq_set_type = st_gpio_irq_set_type, + .irq_startup = st_gpio_irq_startup, + .irq_shutdown = st_gpio_irq_shutdown, +}; + +static int st_gpio_irq_domain_map(struct irq_domain *h, + unsigned int virq, irq_hw_number_t hw) +{ + struct st_gpio_bank *bank = h->host_data; + + irq_set_chip(virq, &st_gpio_irqchip); + irq_set_handler(virq, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); + irq_set_chip_data(virq, bank); + + return 0; +} + +static struct irq_domain_ops st_gpio_irq_ops = { + .map = st_gpio_irq_domain_map, + .xlate = irq_domain_xlate_twocell, }; static int st_gpiolib_register_bank(struct st_pinctrl *info, @@ -1219,8 +1378,8 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, struct pinctrl_gpio_range *range = &bank->range; struct device *dev = info->dev; int bank_num = of_alias_get_id(np, "gpio"); - struct resource res; - int err; + struct resource res, irq_res; + int gpio_irq = 0, err, i; if (of_address_to_resource(np, 0, &res)) return -ENODEV; @@ -1248,6 +1407,51 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, } dev_info(dev, "%s bank added.\n", range->name); + /** + * GPIO bank can have one of the two possible types of + * interrupt-wirings. + * + * First type is via irqmux, single interrupt is used by multiple + * gpio banks. This reduces number of overall interrupts numbers + * required. All these banks belong to a single pincontroller. + * _________ + * | |----> [gpio-bank (n) ] + * | |----> [gpio-bank (n + 1)] + * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] + * | |----> [gpio-bank (... )] + * |_________|----> [gpio-bank (n + 7)] + * + * Second type has a dedicated interrupt per each gpio bank. + * + * [irqN]----> [gpio-bank (n)] + */ + + if (!of_irq_to_resource(np, 0, &irq_res)) { + gpio_irq = irq_res.start; + irq_set_chained_handler(gpio_irq, st_gpio_irq_handler); + irq_set_handler_data(gpio_irq, bank); + } + + if (info->irqmux_base > 0 || gpio_irq > 0) { + /* Setup IRQ domain */ + bank->domain = irq_domain_add_linear(np, + ST_GPIO_PINS_PER_BANK, + &st_gpio_irq_ops, bank); + if (!bank->domain) { + dev_err(dev, "Failed to add irq domain for %s\n", + np->full_name); + } else { + for (i = 0; i < ST_GPIO_PINS_PER_BANK; i++) { + if (irq_create_mapping(bank->domain, i) < 0) + dev_err(dev, + "Failed to map IRQ %i\n", i); + } + } + + } else { + dev_info(dev, "No IRQ support for %s bank\n", np->full_name); + } + return 0; } @@ -1276,6 +1480,8 @@ static int st_pctl_probe_dt(struct platform_device *pdev, struct device_node *np = pdev->dev.of_node; struct device_node *child; int grp_index = 0; + int irq = 0; + struct resource *res; st_pctl_dt_child_count(info, np); if (!info->nbanks) { @@ -1306,6 +1512,21 @@ static int st_pctl_probe_dt(struct platform_device *pdev, } info->data = of_match_node(st_pctl_of_match, np)->data; + irq = platform_get_irq(pdev, 0); + + if (irq > 0) { + res = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "irqmux"); + info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); + + if (IS_ERR(info->irqmux_base)) + return PTR_ERR(info->irqmux_base); + + irq_set_chained_handler(irq, st_gpio_irqmux_handler); + irq_set_handler_data(irq, info); + + } + pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; pdesc = devm_kzalloc(&pdev->dev, sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL); -- cgit v1.2.3-18-g5258 From 155795b9d143f4210c19ab50462e19fdeb38bc81 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 16 Jan 2014 15:37:31 +0000 Subject: pinctrl: st: Add software edge trigger interrupt support ST pin controller does not have hardware support for detecting edge triggered interrupts, It only has level triggering support. This patch attempts to fake up edge triggers from hw level trigger support in software. With this facility now the gpios can be easily used for keypads, otherwise it would be difficult for drivers like keypads to work with level trigger interrupts. Signed-off-by: Srinivas Kandagatla Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 116 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 114 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 51e4f3a1d24..9fb66aa796a 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -271,12 +271,59 @@ struct st_pctl_group { struct st_pinconf *pin_conf; }; +/* + * Edge triggers are not supported at hardware level, it is supported by + * software by exploiting the level trigger support in hardware. + * Software uses a virtual register (EDGE_CONF) for edge trigger configuration + * of each gpio pin in a GPIO bank. + * + * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of + * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. + * + * bit allocation per pin is: + * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] + * -------------------------------------------------------- + * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | + * -------------------------------------------------------- + * + * A pin can have one of following the values in its edge configuration field. + * + * ------- ---------------------------- + * [0-3] - Description + * ------- ---------------------------- + * 0000 - No edge IRQ. + * 0001 - Falling edge IRQ. + * 0010 - Rising edge IRQ. + * 0011 - Rising and Falling edge IRQ. + * ------- ---------------------------- + */ + +#define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 +#define ST_IRQ_EDGE_MASK 0xf +#define ST_IRQ_EDGE_FALLING BIT(0) +#define ST_IRQ_EDGE_RISING BIT(1) +#define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) + +#define ST_IRQ_RISING_EDGE_CONF(pin) \ + (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) + +#define ST_IRQ_FALLING_EDGE_CONF(pin) \ + (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) + +#define ST_IRQ_BOTH_EDGE_CONF(pin) \ + (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) + +#define ST_IRQ_EDGE_CONF(conf, pin) \ + (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) + struct st_gpio_bank { struct gpio_chip gpio_chip; struct pinctrl_gpio_range range; void __iomem *base; struct st_pio_control pc; struct irq_domain *domain; + unsigned long irq_edge_conf; + spinlock_t lock; }; struct st_pinctrl { @@ -1262,18 +1309,37 @@ static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) unsigned long flags; int comp, pin = d->hwirq; u32 val; + u32 pin_edge_conf = 0; switch (type) { case IRQ_TYPE_LEVEL_HIGH: comp = 0; break; + case IRQ_TYPE_EDGE_FALLING: + comp = 0; + pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); + break; case IRQ_TYPE_LEVEL_LOW: comp = 1; break; + case IRQ_TYPE_EDGE_RISING: + comp = 1; + pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); + break; + case IRQ_TYPE_EDGE_BOTH: + comp = st_gpio_get(&bank->gpio_chip, pin); + pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); + break; default: return -EINVAL; } + spin_lock_irqsave(&bank->lock, flags); + bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( + pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); + bank->irq_edge_conf |= pin_edge_conf; + spin_unlock_irqrestore(&bank->lock, flags); + val = readl(bank->base + REG_PIO_PCOMP); val &= ~BIT(pin); val |= (comp << pin); @@ -1282,10 +1348,39 @@ static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) return 0; } +/* + * As edge triggers are not supported at hardware level, it is supported by + * software by exploiting the level trigger support in hardware. + * + * Steps for detection raising edge interrupt in software. + * + * Step 1: CONFIGURE pin to detect level LOW interrupts. + * + * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, + * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. + * IGNORE calling the actual interrupt handler for the pin at this stage. + * + * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler + * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then + * DISPATCH the interrupt to the interrupt handler of the pin. + * + * step-1 ________ __________ + * | | step - 3 + * | | + * step -2 |_____| + * + * falling edge is also detected int the same way. + * + */ static void __gpio_irq_handler(struct st_gpio_bank *bank) { unsigned long port_in, port_mask, port_comp, active_irqs; - int n; + unsigned long bank_edge_mask, flags; + int n, val, ecfg; + + spin_lock_irqsave(&bank->lock, flags); + bank_edge_mask = bank->irq_edge_conf; + spin_unlock_irqrestore(&bank->lock, flags); for (;;) { port_in = readl(bank->base + REG_PIO_PIN); @@ -1298,6 +1393,22 @@ static void __gpio_irq_handler(struct st_gpio_bank *bank) break; for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { + /* check if we are detecting fake edges ... */ + ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); + + if (ecfg) { + /* edge detection. */ + val = st_gpio_get(&bank->gpio_chip, n); + + writel(BIT(n), + val ? bank->base + REG_PIO_SET_PCOMP : + bank->base + REG_PIO_CLR_PCOMP); + + if (ecfg != ST_IRQ_EDGE_BOTH && + !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) + continue; + } + generic_handle_irq(irq_find_mapping(bank->domain, n)); } } @@ -1359,7 +1470,7 @@ static int st_gpio_irq_domain_map(struct irq_domain *h, struct st_gpio_bank *bank = h->host_data; irq_set_chip(virq, &st_gpio_irqchip); - irq_set_handler(virq, handle_level_irq); + irq_set_handler(virq, handle_simple_irq); set_irq_flags(virq, IRQF_VALID); irq_set_chip_data(virq, bank); @@ -1392,6 +1503,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; bank->gpio_chip.of_node = np; + spin_lock_init(&bank->lock); of_property_read_string(np, "st,bank-name", &range->name); bank->gpio_chip.label = range->name; -- cgit v1.2.3-18-g5258 From 2d0c386f135e41865f15e467fa1c6c0ec93d4a60 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Sun, 12 Jan 2014 12:00:30 +0100 Subject: pinctrl: sh-pfc: r8a7791: Add QSPI pin groups A QSPI function set consists of 3 groups: - qspi_ctrl (2 control wires) - qspi_data2 (2 data wires, for Single/Dual SPI) - qspi_data4 (4 data wires, for Quad SPI) Signed-off-by: Geert Uytterhoeven Signed-off-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 63 ++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 77d103fe39d..2a64589b5dc 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -2135,6 +2135,53 @@ static const unsigned int msiof2_tx_pins[] = { static const unsigned int msiof2_tx_mux[] = { MSIOF2_TXD_MARK, }; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 8), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; + +static const unsigned int qspi_ctrl_b_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), +}; +static const unsigned int qspi_ctrl_b_mux[] = { + SPCLK_B_MARK, SSL_B_MARK, +}; +static const unsigned int qspi_data2_b_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), +}; +static const unsigned int qspi_data2_b_mux[] = { + MOSI_IO0_B_MARK, MISO_IO1_B_MARK, +}; +static const unsigned int qspi_data4_b_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), + RCAR_GP_PIN(6, 4), +}; +static const unsigned int qspi_data4_b_mux[] = { + SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK, + IO2_B_MARK, IO3_B_MARK, SSL_B_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -3149,6 +3196,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof2_ss2), SH_PFC_PIN_GROUP(msiof2_rx), SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(qspi_ctrl_b), + SH_PFC_PIN_GROUP(qspi_data2_b), + SH_PFC_PIN_GROUP(qspi_data4_b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -3376,6 +3429,15 @@ static const char * const msiof2_groups[] = { "msiof2_tx", }; +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", + "qspi_ctrl_b", + "qspi_data2_b", + "qspi_data4_b", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_data_b", @@ -3571,6 +3633,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), -- cgit v1.2.3-18-g5258 From 94e692071a51594c5117055676fef3ecbab21b30 Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Thu, 23 Jan 2014 11:37:58 +0100 Subject: pinctrl: at91: use gpiolib API to mark a GPIO used as an IRQ When an IRQ is started on a GPIO line, mark this GPIO as IRQ in the gpiolib so we can keep track of the usage centrally. Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index d990e33d8aa..71247f47fce 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1325,6 +1325,31 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type) return 0; } +static unsigned int gpio_irq_startup(struct irq_data *d) +{ + struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); + unsigned pin = d->hwirq; + int ret; + + ret = gpio_lock_as_irq(&at91_gpio->chip, pin); + if (ret) { + dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n", + d->hwirq); + return ret; + } + gpio_irq_unmask(d); + return 0; +} + +static void gpio_irq_shutdown(struct irq_data *d) +{ + struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); + unsigned pin = d->hwirq; + + gpio_irq_mask(d); + gpio_unlock_as_irq(&at91_gpio->chip, pin); +} + #ifdef CONFIG_PM static u32 wakeups[MAX_GPIO_BANKS]; @@ -1399,6 +1424,8 @@ void at91_pinctrl_gpio_resume(void) static struct irq_chip gpio_irqchip = { .name = "GPIO", + .irq_startup = gpio_irq_startup, + .irq_shutdown = gpio_irq_shutdown, .irq_disable = gpio_irq_mask, .irq_mask = gpio_irq_mask, .irq_unmask = gpio_irq_unmask, -- cgit v1.2.3-18-g5258 From 1e6f8e3c92fbbcd5bcca860c4db4eef2052aa79f Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Mon, 27 Jan 2014 18:23:54 +0800 Subject: pinctrl: Move pint PM storage structure out of blackfin architecture. It is better to keep this structure in the pinctrl-adi2 driver. Signed-off-by: Sonic Zhang Signed-off-by: Linus Walleij --- arch/blackfin/include/asm/irq.h | 9 --------- drivers/pinctrl/pinctrl-adi2.c | 15 ++++++++++++++- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h index 2fd04f10cc2..89de539ed01 100644 --- a/arch/blackfin/include/asm/irq.h +++ b/arch/blackfin/include/asm/irq.h @@ -20,15 +20,6 @@ /* SYS_IRQS and NR_IRQS are defined in */ #include -/* - * pm save bfin pint registers - */ -struct adi_pm_pint_save { - u32 assign; - u32 edge_set; - u32 invert_set; -}; - #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) # define NOP_PAD_ANOMALY_05000244 "nop; nop;" #else diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index 7a39562c3e4..e8120fadf38 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -89,6 +89,19 @@ struct gpio_port_saved { u32 mux; }; +/* + * struct gpio_pint_saved - PINT registers saved in PM operations + * + * @assign: ASSIGN register + * @edge_set: EDGE_SET register + * @invert_set: INVERT_SET register + */ +struct gpio_pint_saved { + u32 assign; + u32 edge_set; + u32 invert_set; +}; + /** * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO * banks can be mapped into one Pin interrupt controller. @@ -114,7 +127,7 @@ struct gpio_pint { int irq; struct irq_domain *domain[2]; struct gpio_pint_regs *regs; - struct adi_pm_pint_save saved_data; + struct gpio_pint_saved saved_data; int map_count; spinlock_t lock; -- cgit v1.2.3-18-g5258 From b4eef7b22544d46d918696253e9086975dc6f8b0 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Mon, 27 Jan 2014 18:23:55 +0800 Subject: pinctrl-adi2: change irq_base from usigned int to int Negative irq_base means this gpio port doens't support interrupts. Signed-off-by: Sonic Zhang Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-adi2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index e8120fadf38..9fb53c921d4 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -173,7 +173,7 @@ struct adi_pinctrl { struct gpio_port { struct list_head node; void __iomem *base; - unsigned int irq_base; + int irq_base; unsigned int width; struct gpio_port_t *regs; struct gpio_port_saved saved_data; -- cgit v1.2.3-18-g5258 From b81e57e6ac35242ba59206b303ba6c7585764ee1 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Mon, 27 Jan 2014 18:23:56 +0800 Subject: pinctrl-adi2: fix coding style issue Signed-off-by: Sonic Zhang Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-adi2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index 9fb53c921d4..72450a120a5 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -641,7 +641,7 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, spin_lock_irqsave(&port->lock, flags); portmux_setup(port, pin_to_offset(range, pin), - P_FUNCT2MUX(*mux)); + P_FUNCT2MUX(*mux)); port_setup(port, pin_to_offset(range, pin), false); mux++; -- cgit v1.2.3-18-g5258 From 4bd7547756af5c71d55e4d77f41db3d06c18b3e0 Mon Sep 17 00:00:00 2001 From: Chao Xie Date: Tue, 28 Jan 2014 15:20:44 +0800 Subject: pinctrl: single: add low power mode support For some silicons, the pin configuration register can control the output of the pin when the pad including the pin enter low power mode. For example, the pin can be "Drive 1", "Drive 0", "Float" when the pad including the pin enter low power mode. It is very useful when you want to control the power leakeage when the SOC enter low power mode, and can save more power for the low power mode. Signed-off-by: Chao Xie Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt | 7 +++++++ drivers/pinctrl/pinctrl-single.c | 3 +++ 2 files changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index bc0dfdfdb14..66dcaa9efd7 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -63,6 +63,13 @@ Optional properties: /* input, enable bits, disable bits, mask */ pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>; +- pinctrl-single,low-power-mode : array of value that are used to configure + low power mode of this pin. For some silicons, the low power mode will + control the output of the pin when the pad including the pin enter low + power mode. + /* low power mode value, mask */ + pinctrl-single,low-power-mode = <0x288 0x388>; + - pinctrl-single,gpio-range : list of value that are used to configure a GPIO range. They're value of subnode phandle, pin base in pinctrl device, pin number in this range, GPIO function value of this GPIO range. diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index de6459628b4..81075f2a1d3 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -662,6 +662,7 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_SLEW_RATE: + case PIN_CONFIG_LOW_POWER_MODE: default: *config = data; break; @@ -699,6 +700,7 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_INPUT_SCHMITT: case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_SLEW_RATE: + case PIN_CONFIG_LOW_POWER_MODE: shift = ffs(func->conf[i].mask) - 1; data &= ~func->conf[i].mask; data |= (arg << shift) & func->conf[i].mask; @@ -1101,6 +1103,7 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, + { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, }, }; struct pcs_conf_type prop4[] = { { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, -- cgit v1.2.3-18-g5258 From 58ffe7a02583bd19bb83c8bc7e277705625316a2 Mon Sep 17 00:00:00 2001 From: Rongjun Ying Date: Thu, 30 Jan 2014 13:54:24 +0800 Subject: pinctrl: sirf: add pin group for USP0 for atlas6 USP0 has multiple functions, and has RX and TX frame sync signals, for some scenarios like audio PCM, we don't need both of them. so here we add two possibilities for USP0 only holding one of TX and RX frame sync. commit 8385af02bad only added this group for prima2, and missed atlas6. This patch fixes it. Signed-off-by: Rongjun Ying Signed-off-by: Barry Song Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-atlas6.c | 43 +++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c index 2b9f3206592..09211fbeda9 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas6.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c @@ -529,6 +529,40 @@ static const struct sirfsoc_padmux usp0_padmux = { static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; +static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = { + { + .group = 1, + .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), + }, +}; + +static const struct sirfsoc_padmux usp0_only_utfs_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask), + .muxmask = usp0_only_utfs_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(2) | BIT(6), + .funcval = 0, +}; + +static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 }; + +static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = { + { + .group = 1, + .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23), + }, +}; + +static const struct sirfsoc_padmux usp0_only_urfs_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask), + .muxmask = usp0_only_urfs_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(2) | BIT(9), + .funcval = 0, +}; + +static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 }; + static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = { { .group = 1, @@ -905,6 +939,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp", usp0_uart_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins), + SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins), SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp", usp1_uart_nostreamctrl_pins), @@ -953,6 +989,9 @@ static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; static const char * const usp0_uart_nostreamctrl_grp[] = { "usp0_uart_nostreamctrl_grp" }; static const char * const usp0grp[] = { "usp0grp" }; +static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" }; +static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" }; + static const char * const usp1grp[] = { "usp1grp" }; static const char * const usp1_uart_nostreamctrl_grp[] = { "usp1_uart_nostreamctrl_grp" }; @@ -1003,6 +1042,10 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, + usp0_only_utfs_padmux), + SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, + usp0_only_urfs_padmux), SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl", usp1_uart_nostreamctrl_grp, -- cgit v1.2.3-18-g5258 From ed118a5fd951bd2def8249ee251842c4f81fe4bd Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 4 Feb 2014 19:55:31 -0800 Subject: pinctrl-msm: Support output-{high,low} configuration Add support for configuring pins as output with value as from the pinconf-generic interface. Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-msm.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c index ef2bf3126da..2cfb1d4e439 100644 --- a/drivers/pinctrl/pinctrl-msm.c +++ b/drivers/pinctrl/pinctrl-msm.c @@ -228,6 +228,11 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, *bit = g->drv_bit; *mask = 7; break; + case PIN_CONFIG_OUTPUT: + *reg = g->ctl_reg; + *bit = g->oe_bit; + *mask = 1; + break; default: dev_err(pctrl->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; @@ -301,6 +306,14 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_DRIVE_STRENGTH: arg = msm_regval_to_drive[arg]; break; + case PIN_CONFIG_OUTPUT: + /* Pin is not output */ + if (!arg) + return -EINVAL; + + val = readl(pctrl->regs + g->io_reg); + arg = !!(val & BIT(g->in_bit)); + break; default: dev_err(pctrl->dev, "Unsupported config parameter: %x\n", param); @@ -357,6 +370,20 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, else arg = msm_drive_to_regval[arg]; break; + case PIN_CONFIG_OUTPUT: + /* set output value */ + spin_lock_irqsave(&pctrl->lock, flags); + val = readl(pctrl->regs + g->io_reg); + if (arg) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + writel(val, pctrl->regs + g->io_reg); + spin_unlock_irqrestore(&pctrl->lock, flags); + + /* enable output */ + arg = 1; + break; default: dev_err(pctrl->dev, "Unsupported config parameter: %x\n", param); -- cgit v1.2.3-18-g5258 From 9a8b6079721ff2e59439fa688916c8e364599eef Mon Sep 17 00:00:00 2001 From: Young-Gun Jang Date: Wed, 5 Feb 2014 11:51:28 +0530 Subject: pinctrl: exynos: add exynos5260 SoC specific data Adds pinctrl support for all platforms based on EXYNOS5260 SoC. Acked-by: Tomasz Figa Signed-off-by: Pankaj Dubey Signed-off-by: Young-Gun Jang Signed-off-by: Rahul Sharma Signed-off-by: Arun Kumar K Signed-off-by: Linus Walleij --- .../bindings/pinctrl/samsung-pinctrl.txt | 1 + drivers/pinctrl/pinctrl-exynos.c | 82 ++++++++++++++++++++++ drivers/pinctrl/pinctrl-samsung.c | 2 + drivers/pinctrl/pinctrl-samsung.h | 1 + 4 files changed, 86 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 257677de3e6..2b32783ba82 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -16,6 +16,7 @@ Required Properties: - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. + - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c index 155b1b3a0e7..07c81306f2f 100644 --- a/drivers/pinctrl/pinctrl-exynos.c +++ b/drivers/pinctrl/pinctrl-exynos.c @@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { }, }; +/* pin banks of exynos5260 pin-controller 0 */ +static struct samsung_pin_bank exynos5260_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5260 pin-controller 1 */ +static struct samsung_pin_bank exynos5260_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), +}; + +/* pin banks of exynos5260 pin-controller 2 */ +static struct samsung_pin_bank exynos5260_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +/* + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes + * three gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5260_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .weint_con = EXYNOS_WKUP_ECON_OFFSET, + .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .label = "exynos5260-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5260_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5260_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl2", + }, +}; + /* pin banks of exynos5420 pin-controller 0 */ static struct samsung_pin_bank exynos5420_pin_banks0[] = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index 47ec2e8741e..0324d4cb19b 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -1120,6 +1120,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos4x12_pin_ctrl }, { .compatible = "samsung,exynos5250-pinctrl", .data = (void *)exynos5250_pin_ctrl }, + { .compatible = "samsung,exynos5260-pinctrl", + .data = (void *)exynos5260_pin_ctrl }, { .compatible = "samsung,exynos5420-pinctrl", .data = (void *)exynos5420_pin_ctrl }, { .compatible = "samsung,s5pv210-pinctrl", diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h index 30622d9afa2..bab9c212255 100644 --- a/drivers/pinctrl/pinctrl-samsung.h +++ b/drivers/pinctrl/pinctrl-samsung.h @@ -254,6 +254,7 @@ struct samsung_pmx_func { extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5260_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; -- cgit v1.2.3-18-g5258 From 97e00faaf16a0642cac47937e26f437651a6b4a4 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 30 Jan 2014 08:10:19 +0900 Subject: pinctrl: sh-pfc: r8a7790: Break out USB0 OVC/VBUS Create a new group for the USB0 OVC/VBUS pin by itself. This allows us to monitor PWEN as GPIO on the Lager board. Signed-off-by: Magnus Damm Acked-by: Laurent Pinchart Acked-by: Simon Horman Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index c381ae63c50..ee2ae05c23a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3231,6 +3231,13 @@ static const unsigned int usb0_pins[] = { static const unsigned int usb0_mux[] = { USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, }; +static const unsigned int usb0_ovc_vbus_pins[] = { + /* OVC/VBUS */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int usb0_ovc_vbus_mux[] = { + USB0_OVC_VBUS_MARK, +}; /* - USB1 ------------------------------------------------------------------- */ static const unsigned int usb1_pins[] = { /* PWEN, OVC */ @@ -3789,6 +3796,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu0_to2), SH_PFC_PIN_GROUP(tpu0_to3), SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc_vbus), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), VIN_DATA_PIN_GROUP(vin0_data, 24), @@ -4134,6 +4142,7 @@ static const char * const tpu0_groups[] = { static const char * const usb0_groups[] = { "usb0", + "usb0_ovc_vbus", }; static const char * const usb1_groups[] = { -- cgit v1.2.3-18-g5258 From 5d88dceac736a779fdf6208bbd0a06e81fe25300 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 30 Jan 2014 18:57:20 +0000 Subject: pinctrl: Quiet logging about missing DT nodes when not using DT On systems which were not booted using DT it is entirely unsurprising that device nodes don't have any DT information and this is going to happen for every single device in the system. Make pinctrl be less chatty about this situation by only logging in the case where we have DT. Signed-off-by: Mark Brown Signed-off-by: Linus Walleij --- drivers/pinctrl/devicetree.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 340fb4e6c60..eda13de2e7c 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -186,7 +186,9 @@ int pinctrl_dt_to_map(struct pinctrl *p) /* CONFIG_OF enabled, p->dev not instantiated from DT */ if (!np) { - dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n"); + if (of_have_populated_dt()) + dev_dbg(p->dev, + "no of_node; not parsing pinctrl DT\n"); return 0; } -- cgit v1.2.3-18-g5258 From dc1791188bce9b3260aa98f9a017ada910a58401 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 6 Feb 2014 17:28:48 +0200 Subject: pinctrl-msm: Add SPI8 pin definitions Add pin, group and function definitions for SPI#8 controller. Signed-off-by: Ivan T. Ivanov Acked-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-msm8x74.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c index f944bf2172e..9aeeb384ddf 100644 --- a/drivers/pinctrl/pinctrl-msm8x74.c +++ b/drivers/pinctrl/pinctrl-msm8x74.c @@ -406,6 +406,7 @@ enum msm8x74_functions { MSM_MUX_blsp_i2c6, MSM_MUX_blsp_i2c11, MSM_MUX_blsp_spi1, + MSM_MUX_blsp_spi8, MSM_MUX_blsp_uart2, MSM_MUX_blsp_uart8, MSM_MUX_slimbus, @@ -416,6 +417,9 @@ static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" }; static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; static const char * const blsp_spi1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" }; +static const char * const blsp_spi8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; static const char * const blsp_uart2_groups[] = { "gpio4", "gpio5" }; static const char * const blsp_uart8_groups[] = { "gpio45", "gpio46" }; static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; @@ -425,6 +429,7 @@ static const struct msm_function msm8x74_functions[] = { FUNCTION(blsp_i2c6), FUNCTION(blsp_i2c11), FUNCTION(blsp_spi1), + FUNCTION(blsp_spi8), FUNCTION(blsp_uart2), FUNCTION(blsp_uart8), FUNCTION(slimbus), @@ -476,10 +481,10 @@ static const struct msm_pingroup msm8x74_groups[] = { PINGROUP(42, NA, NA, NA, NA, NA, NA, NA), PINGROUP(43, NA, NA, NA, NA, NA, NA, NA), PINGROUP(44, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(45, NA, blsp_uart8, NA, NA, NA, NA, NA), - PINGROUP(46, NA, blsp_uart8, NA, NA, NA, NA, NA), - PINGROUP(47, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(48, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA), + PINGROUP(46, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA), + PINGROUP(47, blsp_spi8, NA, NA, NA, NA, NA, NA), + PINGROUP(48, blsp_spi8, NA, NA, NA, NA, NA, NA), PINGROUP(49, NA, NA, NA, NA, NA, NA, NA), PINGROUP(50, NA, NA, NA, NA, NA, NA, NA), PINGROUP(51, NA, NA, NA, NA, NA, NA, NA), -- cgit v1.2.3-18-g5258 From 202909cdf117743bdbf8abc0f817950c8955c8cf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 10 Feb 2014 14:00:57 +0100 Subject: pinctrl: sh-pfc: r8a7790: Add QSPI pin groups A QSPI function set consists of 3 groups: - qspi_ctrl (2 control wires) - qspi_data2 (2 data wires, for Single/Dual SPI) - qspi_data4 (4 data wires, for Quad SPI) Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index ee2ae05c23a..2814440843d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -2389,6 +2389,29 @@ static const unsigned int msiof3_tx_pins[] = { static const unsigned int msiof3_tx_mux[] = { MSIOF3_TXD_MARK, }; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 8), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -3678,6 +3701,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof3_ss2), SH_PFC_PIN_GROUP(msiof3_rx), SH_PFC_PIN_GROUP(msiof3_tx), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -3978,6 +4004,12 @@ static const char * const msiof3_groups[] = { "msiof3_tx", }; +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -4222,6 +4254,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), -- cgit v1.2.3-18-g5258 From 131d85bc3aea81fbe35a30d6df0a6501b87294ed Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Wed, 12 Feb 2014 13:59:38 +0100 Subject: pinctrl: nomadik: Silence compiler warn for !CONFIG_PM The static suspend/resume functions were not being used while !CONFIG_PM. Fix it and convert to CONFIG_PM_SLEEP. Signed-off-by: Ulf Hansson Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-nomadik.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 53a11114927..b6c5793efb8 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -2035,6 +2035,7 @@ static const struct of_device_id nmk_pinctrl_match[] = { {}, }; +#ifdef CONFIG_PM_SLEEP static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) { struct nmk_pinctrl *npct; @@ -2056,6 +2057,7 @@ static int nmk_pinctrl_resume(struct platform_device *pdev) return pinctrl_force_default(npct->pctl); } +#endif static int nmk_pinctrl_probe(struct platform_device *pdev) { @@ -2151,7 +2153,7 @@ static struct platform_driver nmk_pinctrl_driver = { .of_match_table = nmk_pinctrl_match, }, .probe = nmk_pinctrl_probe, -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP .suspend = nmk_pinctrl_suspend, .resume = nmk_pinctrl_resume, #endif -- cgit v1.2.3-18-g5258 From c003eed7a0aa8630b7936a8c2c0132055b4c3c92 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Wed, 12 Feb 2014 13:59:39 +0100 Subject: pinctrl: nomadik: Convert to modern pm_ops Use the SIMPLE_DEV_PM_OPS macro and convert to the modern pm ops. Signed-off-by: Ulf Hansson Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-nomadik.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index b6c5793efb8..cec7762cf33 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -2036,22 +2036,22 @@ static const struct of_device_id nmk_pinctrl_match[] = { }; #ifdef CONFIG_PM_SLEEP -static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) +static int nmk_pinctrl_suspend(struct device *dev) { struct nmk_pinctrl *npct; - npct = platform_get_drvdata(pdev); + npct = dev_get_drvdata(dev); if (!npct) return -EINVAL; return pinctrl_force_sleep(npct->pctl); } -static int nmk_pinctrl_resume(struct platform_device *pdev) +static int nmk_pinctrl_resume(struct device *dev) { struct nmk_pinctrl *npct; - npct = platform_get_drvdata(pdev); + npct = dev_get_drvdata(dev); if (!npct) return -EINVAL; @@ -2146,17 +2146,18 @@ static struct platform_driver nmk_gpio_driver = { .probe = nmk_gpio_probe, }; +static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, + nmk_pinctrl_suspend, + nmk_pinctrl_resume); + static struct platform_driver nmk_pinctrl_driver = { .driver = { .owner = THIS_MODULE, .name = "pinctrl-nomadik", .of_match_table = nmk_pinctrl_match, + .pm = &nmk_pinctrl_pm_ops, }, .probe = nmk_pinctrl_probe, -#ifdef CONFIG_PM_SLEEP - .suspend = nmk_pinctrl_suspend, - .resume = nmk_pinctrl_resume, -#endif }; static int __init nmk_gpio_init(void) -- cgit v1.2.3-18-g5258 From 019c12f474bfc9d72d69654c0db3fbc7584ee176 Mon Sep 17 00:00:00 2001 From: Barry Song Date: Wed, 12 Feb 2014 21:54:47 +0800 Subject: pinctrl: sirf: update copyright years to 2014 Signed-off-by: Barry Song Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-atlas6.c | 3 ++- drivers/pinctrl/sirf/pinctrl-prima2.c | 3 ++- drivers/pinctrl/sirf/pinctrl-sirf.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c index 09211fbeda9..c4dd3d5cf9c 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas6.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c @@ -1,7 +1,8 @@ /* * pinctrl pads, groups, functions for CSR SiRFatlasVI * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. * * Licensed under GPLv2 or later. */ diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c index dde0285544d..8aa76f0776d 100644 --- a/drivers/pinctrl/sirf/pinctrl-prima2.c +++ b/drivers/pinctrl/sirf/pinctrl-prima2.c @@ -1,7 +1,8 @@ /* * pinctrl pads, groups, functions for CSR SiRFprimaII * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. * * Licensed under GPLv2 or later. */ diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index a0d6152701c..72291cd5400 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -1,7 +1,8 @@ /* * pinmux driver for CSR SiRFprimaII * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. * * Licensed under GPLv2 or later. */ -- cgit v1.2.3-18-g5258 From e3653749aaee8dc8c819b9e4137f07e0383afb7e Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 14 Feb 2014 18:21:06 +0800 Subject: pinctrl: pinctrl-adi: combine multiple groups of one function together The data pins of some peripheral are different if connecting to different devices in one pinmux function. In the PPI case, data pins can be used in 8, 16 and 24 pin groups individually. Add these groups into one ppi function. Signed-off-by: Sonic Zhang Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-adi2-bf54x.c | 138 +++++++++++++++++------------------ drivers/pinctrl/pinctrl-adi2-bf60x.c | 128 ++++++++++++++++---------------- drivers/pinctrl/pinctrl-adi2.c | 12 +-- drivers/pinctrl/pinctrl-adi2.h | 8 +- 4 files changed, 139 insertions(+), 147 deletions(-) diff --git a/drivers/pinctrl/pinctrl-adi2-bf54x.c b/drivers/pinctrl/pinctrl-adi2-bf54x.c index ea9d9ab9cda..008a29e92e5 100644 --- a/drivers/pinctrl/pinctrl-adi2-bf54x.c +++ b/drivers/pinctrl/pinctrl-adi2-bf54x.c @@ -309,39 +309,6 @@ static const unsigned keys_8x8_pins[] = { GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, }; -static const struct adi_pin_group adi_pin_groups[] = { - ADI_PIN_GROUP("uart0grp", uart0_pins), - ADI_PIN_GROUP("uart1grp", uart1_pins), - ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins), - ADI_PIN_GROUP("uart2grp", uart2_pins), - ADI_PIN_GROUP("uart3grp", uart3_pins), - ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins), - ADI_PIN_GROUP("rsi0grp", rsi0_pins), - ADI_PIN_GROUP("spi0grp", spi0_pins), - ADI_PIN_GROUP("spi1grp", spi1_pins), - ADI_PIN_GROUP("twi0grp", twi0_pins), - ADI_PIN_GROUP("twi1grp", twi1_pins), - ADI_PIN_GROUP("rotarygrp", rotary_pins), - ADI_PIN_GROUP("can0grp", can0_pins), - ADI_PIN_GROUP("can1grp", can1_pins), - ADI_PIN_GROUP("smc0grp", smc0_pins), - ADI_PIN_GROUP("sport0grp", sport0_pins), - ADI_PIN_GROUP("sport1grp", sport1_pins), - ADI_PIN_GROUP("sport2grp", sport2_pins), - ADI_PIN_GROUP("sport3grp", sport3_pins), - ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins), - ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins), - ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins), - ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins), - ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins), - ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins), - ADI_PIN_GROUP("atapigrp", atapi_pins), - ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins), - ADI_PIN_GROUP("nfc0grp", nfc0_pins), - ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins), - ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins), -}; - static const unsigned short uart0_mux[] = { P_UART0_TX, P_UART0_RX, 0 @@ -513,6 +480,39 @@ static const unsigned short keys_8x8_mux[] = { 0 }; +static const struct adi_pin_group adi_pin_groups[] = { + ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux), + ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux), + ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux), + ADI_PIN_GROUP("uart2grp", uart2_pins, uart2_mux), + ADI_PIN_GROUP("uart3grp", uart3_pins, uart3_mux), + ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins, uart3_ctsrts_mux), + ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux), + ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux), + ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux), + ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux), + ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux), + ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux), + ADI_PIN_GROUP("can0grp", can0_pins, can0_mux), + ADI_PIN_GROUP("can1grp", can1_pins, can1_mux), + ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux), + ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux), + ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux), + ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux), + ADI_PIN_GROUP("sport3grp", sport3_pins, sport3_mux), + ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux), + ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux), + ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux), + ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux), + ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux), + ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux), + ADI_PIN_GROUP("atapigrp", atapi_pins, atapi_mux), + ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins, atapi_alter_mux), + ADI_PIN_GROUP("nfc0grp", nfc0_pins, nfc0_mux), + ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins, keys_4x4_mux), + ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins, keys_8x8_mux), +}; + static const char * const uart0grp[] = { "uart0grp" }; static const char * const uart1grp[] = { "uart1grp" }; static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" }; @@ -532,49 +532,45 @@ static const char * const sport0grp[] = { "sport0grp" }; static const char * const sport1grp[] = { "sport1grp" }; static const char * const sport2grp[] = { "sport2grp" }; static const char * const sport3grp[] = { "sport3grp" }; -static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" }; -static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" }; -static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" }; -static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" }; -static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" }; -static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" }; +static const char * const ppi0grp[] = { "ppi0_8bgrp", + "ppi0_16bgrp", + "ppi0_24bgrp" }; +static const char * const ppi1grp[] = { "ppi1_8bgrp", + "ppi1_16bgrp" }; +static const char * const ppi2grp[] = { "ppi2_8bgrp" }; static const char * const atapigrp[] = { "atapigrp" }; static const char * const atapialtergrp[] = { "atapialtergrp" }; static const char * const nfc0grp[] = { "nfc0grp" }; -static const char * const keys_4x4grp[] = { "keys_4x4grp" }; -static const char * const keys_8x8grp[] = { "keys_8x8grp" }; +static const char * const keysgrp[] = { "keys_4x4grp", + "keys_8x8grp" }; static const struct adi_pmx_func adi_pmx_functions[] = { - ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux), - ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux), - ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux), - ADI_PMX_FUNCTION("uart2", uart2grp, uart2_mux), - ADI_PMX_FUNCTION("uart3", uart3grp, uart3_mux), - ADI_PMX_FUNCTION("uar