From 23fbee9dd5d2a41d36af49ff8e1669fb0c29fda8 Mon Sep 17 00:00:00 2001 From: Ralf Baechle <ralf@linux-mips.org> Date: Mon, 25 Jul 2005 22:45:45 +0000 Subject: Support for Toshiba's RBHMA4500 eval board for the TX4938. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> --- arch/mips/Kconfig | 19 + arch/mips/Makefile | 7 + arch/mips/pci/Makefile | 1 + arch/mips/pci/fixup-tx4938.c | 92 +++ arch/mips/pci/ops-tx4938.c | 198 +++++ arch/mips/tx4938/Kconfig | 24 + arch/mips/tx4938/common/Makefile | 11 + arch/mips/tx4938/common/dbgio.c | 50 ++ arch/mips/tx4938/common/irq.c | 424 ++++++++++ arch/mips/tx4938/common/irq_handler.S | 84 ++ arch/mips/tx4938/common/prom.c | 129 +++ arch/mips/tx4938/common/rtc_rx5c348.c | 202 +++++ arch/mips/tx4938/common/setup.c | 91 +++ arch/mips/tx4938/toshiba_rbtx4938/Makefile | 9 + arch/mips/tx4938/toshiba_rbtx4938/irq.c | 244 ++++++ arch/mips/tx4938/toshiba_rbtx4938/prom.c | 78 ++ arch/mips/tx4938/toshiba_rbtx4938/setup.c | 1035 ++++++++++++++++++++++++ arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c | 219 +++++ arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c | 159 ++++ include/asm-mips/bootinfo.h | 1 + include/asm-mips/tx4938/rbtx4938.h | 207 +++++ include/asm-mips/tx4938/spi.h | 74 ++ include/asm-mips/tx4938/tx4938.h | 706 ++++++++++++++++ include/asm-mips/tx4938/tx4938_mips.h | 54 ++ 24 files changed, 4118 insertions(+) create mode 100644 arch/mips/pci/fixup-tx4938.c create mode 100644 arch/mips/pci/ops-tx4938.c create mode 100644 arch/mips/tx4938/Kconfig create mode 100644 arch/mips/tx4938/common/Makefile create mode 100644 arch/mips/tx4938/common/dbgio.c create mode 100644 arch/mips/tx4938/common/irq.c create mode 100644 arch/mips/tx4938/common/irq_handler.S create mode 100644 arch/mips/tx4938/common/prom.c create mode 100644 arch/mips/tx4938/common/rtc_rx5c348.c create mode 100644 arch/mips/tx4938/common/setup.c create mode 100644 arch/mips/tx4938/toshiba_rbtx4938/Makefile create mode 100644 arch/mips/tx4938/toshiba_rbtx4938/irq.c create mode 100644 arch/mips/tx4938/toshiba_rbtx4938/prom.c create mode 100644 arch/mips/tx4938/toshiba_rbtx4938/setup.c create mode 100644 arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c create mode 100644 arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c create mode 100644 include/asm-mips/tx4938/rbtx4938.h create mode 100644 include/asm-mips/tx4938/spi.h create mode 100644 include/asm-mips/tx4938/tx4938.h create mode 100644 include/asm-mips/tx4938/tx4938_mips.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 338c21f3efd..1f53fe8a89f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -695,6 +695,24 @@ config SOC_AU1500 config SOC_AU1550 bool "SOC_AU1550" +config TOSHIBA_RBTX4938 + bool "Support for Toshiba RBTX4938 board" + select HAVE_STD_PC_SERIAL_PORT + select DMA_NONCOHERENT + select GENERIC_ISA_DMA + select HAS_TXX9_SERIAL + select HW_HAS_PCI + select I8259 + select ISA + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select TOSHIBA_BOARDS + help + This Toshiba board is based on the TX4938 processor. Say Y here to + support this machine type + endchoice choice @@ -837,6 +855,7 @@ config TOSHIBA_FPCIB0 source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" +source "arch/mips/tx4938/Kconfig" source "arch/mips/philips/pnx8550/common/Kconfig" config RWSEM_GENERIC_SPINLOCK diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 9c91e70d8ee..3dc2fb81fb2 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -690,6 +690,13 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 +# +# Toshiba RBTX4938 board +# +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/ +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/ +load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000 + cflags-y += -Iinclude/asm-mips/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index ea8438b81fe..6956de95a7e 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -52,5 +52,6 @@ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c new file mode 100644 index 00000000000..f455520ada8 --- /dev/null +++ b/arch/mips/pci/fixup-tx4938.c @@ -0,0 +1,92 @@ +/* + * Toshiba rbtx4938 pci routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <asm/tx4938/rbtx4938.h> + +extern struct pci_controller tx4938_pci_controller[]; + +int pci_get_irq(struct pci_dev *dev, int pin) +{ + int irq = pin; + u8 slot = PCI_SLOT(dev->devfn); + struct pci_controller *controller = (struct pci_controller *)dev->sysdata; + + if (controller == &tx4938_pci_controller[1]) { + /* TX4938 PCIC1 */ + switch (slot) { + case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; + break; + case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; + break; + } + return 0; + } + + /* IRQ rotation */ + irq--; /* 0-3 */ + if (dev->bus->parent == NULL && + (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { + /* PCI CardSlot (IDSEL=A23) */ + /* PCIA => PCIA (IDSEL=A23) */ + irq = (irq + 0 + slot) % 4; + } else { + /* PCI Backplane */ + irq = (irq + 33 - slot) % 4; + } + irq++; /* 1-4 */ + + switch (irq) { + case 1: + irq = RBTX4938_IRQ_IOC_PCIA; + break; + case 2: + irq = RBTX4938_IRQ_IOC_PCIB; + break; + case 3: + irq = RBTX4938_IRQ_IOC_PCIC; + break; + case 4: + irq = RBTX4938_IRQ_IOC_PCID; + break; + } + return irq; +} + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + unsigned char irq = 0; + + irq = pci_get_irq(dev, pin); + + printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", + dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn), irq); + + return irq; +} + +/* + * Do platform specific device initialization at pci_enable_device() time + */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c new file mode 100644 index 00000000000..4c0dcfce529 --- /dev/null +++ b/arch/mips/pci/ops-tx4938.c @@ -0,0 +1,198 @@ +/* + * Define the pci_ops for the Toshiba rbtx4938 + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <asm/addrspace.h> +#include <asm/tx4938/rbtx4938.h> + +/* initialize in setup */ +struct resource pci_io_resource = { + .name = "pci IO space", + .start = 0, + .end = 0, + .flags = IORESOURCE_IO +}; + +/* initialize in setup */ +struct resource pci_mem_resource = { + .name = "pci memory space", + .start = 0, + .end = 0, + .flags = IORESOURCE_MEM +}; + +struct resource tx4938_pcic1_pci_io_resource = { + .name = "PCI1 IO", + .start = 0, + .end = 0, + .flags = IORESOURCE_IO +}; +struct resource tx4938_pcic1_pci_mem_resource = { + .name = "PCI1 mem", + .start = 0, + .end = 0, + .flags = IORESOURCE_MEM +}; + +static int mkaddr(int bus, int dev_fn, int where, int *flagsp) +{ + if (bus > 0) { + /* Type 1 configuration */ + tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | + ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; + } else { + if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0)) + return -1; + + /* Type 0 configuration */ + tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | + ((dev_fn & 0xff) << 0x08) | (where & 0xfc); + } + /* clear M_ABORT and Disable M_ABORT Int. */ + tx4938_pcicptr->pcistatus = + (tx4938_pcicptr->pcistatus & 0x0000ffff) | + (PCI_STATUS_REC_MASTER_ABORT << 16); + tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; + + return 0; +} + +static int check_abort(int flags) +{ + int code = PCIBIOS_SUCCESSFUL; + /* wait write cycle completion before checking error status */ + while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB) + ; + if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { + tx4938_pcicptr->pcistatus = + (tx4938_pcicptr-> + pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT + << 16); + tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; + code = PCIBIOS_DEVICE_NOT_FOUND; + } + return code; +} + +static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + int flags, retval, dev, busno, func; + + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* check if the bus is top-level */ + if (bus->parent != NULL) + busno = bus->number; + else { + busno = 0; + } + + if (mkaddr(busno, devfn, where, &flags)) + return -1; + + switch (size) { + case 1: + *val = *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 3) ^ 3)); +#else + (where & 3)); +#endif + break; + case 2: + *val = *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 3) ^ 2)); +#else + (where & 3)); +#endif + break; + case 4: + *val = tx4938_pcicptr->g2pcfgdata; + break; + } + + retval = check_abort(flags); + if (retval == PCIBIOS_DEVICE_NOT_FOUND) + *val = 0xffffffff; + + return retval; +} + +static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + int flags, dev, busno, func; + + busno = bus->number; + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* check if the bus is top-level */ + if (bus->parent != NULL) { + busno = bus->number; + } else { + busno = 0; + } + + if (mkaddr(busno, devfn, where, &flags)) + return -1; + + switch (size) { + case 1: + *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 3) ^ 3)) = val; +#else + (where & 3)) = val; +#endif + break; + case 2: + *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 0x3) ^ 0x2)) = val; +#else + (where & 3)) = val; +#endif + break; + case 4: + tx4938_pcicptr->g2pcfgdata = val; + break; + } + + return check_abort(flags); +} + +struct pci_ops tx4938_pci_ops = { + tx4938_pcibios_read_config, + tx4938_pcibios_write_config +}; + +struct pci_controller tx4938_pci_controller[] = { + /* h/w only supports devices 0x00 to 0x14 */ + { + .pci_ops = &tx4938_pci_ops, + .io_resource = &pci_io_resource, + .mem_resource = &pci_mem_resource, + }, + /* h/w only supports devices 0x00 to 0x14 */ + { + .pci_ops = &tx4938_pci_ops, + .io_resource = &tx4938_pcic1_pci_io_resource, + .mem_resource = &tx4938_pcic1_pci_mem_resource, + } +}; diff --git a/arch/mips/tx4938/Kconfig b/arch/mips/tx4938/Kconfig new file mode 100644 index 00000000000..d90e9cd8513 --- /dev/null +++ b/arch/mips/tx4938/Kconfig @@ -0,0 +1,24 @@ +if TOSHIBA_RBTX4938 + +comment "Multiplex Pin Select" +choice + prompt "PIO[58:61]" + default TOSHIBA_RBTX4938_MPLEX_PIO58_61 + +config TOSHIBA_RBTX4938_MPLEX_PIO58_61 + bool "PIO" +config TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND" +config TOSHIBA_RBTX4938_MPLEX_ATA + bool "ATA" + +endchoice + +config TX4938_NAND_BOOT + depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND Boot Support (EXPERIMENTAL)" + help + This is only for Toshiba RBTX4938 reference board, which has NAND IPL. + Select this option if you need to use NAND boot. + +endif diff --git a/arch/mips/tx4938/common/Makefile b/arch/mips/tx4938/common/Makefile new file mode 100644 index 00000000000..74c95c5bcdb --- /dev/null +++ b/arch/mips/tx4938/common/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for common code for Toshiba TX4927 based systems +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +obj-y += prom.o setup.o irq.o irq_handler.o rtc_rx5c348.o +obj-$(CONFIG_KGDB) += dbgio.o + diff --git a/arch/mips/tx4938/common/dbgio.c b/arch/mips/tx4938/common/dbgio.c new file mode 100644 index 00000000000..bea59ff1842 --- /dev/null +++ b/arch/mips/tx4938/common/dbgio.c @@ -0,0 +1,50 @@ +/* + * linux/arch/mips/tx4938/common/dbgio.c + * + * kgdb interface for gdb + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp> + */ + +#include <asm/mipsregs.h> +#include <asm/system.h> +#include <asm/tx4938/tx4938_mips.h> + +extern u8 txx9_sio_kdbg_rd(void); +extern int txx9_sio_kdbg_wr( u8 ch ); + +u8 getDebugChar(void) +{ + return (txx9_sio_kdbg_rd()); +} + +int putDebugChar(u8 byte) +{ + return (txx9_sio_kdbg_wr(byte)); +} + diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c new file mode 100644 index 00000000000..4f90d7faf63 --- /dev/null +++ b/arch/mips/tx4938/common/irq.c @@ -0,0 +1,424 @@ +/* + * linux/arch/mps/tx4938/common/irq.c + * + * Common tx4938 irq handler + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel_stat.h> +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/timex.h> +#include <linux/slab.h> +#include <linux/random.h> +#include <linux/irq.h> +#include <asm/bitops.h> +#include <asm/bootinfo.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/mipsregs.h> +#include <asm/system.h> +#include <asm/tx4938/rbtx4938.h> + +/**********************************************************************************/ +/* Forwad definitions for all pic's */ +/**********************************************************************************/ + +static unsigned int tx4938_irq_cp0_startup(unsigned int irq); +static void tx4938_irq_cp0_shutdown(unsigned int irq); +static void tx4938_irq_cp0_enable(unsigned int irq); +static void tx4938_irq_cp0_disable(unsigned int irq); +static void tx4938_irq_cp0_mask_and_ack(unsigned int irq); +static void tx4938_irq_cp0_end(unsigned int irq); + +static unsigned int tx4938_irq_pic_startup(unsigned int irq); +static void tx4938_irq_pic_shutdown(unsigned int irq); +static void tx4938_irq_pic_enable(unsigned int irq); +static void tx4938_irq_pic_disable(unsigned int irq); +static void tx4938_irq_pic_mask_and_ack(unsigned int irq); +static void tx4938_irq_pic_end(unsigned int irq); + +/**********************************************************************************/ +/* Kernel structs for all pic's */ +/**********************************************************************************/ +DEFINE_SPINLOCK(tx4938_cp0_lock); +DEFINE_SPINLOCK(tx4938_pic_lock); + +#define TX4938_CP0_NAME "TX4938-CP0" +static struct hw_interrupt_type tx4938_irq_cp0_type = { + .typename = TX4938_CP0_NAME, + .startup = tx4938_irq_cp0_startup, + .shutdown = tx4938_irq_cp0_shutdown, + .enable = tx4938_irq_cp0_enable, + .disable = tx4938_irq_cp0_disable, + .ack = tx4938_irq_cp0_mask_and_ack, + .end = tx4938_irq_cp0_end, + .set_affinity = NULL +}; + +#define TX4938_PIC_NAME "TX4938-PIC" +static struct hw_interrupt_type tx4938_irq_pic_type = { + .typename = TX4938_PIC_NAME, + .startup = tx4938_irq_pic_startup, + .shutdown = tx4938_irq_pic_shutdown, + .enable = tx4938_irq_pic_enable, + .disable = tx4938_irq_pic_disable, + .ack = tx4938_irq_pic_mask_and_ack, + .end = tx4938_irq_pic_end, + .set_affinity = NULL +}; + +static struct irqaction tx4938_irq_pic_action = { + .handler = no_action, + .flags = 0, + .mask = CPU_MASK_NONE, + .name = TX4938_PIC_NAME +}; + +/**********************************************************************************/ +/* Functions for cp0 */ +/**********************************************************************************/ + +#define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) ) + +static void __init +tx4938_irq_cp0_init(void) +{ + int i; + + for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &tx4938_irq_cp0_type; + } + + return; +} + +static unsigned int +tx4938_irq_cp0_startup(unsigned int irq) +{ + tx4938_irq_cp0_enable(irq); + + return (0); +} + +static void +tx4938_irq_cp0_shutdown(unsigned int irq) +{ + tx4938_irq_cp0_disable(irq); +} + +static void +tx4938_irq_cp0_enable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_cp0_lock, flags); + + set_c0_status(tx4938_irq_cp0_mask(irq)); + + spin_unlock_irqrestore(&tx4938_cp0_lock, flags); +} + +static void +tx4938_irq_cp0_disable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_cp0_lock, flags); + + clear_c0_status(tx4938_irq_cp0_mask(irq)); + + spin_unlock_irqrestore(&tx4938_cp0_lock, flags); + + return; +} + +static void +tx4938_irq_cp0_mask_and_ack(unsigned int irq) +{ + tx4938_irq_cp0_disable(irq); + + return; +} + +static void +tx4938_irq_cp0_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + tx4938_irq_cp0_enable(irq); + } + + return; +} + +/**********************************************************************************/ +/* Functions for pic */ +/**********************************************************************************/ + +u32 +tx4938_irq_pic_addr(int irq) +{ + /* MVMCP -- need to formulize this */ + irq -= TX4938_IRQ_PIC_BEG; + + switch (irq) { + case 17: + case 16: + case 1: + case 0:{ + return (TX4938_MKA(TX4938_IRC_IRLVL0)); + } + case 19: + case 18: + case 3: + case 2:{ + return (TX4938_MKA(TX4938_IRC_IRLVL1)); + } + case 21: + case 20: + case 5: + case 4:{ + return (TX4938_MKA(TX4938_IRC_IRLVL2)); + } + case 23: + case 22: + case 7: + case 6:{ + return (TX4938_MKA(TX4938_IRC_IRLVL3)); + } + case 25: + case 24: + case 9: + case 8:{ + return (TX4938_MKA(TX4938_IRC_IRLVL4)); + } + case 27: + case 26: + case 11: + case 10:{ + return (TX4938_MKA(TX4938_IRC_IRLVL5)); + } + case 29: + case 28: + case 13: + case 12:{ + return (TX4938_MKA(TX4938_IRC_IRLVL6)); + } + case 31: + case 30: + case 15: + case 14:{ + return (TX4938_MKA(TX4938_IRC_IRLVL7)); + } + } + + return (0); +} + +u32 +tx4938_irq_pic_mask(int irq) +{ + /* MVMCP -- need to formulize this */ + irq -= TX4938_IRQ_PIC_BEG; + + switch (irq) { + case 31: + case 29: + case 27: + case 25: + case 23: + case 21: + case 19: + case 17:{ + return (0x07000000); + } + case 30: + case 28: + case 26: + case 24: + case 22: + case 20: + case 18: + case 16:{ + return (0x00070000); + } + case 15: + case 13: + case 11: + case 9: + case 7: + case 5: + case 3: + case 1:{ + return (0x00000700); + } + case 14: + case 12: + case 10: + case 8: + case 6: + case 4: + case 2: + case 0:{ + return (0x00000007); + } + } + return (0x00000000); +} + +static void +tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits) +{ + unsigned long val = 0; + + val = TX4938_RD(pic_reg); + val &= (~clr_bits); + val |= (set_bits); + TX4938_WR(pic_reg, val); + mmiowb(); + TX4938_RD(pic_reg); + + return; +} + +static void __init +tx4938_irq_pic_init(void) +{ + unsigned long flags; + int i; + + for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 2; + irq_desc[i].handler = &tx4938_irq_pic_type; + } + + setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); + + spin_lock_irqsave(&tx4938_pic_lock, flags); + + TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ + TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */ + + spin_unlock_irqrestore(&tx4938_pic_lock, flags); + + return; +} + +static unsigned int +tx4938_irq_pic_startup(unsigned int irq) +{ + tx4938_irq_pic_enable(irq); + + return (0); +} + +static void +tx4938_irq_pic_shutdown(unsigned int irq) +{ + tx4938_irq_pic_disable(irq); + + return; +} + +static void +tx4938_irq_pic_enable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_pic_lock, flags); + + tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0, + tx4938_irq_pic_mask(irq)); + + spin_unlock_irqrestore(&tx4938_pic_lock, flags); + + return; +} + +static void +tx4938_irq_pic_disable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_pic_lock, flags); + + tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), + tx4938_irq_pic_mask(irq), 0); + + spin_unlock_irqrestore(&tx4938_pic_lock, flags); + + return; +} + +static void +tx4938_irq_pic_mask_and_ack(unsigned int irq) +{ + tx4938_irq_pic_disable(irq); + + return; +} + +static void +tx4938_irq_pic_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + tx4938_irq_pic_enable(irq); + } + + return; +} + +/**********************************************************************************/ +/* Main init functions */ +/**********************************************************************************/ + +void __init +tx4938_irq_init(void) +{ + extern asmlinkage void tx4938_irq_handler(void); + + tx4938_irq_cp0_init(); + tx4938_irq_pic_init(); + set_except_vector(0, tx4938_irq_handler); + + return; +} + +int +tx4938_irq_nested(void) +{ + int sw_irq = 0; + u32 level2; + + level2 = TX4938_RD(0xff1ff6a0); + if ((level2 & 0x10000) == 0) { + level2 &= 0x1f; + sw_irq = TX4938_IRQ_PIC_BEG + level2; + if (sw_irq == 26) { + { + extern int toshiba_rbtx4938_irq_nested(int sw_irq); + sw_irq = toshiba_rbtx4938_irq_nested(sw_irq); + } + } + } + + wbflush(); + return (sw_irq); +} diff --git a/arch/mips/tx4938/common/irq_handler.S b/arch/mips/tx4938/common/irq_handler.S new file mode 100644 index 00000000000..1b2f72bac42 --- /dev/null +++ b/arch/mips/tx4938/common/irq_handler.S @@ -0,0 +1,84 @@ +/* + * linux/arch/mips/tx4938/common/handler.S + * + * Primary interrupt handler for tx4938 based systems + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/regdef.h> +#include <asm/stackframe.h> +#include <asm/tx4938/rbtx4938.h> + + + .align 5 + NESTED(tx4938_irq_handler, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + mfc0 t0, CP0_CAUSE + mfc0 t1, CP0_STATUS + and t0, t1 + + andi t1, t0, STATUSF_IP7 /* cpu timer */ + bnez t1, ll_ip7 + + /* IP6..IP3 multiplexed -- do not use */ + + andi t1, t0, STATUSF_IP2 /* tx4938 pic */ + bnez t1, ll_ip2 + + andi t1, t0, STATUSF_IP1 /* user line 1 */ + bnez t1, ll_ip1 + + andi t1, t0, STATUSF_IP0 /* user line 0 */ + bnez t1, ll_ip0 + + .set reorder + + nop + END(tx4938_irq_handler) + + .align 5 + + +ll_ip7: + li a0, TX4938_IRQ_CPU_TIMER + move a1, sp + jal do_IRQ + j ret_from_irq + + +ll_ip2: + jal tx4938_irq_nested + nop + beqz v0, goto_spurious_interrupt + nop + move a0, v0 + move a1, sp + jal do_IRQ + j ret_from_irq + +goto_spurious_interrupt: + j ret_from_irq + +ll_ip1: + li a0, TX4938_IRQ_USER1 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_ip0: + li a0, TX4938_IRQ_USER0 + move a1, sp + jal do_IRQ + j ret_from_irq diff --git a/arch/mips/tx4938/common/prom.c b/arch/mips/tx4938/common/prom.c new file mode 100644 index 00000000000..3189a65f7d7 --- /dev/null +++ b/arch/mips/tx4938/common/prom.c @@ -0,0 +1,129 @@ +/* + * linux/arch/mips/tx4938/common/prom.c + * + * common tx4938 memory interface + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/bootmem.h> + +#include <asm/addrspace.h> +#include <asm/bootinfo.h> +#include <asm/tx4938/tx4938.h> + +static unsigned int __init +tx4938_process_sdccr(u64 * addr) +{ + u64 val; + unsigned int sdccr_ce; + unsigned int sdccr_rs; + unsigned int sdccr_cs; + unsigned int sdccr_mw; + unsigned int rs = 0; + unsigned int cs = 0; + unsigned int mw = 0; + unsigned int bc = 4; + unsigned int msize = 0; + + val = (*((vu64 *) (addr))); + + /* MVMCP -- need #defs for these bits masks */ + sdccr_ce = ((val & (1 << 10)) >> 10); + sdccr_rs = ((val & (3 << 5)) >> 5); + sdccr_cs = ((val & (7 << 2)) >> 2); + sdccr_mw = ((val & (1 << 0)) >> 0); + + if (sdccr_ce) { + switch (sdccr_rs) { + case 0:{ + rs = 2048; + break; + } + case 1:{ + rs = 4096; + break; + } + case 2:{ + rs = 8192; + break; + } + default:{ + rs = 0; + break; + } + } + switch (sdccr_cs) { + case 0:{ + cs = 256; + break; + } + case 1:{ + cs = 512; + break; + } + case 2:{ + cs = 1024; + break; + } + case 3:{ + cs = 2048; + break; + } + case 4:{ + cs = 4096; + break; + } + default:{ + cs = 0; + break; + } + } + switch (sdccr_mw) { + case 0:{ + mw = 8; + break; + } /* 8 bytes = 64 bits */ + case 1:{ + mw = 4; + break; + } /* 4 bytes = 32 bits */ + } + } + + /* bytes per chip MB per chip bank count */ + msize = (((rs * cs * mw) / (1024 * 1024)) * (bc)); + + /* MVMCP -- bc hard coded to 4 from table 9.3.1 */ + /* boad supports bc=2 but no way to detect */ + + return (msize); +} + +unsigned int __init +tx4938_get_mem_size(void) +{ + unsigned int c0; + unsigned int c1; + unsigned int c2; + unsigned int c3; + unsigned int total; + + /* MVMCP -- need #defs for these registers */ + c0 = tx4938_process_sdccr((u64 *) 0xff1f8000); + c1 = tx4938_process_sdccr((u64 *) 0xff1f8008); + c2 = tx4938_process_sdccr((u64 *) 0xff1f8010); + c3 = tx4938_process_sdccr((u64 *) 0xff1f8018); + total = c0 + c1 + c2 + c3; + + return (total); +} diff --git a/arch/mips/tx4938/common/rtc_rx5c348.c b/arch/mips/tx4938/common/rtc_rx5c348.c new file mode 100644 index 00000000000..d249edbb6af --- /dev/null +++ b/arch/mips/tx4938/common/rtc_rx5c348.c @@ -0,0 +1,202 @@ +/* + * RTC routines for RICOH Rx5C348 SPI chip. + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/rtc.h> +#include <linux/time.h> +#include <asm/time.h> +#include <asm/tx4938/spi.h> + +#define EPOCH 2000 + +/* registers */ +#define Rx5C348_REG_SECOND 0 +#define Rx5C348_REG_MINUTE 1 +#define Rx5C348_REG_HOUR 2 +#define Rx5C348_REG_WEEK 3 +#define Rx5C348_REG_DAY 4 +#define Rx5C348_REG_MONTH 5 +#define Rx5C348_REG_YEAR 6 +#define Rx5C348_REG_ADJUST 7 +#define Rx5C348_REG_ALARM_W_MIN 8 +#define Rx5C348_REG_ALARM_W_HOUR 9 +#define Rx5C348_REG_ALARM_W_WEEK 10 +#define Rx5C348_REG_ALARM_D_MIN 11 +#define Rx5C348_REG_ALARM_D_HOUR 12 +#define Rx5C348_REG_CTL1 14 +#define Rx5C348_REG_CTL2 15 + +/* register bits */ +#define Rx5C348_BIT_PM 0x20 /* REG_HOUR */ +#define Rx5C348_BIT_Y2K 0x80 /* REG_MONTH */ +#define Rx5C348_BIT_24H 0x20 /* REG_CTL1 */ +#define Rx5C348_BIT_XSTP 0x10 /* REG_CTL2 */ + +/* commands */ +#define Rx5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */ +#define Rx5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */ +#define Rx5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */ +#define Rx5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */ + +static struct spi_dev_desc srtc_dev_desc = { + .baud = 1000000, /* 1.0Mbps @ Vdd 2.0V */ + .tcss = 31, + .tcsh = 1, + .tcsr = 62, + /* 31us for Tcss (62us for Tcsr) is required for carry operation) */ + .byteorder = 1, /* MSB-First */ + .polarity = 0, /* High-Active */ + .phase = 1, /* Shift-Then-Sample */ + +}; +static int srtc_chipid; +static int srtc_24h; + +static inline int +spi_rtc_io(unsigned char *inbuf, unsigned char *outbuf, unsigned int count) +{ + unsigned char *inbufs[1], *outbufs[1]; + unsigned int incounts[2], outcounts[2]; + inbufs[0] = inbuf; + incounts[0] = count; + incounts[1] = 0; + outbufs[0] = outbuf; + outcounts[0] = count; + outcounts[1] = 0; + return txx9_spi_io(srtc_chipid, &srtc_dev_desc, + inbufs, incounts, outbufs, outcounts, 0); +} + +/* + * Conversion between binary and BCD. + */ +#ifndef BCD_TO_BIN +#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) +#endif + +#ifndef BIN_TO_BCD +#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) +#endif + +/* RTC-dependent code for time.c */ + +static int +rtc_rx5c348_set_time(unsigned long t) +{ + unsigned char inbuf[8]; + struct rtc_time tm; + u8 year, month, day, hour, minute, second, century; + + /* convert */ + to_tm(t, &tm); + + year = tm.tm_year % 100; + month = tm.tm_mon+1; /* tm_mon starts from 0 to 11 */ + day = tm.tm_mday; + hour = tm.tm_hour; + minute = tm.tm_min; + second = tm.tm_sec; + century = tm.tm_year / 100; + + inbuf[0] = Rx5C348_CMD_MW(Rx5C348_REG_SECOND); + BIN_TO_BCD(second); + inbuf[1] = second; + BIN_TO_BCD(minute); + inbuf[2] = minute; + + if (srtc_24h) { + BIN_TO_BCD(hour); + inbuf[3] = hour; + } else { + /* hour 0 is AM12, noon is PM12 */ + inbuf[3] = 0; + if (hour >= 12) + inbuf[3] = Rx5C348_BIT_PM; + hour = (hour + 11) % 12 + 1; + BIN_TO_BCD(hour); + inbuf[3] |= hour; + } + inbuf[4] = 0; /* ignore week */ + BIN_TO_BCD(day); + inbuf[5] = day; + BIN_TO_BCD(month); + inbuf[6] = month; + if (century >= 20) + inbuf[6] |= Rx5C348_BIT_Y2K; + BIN_TO_BCD(year); + inbuf[7] = year; + /* write in one transfer to avoid data inconsistency */ + return spi_rtc_io(inbuf, NULL, 8); +} + +static unsigned long +rtc_rx5c348_get_time(void) +{ + unsigned char inbuf[8], outbuf[8]; + unsigned int year, month, day, hour, minute, second; + + inbuf[0] = Rx5C348_CMD_MR(Rx5C348_REG_SECOND); + memset(inbuf + 1, 0, 7); + /* read in one transfer to avoid data inconsistency */ + if (spi_rtc_io(inbuf, outbuf, 8)) + return 0; + second = outbuf[1]; + BCD_TO_BIN(second); + minute = outbuf[2]; + BCD_TO_BIN(minute); + if (srtc_24h) { + hour = outbuf[3]; + BCD_TO_BIN(hour); + } else { + hour = outbuf[3] & ~Rx5C348_BIT_PM; + BCD_TO_BIN(hour); + hour %= 12; + if (outbuf[3] & Rx5C348_BIT_PM) + hour += 12; + } + day = outbuf[5]; + BCD_TO_BIN(day); + month = outbuf[6] & ~Rx5C348_BIT_Y2K; + BCD_TO_BIN(month); + year = outbuf[7]; + BCD_TO_BIN(year); + year += EPOCH; + + return mktime(year, month, day, hour, minute, second); +} + +void __init +rtc_rx5c348_init(int chipid) +{ + unsigned char inbuf[2], outbuf[2]; + srtc_chipid = chipid; + /* turn on RTC if it is not on */ + inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL2); + inbuf[1] = 0; + spi_rtc_io(inbuf, outbuf, 2); + if (outbuf[1] & Rx5C348_BIT_XSTP) { + inbuf[0] = Rx5C348_CMD_W(Rx5C348_REG_CTL2); + inbuf[1] = 0; + spi_rtc_io(inbuf, NULL, 2); + } + + inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL1); + inbuf[1] = 0; + spi_rtc_io(inbuf, outbuf, 2); + if (outbuf[1] & Rx5C348_BIT_24H) + srtc_24h = 1; + + /* set the function pointers */ + rtc_get_time = rtc_rx5c348_get_time; + rtc_set_time = rtc_rx5c348_set_time; +} diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c new file mode 100644 index 00000000000..fc992953bf9 --- /dev/null +++ b/arch/mips/tx4938/common/setup.c @@ -0,0 +1,91 @@ +/* + * linux/arch/mips/tx4938/common/setup.c + * + * common tx4938 setup routines + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel_stat.h> +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/timex.h> +#include <linux/slab.h> +#include <linux/random.h> +#include <linux/irq.h> +#include <asm/bitops.h> +#include <asm/bootinfo.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/mipsregs.h> +#include <asm/system.h> +#include <asm/time.h> +#include <asm/time.h> +#include <asm/tx4938/rbtx4938.h> + +extern void toshiba_rbtx4938_setup(void); +extern void rbtx4938_time_init(void); + +void __init tx4938_setup(void); +void __init tx4938_time_init(void); +void __init tx4938_timer_setup(struct irqaction *irq); +void dump_cp0(char *key); + +void (*__wbflush) (void); + +static void +tx4938_write_buffer_flush(void) +{ + mmiowb(); + + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + "lw $0,%0\n\t" + "nop\n\t" + ".set pop" + : /* no output */ + : "m" (*(int *)KSEG1) + : "memory"); +} + +void __init +plat_setup(void) +{ + board_time_init = tx4938_time_init; + board_timer_setup = tx4938_timer_setup; + __wbflush = tx4938_write_buffer_flush; + toshiba_rbtx4938_setup(); +} + +void __init +tx4938_time_init(void) +{ + rbtx4938_time_init(); +} + +void __init +tx4938_timer_setup(struct irqaction *irq) +{ + u32 count; + u32 c1; + u32 c2; + + setup_irq(TX4938_IRQ_CPU_TIMER, irq); + + c1 = read_c0_count(); + count = c1 + (mips_hpt_frequency / HZ); + write_c0_compare(count); + c2 = read_c0_count(); +} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/Makefile b/arch/mips/tx4938/toshiba_rbtx4938/Makefile new file mode 100644 index 00000000000..226941279d7 --- /dev/null +++ b/arch/mips/tx4938/toshiba_rbtx4938/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for common code for Toshiba TX4927 based systems +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +obj-y += prom.o setup.o irq.o spi_eeprom.o spi_txx9.o diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c new file mode 100644 index 00000000000..230f5a93c2e --- /dev/null +++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c @@ -0,0 +1,244 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c + * + * Toshiba RBTX4938 specific interrupt handlers + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +/* +IRQ Device + +16 TX4938-CP0/00 Software 0 +17 TX4938-CP0/01 Software 1 +18 TX4938-CP0/02 Cascade TX4938-CP0 +19 TX4938-CP0/03 Multiplexed -- do not use +20 TX4938-CP0/04 Multiplexed -- do not use +21 TX4938-CP0/05 Multiplexed -- do not use +22 TX4938-CP0/06 Multiplexed -- do not use +23 TX4938-CP0/07 CPU TIMER + +24 TX4938-PIC/00 +25 TX4938-PIC/01 +26 TX4938-PIC/02 Cascade RBTX4938-IOC +27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet +28 TX4938-PIC/04 +29 TX4938-PIC/05 TX4938 ETH1 +30 TX4938-PIC/06 TX4938 ETH0 +31 TX4938-PIC/07 +32 TX4938-PIC/08 TX4938 SIO 0 +33 TX4938-PIC/09 TX4938 SIO 1 +34 TX4938-PIC/10 TX4938 DMA0 +35 TX4938-PIC/11 TX4938 DMA1 +36 TX4938-PIC/12 TX4938 DMA2 +37 TX4938-PIC/13 TX4938 DMA3 +38 TX4938-PIC/14 +39 TX4938-PIC/15 +40 TX4938-PIC/16 TX4938 PCIC +41 TX4938-PIC/17 TX4938 TMR0 +42 TX4938-PIC/18 TX4938 TMR1 +43 TX4938-PIC/19 TX4938 TMR2 +44 TX4938-PIC/20 +45 TX4938-PIC/21 +46 TX4938-PIC/22 TX4938 PCIERR +47 TX4938-PIC/23 +48 TX4938-PIC/24 +49 TX4938-PIC/25 +50 TX4938-PIC/26 +51 TX4938-PIC/27 +52 TX4938-PIC/28 +53 TX4938-PIC/29 +54 TX4938-PIC/30 +55 TX4938-PIC/31 TX4938 SPI + +56 RBTX4938-IOC/00 PCI-D +57 RBTX4938-IOC/01 PCI-C +58 RBTX4938-IOC/02 PCI-B +59 RBTX4938-IOC/03 PCI-A +60 RBTX4938-IOC/04 RTC +61 RBTX4938-IOC/05 ATA +62 RBTX4938-IOC/06 MODEM +63 RBTX4938-IOC/07 SWINT +*/ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/mm.h> +#include <linux/swap.h> +#include <linux/ioport.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/pci.h> +#include <linux/timex.h> +#include <asm/bootinfo.h> +#include <asm/page.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/processor.h> +#include <asm/ptrace.h> +#include <asm/reboot.h> +#include <asm/time.h> +#include <linux/version.h> +#include <linux/bootmem.h> +#include <asm/tx4938/rbtx4938.h> + +static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq); + +DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock); + +#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" +static struct hw_interrupt_type toshiba_rbtx4938_irq_ioc_type = { + .typename = TOSHIBA_RBTX4938_IOC_NAME, + .startup = toshiba_rbtx4938_irq_ioc_startup, + .shutdown = toshiba_rbtx4938_irq_ioc_shutdown, + .enable = toshiba_rbtx4938_irq_ioc_enable, + .disable = toshiba_rbtx4938_irq_ioc_disable, + .ack = toshiba_rbtx4938_irq_ioc_mask_and_ack, + .end = toshiba_rbtx4938_irq_ioc_end, + .set_affinity = NULL +}; + +#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000 +#define TOSHIBA_RBTX4938_IOC_INTR_STAT 0xb7f0200a + +int +toshiba_rbtx4938_irq_nested(int sw_irq) +{ + u8 level3; + + level3 = reg_rd08(TOSHIBA_RBTX4938_IOC_INTR_STAT) & 0xff; + if (level3) { + /* must use fls so onboard ATA has priority */ + sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1; + } + + wbflush(); + return sw_irq; +} + +static struct irqaction toshiba_rbtx4938_irq_ioc_action = { + .handler = no_action, + .flags = 0, + .mask = CPU_MASK_NONE, + .name = TOSHIBA_RBTX4938_IOC_NAME, +}; + +/**********************************************************************************/ +/* Functions for ioc */ +/**********************************************************************************/ +static void __init +toshiba_rbtx4938_irq_ioc_init(void) +{ + int i; + + for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; + i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 3; + irq_desc[i].handler = &toshiba_rbtx4938_irq_ioc_type; + } + + setup_irq(RBTX4938_IRQ_IOCINT, + &toshiba_rbtx4938_irq_ioc_action); +} + +static unsigned int +toshiba_rbtx4938_irq_ioc_startup(unsigned int irq) +{ + toshiba_rbtx4938_irq_ioc_enable(irq); + + return 0; +} + +static void +toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq) +{ + toshiba_rbtx4938_irq_ioc_disable(irq); +} + +static void +toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) +{ + unsigned long flags; + volatile unsigned char v; + + spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags); + + v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); + v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); + mmiowb(); + TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); + + spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags); +} + +static void +toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) +{ + unsigned long flags; + volatile unsigned char v; + + spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags); + + v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); + v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); + mmiowb(); + TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); + + spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags); +} + +static void +toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq) +{ + toshiba_rbtx4938_irq_ioc_disable(irq); +} + +static void +toshiba_rbtx4938_irq_ioc_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + toshiba_rbtx4938_irq_ioc_enable(irq); + } +} + +extern void __init txx9_spi_irqinit(int irc_irq); + +void __init arch_init_irq(void) +{ + extern void tx4938_irq_init(void); + + /* Now, interrupt control disabled, */ + /* all IRC interrupts are masked, */ + /* all IRC interrupt mode are Low Active. */ + + /* mask all IOC interrupts */ + *rbtx4938_imask_ptr = 0; + + /* clear SoftInt interrupts */ + *rbtx4938_softint_ptr = 0; + tx4938_irq_init(); + toshiba_rbtx4938_irq_ioc_init(); + /* Onboard 10M Ether: High Active */ + TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000040); + + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_SPI_SEL) { + txx9_spi_irqinit(RBTX4938_IRQ_IRC_SPI); + } + + wbflush(); +} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/prom.c b/arch/mips/tx4938/toshiba_rbtx4938/prom.c new file mode 100644 index 00000000000..7df8b32ba26 --- /dev/null +++ b/arch/mips/tx4938/toshiba_rbtx4938/prom.c @@ -0,0 +1,78 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c + * + * rbtx4938 specific prom routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include <linux/config.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/bootmem.h> + +#include <asm/addrspace.h> +#include <asm/bootinfo.h> +#include <asm/tx4938/tx4938.h> + +void __init prom_init_cmdline(void) +{ + int argc = (int) fw_arg0; + char **argv = (char **) fw_arg1; + int i; + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) { + *arcs_cmdline = '\0'; + } + + for (i = 1; i < argc; i++) { + if (i != 1) { + strcat(arcs_cmdline, " "); + } + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(void) +{ + extern int tx4938_get_mem_size(void); + int msize; +#ifndef CONFIG_TX4938_NAND_BOOT + prom_init_cmdline(); +#endif + mips_machgroup = MACH_GROUP_TOSHIBA; + mips_machtype = MACH_TOSHIBA_RBTX4938; + + msize = tx4938_get_mem_size(); + add_memory_region(0, msize << 20, BOOT_MEM_RAM); + + return; +} + +unsigned long __init prom_free_prom_memory(void) +{ + return 0; +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ + return; +} + +const char *get_system_type(void) +{ + return "Toshiba RBTX4938"; +} + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c new file mode 100644 index 00000000000..9f1dcc8ca5a --- /dev/null +++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c @@ -0,0 +1,1035 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c + * + * Setup pointers to hardware-dependent routines. + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/ioport.h> +#include <linux/proc_fs.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/console.h> +#include <linux/pci.h> +#include <asm/wbflush.h> +#include <asm/reboot.h> +#include <asm/irq.h> +#include <asm/time.h> +#include <asm/uaccess.h> +#include <asm/io.h> +#include <asm/bootinfo.h> +#include <asm/tx4938/rbtx4938.h> +#ifdef CONFIG_SERIAL_TXX9 +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> +#endif + +extern void rbtx4938_time_init(void) __init; +extern char * __init prom_getcmdline(void); +static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); + +/* These functions are used for rebooting or halting the machine*/ +extern void rbtx4938_machine_restart(char *command); +extern void rbtx4938_machine_halt(void); +extern void rbtx4938_machine_power_off(void); + +/* clocks */ +unsigned int txx9_master_clock; +unsigned int txx9_cpu_clock; +unsigned int txx9_gbus_clock; + +unsigned long rbtx4938_ce_base[8]; +unsigned long rbtx4938_ce_size[8]; +int txboard_pci66_mode; +static int tx4938_pcic_trdyto; /* default: disabled */ +static int tx4938_pcic_retryto; /* default: disabled */ +static int tx4938_ccfg_toeon = 1; + +struct tx4938_pcic_reg *pcicptrs[4] = { + tx4938_pcicptr /* default setting for TX4938 */ +}; + +static struct { + unsigned long base; + unsigned long size; +} phys_regions[16] __initdata; +static int num_phys_regions __initdata; + +#define PHYS_REGION_MINSIZE 0x10000 + +void rbtx4938_machine_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + local_irq_disable(); + + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void rbtx4938_machine_power_off(void) +{ + rbtx4938_machine_halt(); + /* no return */ +} + +void rbtx4938_machine_restart(char *command) +{ + local_irq_disable(); + + printk("Rebooting..."); + *rbtx4938_softresetlock_ptr = 1; + *rbtx4938_sfvol_ptr = 1; + *rbtx4938_softreset_ptr = 1; + wbflush(); + + while(1); +} + +void __init +txboard_add_phys_region(unsigned long base, unsigned long size) +{ + if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { + printk("phys_region overflow\n"); + return; + } + phys_regions[num_phys_regions].base = base; + phys_regions[num_phys_regions].size = size; + num_phys_regions++; +} +unsigned long __init +txboard_find_free_phys_region(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + int i; + + for (base = begin / size * size; base < end; base += size) { + for (i = 0; i < num_phys_regions; i++) { + if (phys_regions[i].size && + base <= phys_regions[i].base + (phys_regions[i].size - 1) && + base + (size - 1) >= phys_regions[i].base) + break; + } + if (i == num_phys_regions) + return base; + } + return 0; +} +unsigned long __init +txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, + unsigned long *size) +{ + unsigned long sz, base; + for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { + base = txboard_find_free_phys_region(begin, end, sz); + if (base) { + *size = sz; + return base; + } + } + return 0; +} +unsigned long __init +txboard_request_phys_region_range(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region(unsigned long size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region_shrink(unsigned long *size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region_shrink(begin, end, size); + if (base) + txboard_add_phys_region(base, *size); + return base; +} + +#ifdef CONFIG_PCI +void __init +tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, + struct pci_controller *channel, + unsigned long pci_io_base, + int extarb) +{ + int i; + + /* Disable All Initiator Space */ + pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| + TX4938_PCIC_PCICCFG_G2PMEN(1)| + TX4938_PCIC_PCICCFG_G2PMEN(2)| + TX4938_PCIC_PCICCFG_G2PIOEN); + + /* GB->PCI mappings */ + pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; + pcicptr->g2piogbase = pci_io_base | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PIOGBASE_ECHG +#else + TX4938_PCIC_G2PIOGBASE_BSDIS +#endif + ; + pcicptr->g2piopbase = 0; + for (i = 0; i < 3; i++) { + pcicptr->g2pmmask[i] = 0; + pcicptr->g2pmgbase[i] = 0; + pcicptr->g2pmpbase[i] = 0; + } + if (channel->mem_resource->end) { + pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; + pcicptr->g2pmgbase[0] = channel->mem_resource->start | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PMnGBASE_ECHG +#else + TX4938_PCIC_G2PMnGBASE_BSDIS +#endif + ; + pcicptr->g2pmpbase[0] = channel->mem_resource->start; + } + /* PCI->GB mappings (I/O 256B) */ + pcicptr->p2giopbase = 0; /* 256B */ + pcicptr->p2giogbase = 0; + /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ + pcicptr->p2gm0plbase = 0; + pcicptr->p2gm0pubase = 0; + pcicptr->p2gmgbase[0] = 0 | + TX4938_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4938_PCIC_P2GMnGBASE_TECHG +#else + TX4938_PCIC_P2GMnGBASE_TBSDIS +#endif + ; + /* PCI->GB mappings (MEM 16MB) */ + pcicptr->p2gm1plbase = 0xffffffff; + pcicptr->p2gm1pubase = 0xffffffff; + pcicptr->p2gmgbase[1] = 0; + /* PCI->GB mappings (MEM 1MB) */ + pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ + pcicptr->p2gmgbase[2] = 0; + + pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; + /* Enable Initiator Memory Space */ + if (channel->mem_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); + /* Enable Initiator I/O Space */ + if (channel->io_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; + /* Enable Initiator Config */ + pcicptr->pciccfg |= + TX4938_PCIC_PCICCFG_ICAEN | + TX4938_PCIC_PCICCFG_TCAR; + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + pcicptr->pcicfg1 = 0; + + pcicptr->g2ptocnt &= ~0xffff; + + if (tx4938_pcic_trdyto >= 0) { + pcicptr->g2ptocnt &= ~0xff; + pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); + } + + if (tx4938_pcic_retryto >= 0) { + pcicptr->g2ptocnt &= ~0xff00; + pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); + } + + /* Clear All Local Bus Status */ + pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; + /* Enable All Local Bus Interrupts */ + pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; + /* Clear All Initiator Status */ + pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; + /* Enable All Initiator Interrupts */ + pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; + /* Clear All PCI Status Error */ + pcicptr->pcistatus = + (pcicptr->pcistatus & 0x0000ffff) | + (TX4938_PCIC_PCISTATUS_ALL << 16); + /* Enable All PCI Status Error Interrupts */ + pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; + + if (!extarb) { + /* Reset Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; + pcicptr->pbabm = 0; + /* Enable Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; + } + + /* PCIC Int => IRC IRQ16 */ + pcicptr->pcicfg2 = + (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; + + pcicptr->pcistatus = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; +} + +int __init +tx4938_report_pciclk(void) +{ + unsigned long pcode = TX4938_REV_PCODE(); + int pciclk = 0; + printk("TX%lx PCIC --%s PCICLK:", + pcode, + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + + switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { + case TX4938_CCFG_PCIDIVMODE_4: + pciclk = txx9_cpu_clock / 4; break; + case TX4938_CCFG_PCIDIVMODE_4_5: + pciclk = txx9_cpu_clock * 2 / 9; break; + case TX4938_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4938_CCFG_PCIDIVMODE_5_5: + pciclk = txx9_cpu_clock * 2 / 11; break; + case TX4938_CCFG_PCIDIVMODE_8: + pciclk = txx9_cpu_clock / 8; break; + case TX4938_CCFG_PCIDIVMODE_9: + pciclk = txx9_cpu_clock / 9; break; + case TX4938_CCFG_PCIDIVMODE_10: + pciclk = txx9_cpu_clock / 10; break; + case TX4938_CCFG_PCIDIVMODE_11: + pciclk = txx9_cpu_clock / 11; break; + } + printk("Internal(%dMHz)", pciclk / 1000000); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) +{ + pcicptrs[ch] = pcicptr; +} + +struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) +{ + return pcicptrs[ch]; +} + +static struct pci_dev *fake_pci_dev(struct pci_controller *hose, + int top_bus, int busnr, int devfn) +{ + static struct pci_dev dev; + static struct pci_bus bus; + + dev.sysdata = (void *)hose; + dev.devfn = devfn; + bus.number = busnr; + bus.ops = hose->pci_ops; + bus.parent = NULL; + dev.bus = &bus; + + return &dev; +} + +#define EARLY_PCI_OP(rw, size, type) \ +static int early_##rw##_config_##size(struct pci_controller *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, word, u16 *) + +int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) +{ + u32 pci_devfn; + unsigned short vid; + int devfn_start = 0; + int devfn_stop = 0xff; + int cap66 = -1; + u16 stat; + + printk("PCI: Checking 66MHz capabilities...\n"); + + for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) { + early_read_config_word(hose, top_bus, current_bus, pci_devfn, + PCI_VENDOR_ID, &vid); + + if (vid == 0xffff) continue; + + /* check 66MHz capability */ + if (cap66 < 0) + cap66 = 1; + if (cap66) { + early_read_config_word(hose, top_bus, current_bus, pci_devfn, + PCI_STATUS, &stat); + if (!(stat & PCI_STATUS_66MHZ)) { + printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n", + current_bus, pci_devfn); + cap66 = 0; + break; + } + } + } + return cap66 > 0; +} + +int __init +tx4938_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; + /* Double PCICLK (if possible) */ + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = + tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK; + switch (pcidivmode) { + case TX4938_CCFG_PCIDIVMODE_8: + case TX4938_CCFG_PCIDIVMODE_4: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4; + pciclk = txx9_cpu_clock / 4; + break; + case TX4938_CCFG_PCIDIVMODE_9: + case TX4938_CCFG_PCIDIVMODE_4_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; + pciclk = txx9_cpu_clock * 2 / 9; + break; + case TX4938_CCFG_PCIDIVMODE_10: + case TX4938_CCFG_PCIDIVMODE_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5; + pciclk = txx9_cpu_clock / 5; + break; + case TX4938_CCFG_PCIDIVMODE_11: + case TX4938_CCFG_PCIDIVMODE_5_5: + default: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; + pciclk = txx9_cpu_clock * 2 / 11; + break; + } + tx4938_ccfgptr->ccfg = + (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) + | pcidivmode; + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)tx4938_ccfgptr->ccfg); + } else { + pciclk = -1; + } + return pciclk; +} + +extern struct pci_controller tx4938_pci_controller[]; +static int __init tx4938_pcibios_init(void) +{ + unsigned long mem_base[2]; + unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ + unsigned long io_base[2]; + unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ + /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ + int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); + + PCIBIOS_MIN_IO = 0x00001000UL; + PCIBIOS_MIN_MEM = 0x01000000UL; + + mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); + io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); + + printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + (unsigned short)(tx4938_pcicptr->pciid >> 16), + (unsigned short)(tx4938_pcicptr->pciid & 0xffff), + (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), + extarb ? "External" : "Internal"); + + /* setup PCI area */ + tx4938_pci_controller[0].io_resource->start = io_base[0]; + tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; + tx4938_pci_controller[0].mem_resource->start = mem_base[0]; + tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; + + set_tx4938_pcicptr(0, tx4938_pcicptr); + + register_pci_controller(&tx4938_pci_controller[0]); + + if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { + printk("TX4938_CCFG_PCI66 already configured\n"); + txboard_pci66_mode = -1; /* already configured */ + } + + /* Reset PCI Bus */ + *rbtx4938_pcireset_ptr = 0; + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + if (txboard_pci66_mode > 0) + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + *rbtx4938_pcireset_ptr = 1; + wbflush(); + tx4938_report_pcic_status1(tx4938_pcicptr); + + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + if (txboard_pci66_mode == 0 && + txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { + /* Reset PCI Bus */ + *rbtx4938_pcireset_ptr = 0; + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + *rbtx4938_pcireset_ptr = 1; + wbflush(); + /* Reinitialize PCIC */ + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + } + + mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); + io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); + /* Reset PCIC1 */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; + /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ + if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; + else + tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; + mdelay(10); + /* clear PCIC1 reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + tx4938_report_pcic_status1(tx4938_pcic1ptr); + + printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", + (unsigned short)(tx4938_pcic1ptr->pciid >> 16), + (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), + (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); + printk("%s PCICLK:%dMHz\n", + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", + txx9_gbus_clock / + ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / + 1000000); + + /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ + tx4938_pci_controller[1].io_resource->start = + io_base[1] - io_base[0]; + tx4938_pci_controller[1].io_resource->end = + io_base[1] - io_base[0] + io_size[1] - 1; + tx4938_pci_controller[1].mem_resource->start = mem_base[1]; + tx4938_pci_controller[1].mem_resource->end = + mem_base[1] + mem_size[1] - 1; + set_tx4938_pcicptr(1, tx4938_pcic1ptr); + + register_pci_controller(&tx4938_pci_controller[1]); + + tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); + + /* map ioport 0 to PCI I/O space address 0 */ + set_io_port_base(KSEG1 + io_base[0]); + + return 0; +} + +arch_initcall(tx4938_pcibios_init); + +#endif /* CONFIG_PCI */ + +/* SPI support */ + +/* chip select for SPI devices */ +#define SEEPROM1_CS 7 /* PIO7 */ +#define SEEPROM2_CS 0 /* IOC */ +#define SEEPROM3_CS 1 /* IOC */ +#define SRTC_CS 2 /* IOC */ + +static int rbtx4938_spi_cs_func(int chipid, int on) +{ + unsigned char bit; + switch (chipid) { + case RBTX4938_SEEPROM1_CHIPID: + if (on) + tx4938_pioptr->dout &= ~(1 << SEEPROM1_CS); + else + tx4938_pioptr->dout |= (1 << SEEPROM1_CS); + return 0; + break; + case RBTX4938_SEEPROM2_CHIPID: + bit = (1 << SEEPROM2_CS); + break; + case RBTX4938_SEEPROM3_CHIPID: + bit = (1 << SEEPROM3_CS); + break; + case RBTX4938_SRTC_CHIPID: + bit = (1 << SRTC_CS); + break; + default: + return -ENODEV; + } + /* bit1,2,4 are low active, bit3 is high active */ + *rbtx4938_spics_ptr = + (*rbtx4938_spics_ptr & ~bit) | + ((on ? (bit ^ 0x0b) : ~(bit ^ 0x0b)) & bit); + return 0; +} + +#ifdef CONFIG_PCI +extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); + +int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr) +{ + struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata; + static unsigned char dat[17]; + static int read_dat = 0; + int ch = 0; + + if (channel != &tx4938_pci_controller[1]) + return -ENODEV; + /* TX4938 PCIC1 */ + switch (PCI_SLOT(dev->devfn)) { + case TX493