From 1938de46cb7e108120ffbf5155678a2a5e05b377 Mon Sep 17 00:00:00 2001 From: Mike Hench Date: Wed, 19 Mar 2008 12:40:15 -0500 Subject: [MTD] [NAND] corrected MPC8313 NAND fixes Fix a race condition in fsl_elbc_run_command Fix incorrect usage of clearbits32 that bashed option register Remove work around for bashed register Signed-off-by: Mike Hench Acked-by: Scott Wood Signed-off-by: David Woodhouse --- drivers/mtd/nand/fsl_elbc_nand.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index cb12b67ce5e..919c192b8f2 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -184,11 +184,11 @@ static int fsl_elbc_run_command(struct mtd_info *mtd) in_be32(&lbc->fbar), in_be32(&lbc->fpar), in_be32(&lbc->fbcr), priv->bank); + ctrl->irq_status = 0; /* execute special operation */ out_be32(&lbc->lsor, priv->bank); /* wait for FCM complete flag or timeout */ - ctrl->irq_status = 0; wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, FCM_TIMEOUT_MSECS * HZ/1000); ctrl->status = ctrl->irq_status; @@ -667,7 +667,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) /* adjust Option Register and ECC to match Flash page size */ if (mtd->writesize == 512) { priv->page_size = 0; - clrbits32(&lbc->bank[priv->bank].or, ~OR_FCM_PGS); + clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); } else if (mtd->writesize == 2048) { priv->page_size = 1; setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); @@ -688,11 +688,6 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) return -1; } - /* The default u-boot configuration on MPC8313ERDB causes errors; - * more delay is needed. This should be safe for other boards - * as well. - */ - setbits32(&lbc->bank[priv->bank].or, 0x70); return 0; } -- cgit v1.2.3-18-g5258