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path: root/drivers/usb/phy/phy-omap-usb3.c
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2013-10-03usb: phy: omap-usb3: Don't use omap_get_control_dev()Roger Quadros
omap_get_control_dev() is being deprecated as it doesn't support multiple instances. As control device is present only from OMAP4 onwards which supports DT only, we use phandles to get the reference to the control device. As we don't support non-DT boot, we just bail out on probe if device node is not present. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-10-03usb: phy: omap: Add new device types and remove omap_control_usb3_phy_power()Roger Quadros
Add support for new device types and in the process rid of "ti,type" device tree property. The correct type of device will be determined from the compatible string instead. Introduce a compatible string for each device type. At the moment we support 4 types OTGHS, USB2, PIPE3 (e.g. USB3) and DRA7USB2. Update DT binding information to reflect these changes. Also get rid of omap_control_usb3_phy_power(). Just one function i.e. omap_control_usb_phy_power() will now take care of all PHY types. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-09-17usb: phy: omap-usb3: Fix return valueSachin Kamat
The function returns a pointer. Hence return NULL instead of 0. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-07-29usb: phy: omap-usb3: Improve DPLL parameter lookup codeRoger Quadros
Use a mapping table (dpll_map) to match the possible system clock rates to the appropriate DPLL parameters. Introduce a function "omap_usb3_get_dpll_params()" that will return the matching DPLL parameters for the given clock rate. Also, bail out on phy init if DPLL locking fails. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-07-15usb: phy: omap-usb3: fix dpll clock indexRuchika Kharwar
Correction of the omap_usb3_dpll_params array when the sys_clk_rate is 20MHz. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Ruchika Kharwar <ruchika@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-06-01usb: phy: omap-usb3: updated dpll M,N values to support DRA7xx devicesRuchika Kharwar
Addition of the M and N recommended values for the USB3 PHY DPLL. Sysclk for DRA7xx is 20MHz. This yields: Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz Signed-off-by: Ruchika Kharwar <ruchika@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-03-18usb: phy: rename all phy drivers to phy-$name-usb.cFelipe Balbi
this will make sure that we have sensible names for all phy drivers. Current situation was already quite bad with too generic names being used. Signed-off-by: Felipe Balbi <balbi@ti.com>