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path: root/drivers/gpu/drm/nouveau
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2012-03-13drm/nvd0/disp: fix dcb sor link matching in supervisor handlerBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: initial implementation of displayportBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: make dp dpms function common, call from sor code insteadBen Skeggs
GF119 will use this too. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/hwsq: some nv92 fixesMartin Peres
The shift from hwsq_data = 0x1400 to 0x080000 actually happened in nv94, not nv92 This fixes some reclocking issues on my newly acquired nv92 Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: move all nv50/sor-specific code out of nouveau_dp.cBen Skeggs
Off-chip encoders (which we don't support yet anyway), and newer chipsets (such as NVD9...), will need their own code for this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: make functions for executing various bios tablesBen Skeggs
More code to do the same thing, but will make it easier to handle various changes that could possibly happen the the VBIOS tables. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: fix oops if chipset has no pm support at allBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/bios: rework vbios shadowingBen Skeggs
Refactored to allow shadowing of VBIOS images longer than 64KiB, which allows us to pass the VBIOS checksum test on certain boards. There's also a workaround for reading the PROM VBIOS on some chipsets. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/bios: attempt acpi rom fetch before pciromBen Skeggs
There's cards out there with completely messed up PCIROM images that have a perfectly valid signature.. Sigh! Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: attempt to handle more than 2 crtcs if possibleBen Skeggs
Theoretically handles CRTC2/CRTC3, should any GF119 out there actually have them enabled. The room is there for the regs etc, so why not :) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvc0/vram: get part count from PUNITSBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv40/pm: fix fanspeed regressionBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: several fixes for nvc0 memory timingsRoy Spliet
This patch fixes two small issues in timing generation as spotted on several NVCx cards. In addition, the header of the file is updated to also contain (some of) the current developers of this code. Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvc0/pm: restrict pll mode to clocks that can actually use itBen Skeggs
Fixes reclocking failure on some chips where we attempted to set PDAEMON to PLL mode. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: fix bad comparison in dp_link_train_commit()Xi Wang
The comparison (lpre == DP_TRAIN_PRE_EMPHASIS_9_5) is always false: lpre is initialized as (lane & 0x0c) >> 2, which is at most 3, while DP_TRAIN_PRE_EMPHASIS_9_5 is defined as (3 << 3). Signed-off-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/mxm: call mxmi to determine revision before calling mxmsBen Skeggs
There's a HP laptop out there where the MXM version in the VBIOS doesn't match what the ACPI implementation is expecting. These tables will accept 0x00 to MXMS to return latest version, but *only* if MXMI has been called first.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: init only after display subsystem has been createdBen Skeggs
This patch fixes an oops cause by pm_trigger accessing the (uninitialised) crtc list. Reported-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvc0/fb: detect presense of second rankBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/display: expose color vibrance controlChristoph Bumiller
Signed-off-by: Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50-nvc0/vm: support unsnooped system memoryBen Skeggs
v2 (Emil Velikov <emil.l.velikov@gmail.com>): - Fixed a regression on certain nv50 IGP due to not passing the correct target type to nv50_vm_addr() Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Tested-by: Johannes Obermayr <johannesobermayr@gmx.de>
2012-03-13drm/nouveau: recognise DCB connector type for DP+DVI+VGA DMS-59Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/mem: handle dll_off for ddr2/ddr3Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: extend profile interface for destroy/init/finiBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: rework to allow selecting separate profiles for ac/batteryBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: fix dll off -> dll on transitionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: detect when we need dll disabled for gddr3Ben Skeggs
Fixes minor flickering on NVS295 when at perflvl 0. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50: fix detection of second vram rankBen Skeggs
Goes a long way to correcting NVS295 memory reclocking issues. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: track mr2 for gddr3Ben Skeggs
There's some "extended" GDDR3 chipsets out there with EMRS2 settings that change the layout of MRS/EMRS1 bitmaps.. Sigh.. Still need to track down how exactly we're supposed to handle this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/pm: wait for all fifo-connected engines to idle before reclockingMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/pm: use hwsq for engine reclocking tooBen Skeggs
Idea from Martin Peres, different implementation by me. v2: Martin Peres: - fix mast calculation Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/disp: more accurate function to determine active crtcsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/pm: initial work towards proper memory reclocking, with timingsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: introduce ram reclocking helperBen Skeggs
This will probably result in more lines of code, however, we're going to have at least 3 slightly different implementations of this very soon and I'd rather keep the ram reclocking logic separate from the hw specifics. DDR2/DDR3/GDDR3 implemented thus far, others will be added as necessary. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: embed timings into perflvl structsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: calculate memory timings at perflvl creation timeBen Skeggs
Statically generating the PFB register and MR values for each timing set turns out to be insufficient. There's at least one (so far) known piece of information which effects MR values which is stored in the perflvl entry on some chipsets (and in another table on later ones), which is disconnected from the timing table entries. After this change we will generate a timing set based on an input clock frequency instead, and have this data stored in the performance level data. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: readback boot perflvl *before* parsing vbiosBen Skeggs
We might want/need the boot data to generate the other perflevels. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validationRoy Spliet
Roy Spliet: - Implement according to specs - Simplify - Make array for mc latency registers Martin Peres: - squash and split all the commits from Roy - rework following Ben Skeggs comments - add a form of timings validation - store the initial timings for later use Ben Skeggs - merge slightly modified tidy-up patch with this one - remove perflvl-dropping logic for the moment Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: restructure bios table parsingBen Skeggs
It turns out we need access to some additional information in various VBIOS tables to handle PFB memory timings correctly. Rather than hack in parsing of the new stuff in some kludgy way, I've restructured the VBIOS parsing to be more primitive, so we can use them in more flexible ways in the future. The perflvl->timing association code is disabled for the moment until it can be reworked. We don't use this stuff yet anyway, so no harm done. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: avoid potential divide-by-zeroBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau: Fix module parameter description formatsJean Delvare
Module parameter descriptions don't take a trailing \n, otherwise it breaks formatting of modinfo's output. Also remove trailing space. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: David Airlie <airlied@linux.ie> Cc: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: improve memory timing generationRoy Spliet
- Rename several VBIOS entries to closer match the real world - Add the missing 0x100238 and 0x100240 register values - Parse bit 14 of the VBIOS timing table - "Magic value" -> tCWL, fixing some minor bugs in the process - Also name a few more by their name rather than their number. - Some values seem to be dependent on the memory type. Fix Edits by Martin Peres <martin.peres@labri.fr>: - this is a squash commit - reworked for fixing some style issues Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: improve the reclocking logs' readabilityMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau: move pwm_divisor to the nouveau_pm_fan structMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: restore fan speed after suspendMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: style fixesMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau: rework the init/takedown orderingBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvc0: add initial memory type detectionBen Skeggs
Uses only the VBIOS tables, from what I can tell this is what NVIDIA do too, I was able to change the detected memory type by modifying this table on a NVC1 chipset. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50: hopefully handle the DDR2/DDR3 memtype detection somewhat betterBen Skeggs
M version 2 appears to have a table with some form of memory type info available. NVIDIA appear to ignore the table information except for this DDR2/DDR3 case (which has the same value in 0x100714). My guess is this is due to some of the supported memory types not being represented in the table. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50: add memory type detectionBen Skeggs
DDR1/DDR[23] confirmed on NVA8 (see note about DDR3 in source) by changing the value and watching the binary driver's behaviour. GDDR3/4 values confirmed on a NV96 via the same method above. That GDDR4 is present is interesting, as far as I can see no boards using it were ever released. GDDR5 value is based on VBIOS images of known GDDR5 boards. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv20-nv40: add memory type detectionBen Skeggs
NV20/NV30 is partially educated guesswork at this point, based on any information around about available memory types and a horribly unspeakable amount of vbios image scouring. I'm not entirely certain the GDDR3 define is correct, I have not spotted a single vbios with that value yet (though it is mentioned in some 1218-using nv4x vbios), but there are reports that some nv3x did use it.. NV40(100914) confirmed by switching an NV49 to DDR1/DDR2 values and making sure that the binary driver behaviour showed it had detected DDR1/DDR2 instead of GDDR3 before dying horribly. NV40(100474) confirmed by doing much the same task as above on an NV44, except this was *much* easier as changing the values didn't seem to have any noticable effect on the memory controller aside from changing the binary driver's behaviour. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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