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path: root/drivers/gpu/drm/i915/intel_ringbuffer.c
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2010-11-23drm/i915: Use drm_i915_gem_object as the preferred typeChris Wilson
A glorified s/obj_priv/obj/ with a net reduction of over a 100 lines and many characters! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-11Revert "drm/i915/ringbuffer: Ignore failure to setup the ring on Sandybridge"Chris Wilson
This reverts commit 629e894173c9de589913cf649deaadec4b0579bd.
2010-11-11drm/i915/ringbuffer: set FORCE_WAKE bit before reading ring registerZou Nan hai
Before reading ring register, set FORCE_WAKE bit to prevent GT core power down to low power state, otherwise we may read stale values. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> [ickle: added a udelay which seemed to do the trick on my SNB] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-08drm/i915/ringbuffer: Use the HEAD auto-reporting mechanismChris Wilson
My Sandybridge only reports 0 for the ring buffer registers, causing it to hang as soon as we exhaust the available ring. As a workaround, take advantage of our huge ring buffers and use the auto-reporting mechanism to update the status page with the HEAD location every 64 KiB. Cherry-picked from 6aa56062eaba67adfb247cded244fd877329588d. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31404 Tested-by: Zhao Jian <jian.j.zhao@intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-07drm/i915/ringbuffer: Ignore failure to setup the ring on SandybridgeChris Wilson
The ring buffer registers return 0 whilst idle (for some values of idle) on early Sandybridge hw. Persevere even when all appears hopeless... Fortunately the head auto-reporting prevents most hangs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31370 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-07drm/i915/ringbuffer: Be consistent in use of ring->size when initialisingChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-04drm/i915: kill mappable/fenceable disdinctionDaniel Vetter
a00b10c360b35d6431a "Only enforce fence limits inside the GTT" also added a fenceable/mappable disdinction when binding/pinning buffers. This only complicates the code with no pratical gain: - In execbuffer this matters on for g33/pineview, as this is the only chip that needs fences and has an unmappable gtt area. But fences are only possible in the mappable part of the gtt, so need_fence implies need_mappable. And need_mappable is only set independantly with relocations which implies (for sane userspace) that the buffer is untiled. - The overlay code is only really used on i8xx, which doesn't have unmappable gtt. And it doesn't support tiled buffers, currently. - For all other buffers it's a bug to pass in a tiled bo. In short, this disdinction doesn't have any practical gain. I've also reverted mapping the overlay and context pages as possibly unmappable. It's not worth being overtly clever here, all the big gains from unmappable are for execbuf bos. Also add a comment for a clever optimization that confused me while reading the original patch by Chris Wilson. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-02drm/i915: Drop the iomem accessors when writing to the kmapped blt batchChris Wilson
I presumed that we would be writing to the batch through the GTT having bound it, so I converted it to use iomem. Even later as I spotted that we didn't even move the batch to the GTT (now an issue since we default to uncached memory on SNB) I still didn't realise that using iomem for kmapped memory was incorrect. Fix it. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-02drm/i915: SNB BLT workaroundChris Wilson
On some stepping of SNB cpu, the first command to be parsed in BLT command streamer should be MI_BATCHBUFFER_START otherwise the GPU may hang. (cherry picked from commit 8d19215be8254f4f75e9c5a0d28345947b0382db) Conflicts: drivers/gpu/drm/i915/intel_ringbuffer.c drivers/gpu/drm/i915/intel_ringbuffer.h Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-02drm/i915: SNB BLT workaroundZou Nan hai
On some stepping of SNB cpu, the first command to be parsed in BLT command streamer should be MI_BATCHBUFFER_START otherwise the GPU may hang. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> [ickle: rebased for -next] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29drm/i915/ringbuffer: Use the HEAD auto-reporting mechanismChris Wilson
My Sandybridge only reports 0 for the ring buffer registers, causing it to hang as soon as we exhaust the available ring. As a workaround, take advantage of our huge ring buffers and use the auto-reporting mechanism to update the status page with the HEAD location every 64 KiB. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29drm/i915: Check if the GPU hung whilst waiting for the ring to clearChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29drm/i915/ringbuffer: Remove duplicate initialisation of ring controlChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29drm/i915/ringbuffer: Disable the ringbuffer on cleanup.Chris Wilson
It should be idle on cleanup anyway... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29drm/i915: Only enforce fence limits inside the GTT.Chris Wilson
So long as we adhere to the fence registers rules for alignment and no overlaps (including with unfenced accesses to linear memory) and account for the tiled access in our size allocation, we do not have to allocate the full fenced region for the object. This allows us to fight the bloat tiling imposed on pre-i965 chipsets and frees up RAM for real use. [Inside the GTT we still suffer the additional alignment constraints, so it doesn't magic allow us to render larger scenes without stalls -- we need the expanded GTT and fence pipelining to overcome those...] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-28drm/i915/ringbuffer: Check that we setup the ringbufferChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27drm/i915: range-restricted bind_to_gttDaniel Vetter
Like before add a parameter mappable (also to gem_object_pin) and set it depending upon the context. Only bos that are brought into the gtt due to an execbuffer call can be put into the unmappable part of the gtt, everything else (especially pinned objects) need to be put into the mappable part of the gtt. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27drm/i915: Propagate error from failing to queue a requestChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27drm/i915: Propagate errors from writing to ringbufferChris Wilson
Preparing the ringbuffer for adding new commands can fail (a timeout whilst waiting for the GPU to catch up and free some space). So check for any potential error before overwriting HEAD with new commands, and propagate that error back to the user where possible. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27drm/i915/ringbuffer: Drop the redundant dev from the vfunc interfaceChris Wilson
The ringbuffer keeps a pointer to the parent device, so we can use that instead of passing around the pointer on the stack. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-24drm/i915: Move gpu_write_list to per-ringChris Wilson
... to prevent flush processing of an idle (or even absent) ring. This fixes a regression during suspend from 87acb0a5. Reported-and-tested-by: Alexey Fisher <bug-track@fisher-privat.net> Tested-by: Peter Clifton <pcjc2@cam.ac.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-22drm/i915/ringbuffer: Write the value passed in to the tail registerChris Wilson
This should fix the error along the reset path were we tried to clear the tail register by setting it to 0, but were in fact setting it to the current value and complaining when it did not reset to 0. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-21drm/i915: IS_IRONLAKE is synonymous with gen == 5Chris Wilson
So remove the redundant bit in the capabilities block and s/IS_IRONLAKE/IS_GEN5/. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-21drm/i915: Enable SandyBridge blitter ringChris Wilson
Based on an original patch by Zhenyu Wang, this initializes the BLT ring for SandyBridge and enables support for user execbuffers. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-21drm/i915/ringbuffer: Remove broken intel_fill_struct()Chris Wilson
... before someone tries to use it. The code both calls intel_ring_begin/advance() and open-codes the bookkeeping performed by those two functions. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-21drm/i915/ringbuffer: Fix emit batch buffer regression from 8187a2bChris Wilson
In commit 8187a2b, the number of dwords used in the ringbuffer for executing the batch buffer was erroneously changed from 2 to 4. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-19drm/i915: Sleep whilst waiting for the ringChris Wilson
If userspace is submitting so many long running batches that the ring becomes full, throttle by sleeping for a 1ms before checking for free space. Simply yielding was causing excessive scheduler overhead whilst making no progress. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-30drm/i915/debug: Convert i915_verify_active() to scan all listsChris Wilson
... and check more regularly. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-25drm/i915: kill ring->setup_status_pageDaniel Vetter
It's the same code, essentially, so kill all copies safe one unified version. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-25drm/i915: kill ring->get_active_headDaniel Vetter
All functions are extremely similar, so fold them into one generic implementation. This function isn't used anyway, because there's not yet a bsd ring error state dumper. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-25drm/i915: kill per-ring macrosDaniel Vetter
Two macros that use a base address for HWS_PGA were missing, add them. Also switch the remaining users of *_ACTHD to the ring-base one. Kill the other ring-specific macros because they're now unused. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [ickle: And silence checkpatch whilst in the vicinity] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-25drm/i915: fix ACTHD for gen <= 3Daniel Vetter
This was mixed up in the following patch: commit a6c45cf013a57e32ddae43dd4ac911eb4a3919fd Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Fri Sep 17 00:32:17 2010 +0100 drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965g Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-24drm/i915: Only hold a process-local lock whilst throttling.Chris Wilson
Avoid cause latencies in other clients by not taking the global struct mutex and moving the per-client request manipulation a local per-client mutex. For example, this allows a compositor to schedule a page-flip (through X) whilst an OpenGL application is monopolising the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915/ringbuffer: whitespace cleanupChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: drop alignment ringbuffer parameterDaniel Vetter
Always PAGE_SIZE and only complicates the code. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: don't explicitly initialize ringbuffer members to zeroDaniel Vetter
The compiler happily does that for us. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: use new macros to access the ring ctl registerDaniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: use new macros to access the ring head registerDaniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: use new macros to access the ring start registerDaniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: use new macros to access the ring tail registerDaniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: add relative ring register macrosDaniel Vetter
Documentation explicitly mentions that the ring registers are designed to have the same offsets relative to a base registers. Use this to fight the code beaurocratic in intel_ringbuffer.c. No code changes in this patch, just the new definitions. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915/ringbuffer: Mark the initialisation structs as constant.Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: add a new BSD ring buffer for SandybridgeXiang, Haihao
This ring buffer is used for video decoding/encoding on Sandybridge. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915/ringbuffer: Implement advance using set_tailChris Wilson
As noted by Zhenyu, we can now simply replace the existing advance hook by calling the new set_tail function pointer directly. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: add set_tail hook in struct intel_ring_bufferXiang, Haihao
This is prepared for video codec ring buffer on Sandybridge. It is needed to read/write more than one register to move the tail pointer of the video codec ring on Sandybridge. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: do not export the instances of struct intel_ring_bufferXiang, Haihao
Introduce intel_init_render_ring_buffer(), intel_init_bsd_ring_buffer for ring initialization. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: Only emit a flush request on the active ring.Chris Wilson
When flushing the GPU domains,we emit a flush on *both* rings, even though they share a unified cache. Only emit the flush on the currently active ring. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965gChris Wilson
Avoid confusion between i965g meaning broadwater and the gen4+ chipset families. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14drm/i915: Remove unused intel_ringbuffer->ring_flagChris Wilson
This can always be re-added should somebody find a use... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08drm/i915: move flushing list processing to i915_retire_commandsDaniel Vetter
... instead of threading flush_domains through the execbuf code to i915_add_request. With this change 2 small cleanups are possible (likewise the majority of the patch): - The flush_domains parameter of i915_add_request is always 0. Drop it and the corresponding logic. - Ditto for the seqno param of i915_gem_process_flushing_list. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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