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path: root/drivers/gpu/drm/i915/intel_display.c
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2011-05-09drm/i915: fix intel_crtc_clock_get pipe reads after "cleanup cleanup"Chris Wilson
Despite the fixes in 548f245ba6a31 (drm/i915: fix per-pipe reads after "cleanup"), we missed one neighbouring read that was mistakenly replaced with the reg value in 9db4a9c (drm/i915: cleanup per-pipe reg usage). This was preventing us from correctly determining the mode the BIOS left the panel in for machines that neither have an OpRegion nor access to the VBT, (e.g. the EeePC 700). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-09drm/i915: Only enable the plane after setting the fb base (pre-ILK)Chris Wilson
When enabling the plane, it is helpful to have already pointed that plane to valid memory or else we may incur the wrath of a PGTBL_ER. This code preserved the behaviour from the bad old days for unknown reasons... Found by assert_fb_bound_for_plane(). References: https://bugs.freedesktop.org/show_bug.cgi?id=36246 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-04drm/i915: Release object along create user fb error pathChris Wilson
Reported-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org Signed-off-by: Keith Packard <keithp@keithp.com>
2011-04-28drm: Verify debug message argumentsJoe Perches
Add __attribute__((format (printf, 4, 5))) to drm_ut_debug_printk and fix fallout. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-13drm/i915: Initialise g4x watermarks for disabled pipesChris Wilson
We were using uninitialised watermarks values for disabled pipes which were combined into a single WM register and so corrupting the values for the enabled pipe and upsetting the display hardware. Reported-by: Riccardo Magliocchetti <riccardo.magliocchetti@gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=32612 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-04-12drm/i915: Sanitize the output registers after resumeChris Wilson
Similar to booting, we need to inspect the state left by the BIOS and remove any conflicting bits before we take over. The example reported by Seth Forshee is very similar to the bug we encountered with the state left by grub2, that the crtc pipe<->planning mapping was reversed from our expectations and so we failed to turn off the outputs when booting or, in this case, resuming. This may be in fact the same bug, but triggered at resume time. This patch rearranges the code we already have to clear up the conflicting state upon init and calls it from reset (which is called after we have lost control of the hardware, i.e. along both the boot and resume paths) instead. Reported-and-tested-by: Seth Forshee <seth.forshee@canonical.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35796 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-03-23drm/i915: report correct render clock frequencies on SNBJesse Barnes
Fix up the debug file to report the right frequencies. On SNB, we program the PCU with a frequency ratio, which is multiplied by 100MHz on the CPU side. But GFX only runs at half that, so report it as such to avoid confusion. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Keith Packard <keithp@keithp.com>
2011-03-23drm/i915: Re-enable self-refreshYuanhan Liu
A broken implementation of is_pot() prevented the detection of when a singular pipe was enabled. Eric Anholt pointed out the existence of is_power_of_2() so use that instead of our broken code! Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35402 Signed-off-by: Yuanhan Liu <yuanhan.liu@intel.com> Tested-by: xunx.fang@intel.com Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-23drm/i915: skip redundant operations whilst enabling pipes and planesChris Wilson
If the pipe or plane is already enabled, then we do not need to enable it again and can skip the delay. Similarly if it is already disabled when we want to disable it, we can also skip it. This fixes a regression from b24e717988, which caused the LVDS output on one PineView machine to become corrupt after changing orientation several times. References: https://bugs.freedesktop.org/show_bug.cgi?id=34601 Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Keith Packard <keithp@keithp.com> Tested-by: mengmeng.meng@intel.com
2011-03-23drm/i915: Remove surplus POSTING_READs before wait_for_vblankChris Wilson
... as wait_for_vblank (and friends) will do a flush of the MMIO writes anyway. References: https://bugs.freedesktop.org/show_bug.cgi?id=34601 Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Keith Packard <keithp@keithp.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-03-07Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
Apply the trivial conflicting regression fixes, but keep GPU semaphores enabled. Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem_execbuffer.c
2011-03-06drm/i915: Do not overflow the MMADDR write FIFOChris Wilson
Whilst the GT is powered down (rc6), writes to MMADDR are placed in a FIFO by the System Agent. This is a limited resource, only 64 entries, of which 20 are reserved for Display and PCH writes, and so we must take care not to queue up too many writes. To avoid this, there is counter which we can poll to ensure there are sufficient free entries in the fifo. "Issuing a write to a full FIFO is not supported; at worst it could result in corruption or a system hang." Reported-and-Tested-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34056 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-01Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
2011-02-24drm/i915: Fix unintended recursion in ironlake_disable_rc6Chris Wilson
After disabling, we're meant to teardown the bo used for the contexts, not recurse into ourselves again and preventing module unload. Reported-and-tested-by: Ben Widawsky <bwidawsk@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22drm/i915: Use a device flag for non-interruptible phasesChris Wilson
The code paths for modesetting are growing in complexity as we may need to move the buffers around in order to fit the scanout in the aperture. Therefore we face a choice as to whether to thread the interruptible status through the entire pinning and unbinding code paths or to add a flag to the device when we may not be interrupted by a signal. This does the latter and so fixes a few instances of modesetting failures under stress. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22drm/i915: Protect against drm_gem_object not being the first memberChris Wilson
Dave Airlie spotted that we had a potential bug should we ever rearrange the drm_i915_gem_object so not the base drm_gem_object was not its first member. He noticed that we often convert the return of drm_gem_object_lookup() immediately into drm_i915_gem_object and then check the result for nullity. This is only valid when the base object is the first member and so the superobject has the same address. Play safe instead and use the compiler to convert back to the original return address for sanity testing. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22drm/i915: fix per-pipe reads after "cleanup"Jesse Barnes
In a few places I replaced reads of per-pipe registers with the actual register offsets themselves (converting I915_READ(reg) to _PIPE(reg)). Alexey caught this on his 9xx machine because the cursor control write was affected. A quick audit showed a few more places where I'd borked a read, so here's a patch to fix things up. Reported-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: compilation fix] Tested-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22Revert "drm/i915: Disable SSC for outputs other than LVDS or DP"Chris Wilson
This reverts commit 633f2ea26665d37bb3c8ae30799aa14988622653 and the attempted fix dcbe6f2b3d136995915e2f9ecc7d4f3b28f47b6c. There is a single clock source used for both SSC (some LVDS and DP) and non-SSC (VGA, DVI) outputs. So we need to be careful to only enable SSC as necessary. However, fiddling with DREFCLK was causing DP links to be dropped and we do not have a fix ready, so revert. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22drm/i915: skip FDI & PCH enabling for DP_AJesse Barnes
eDP on the CPU doesn't need the PCH set up at all, it can in fact cause problems. So avoid FDI training and PCH PLL enabling in that case. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Andy Whitcroft <apw@canonical.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22drm/i915: Ignore a hung GPU when flushing the framebuffer prior to a switchChris Wilson
If the gpu is hung, then whatever was inside the render cache is lost and there is little point waiting for it. Or complaining if we see an EIO or EAGAIN instead. So, if the GPU is indeed in its death throes when we need to rewrite the registers for a new framebuffer, just ignore the error and proceed with the update. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-16Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
Grab the latest stabilisation bits from -fixes and some suspend and resume fixes from linus. Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_irq.c
2011-02-16drm/i915: Ignore a hung GPU when flushing the framebuffer prior to a switchChris Wilson
If the gpu is hung, then whatever was inside the render cache is lost and there is little point waiting for it. Or complaining if we see an EIO or EAGAIN instead. So, if the GPU is indeed in its death throes when we need to rewrite the registers for a new framebuffer, just ignore the error and proceed with the update. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-11drm/i915: disable PCH ports if needed when disabling a CRTCJesse Barnes
Disable any PCH ports associated with a pipe when disabling it. This should prevent transcoder disable failures due to ports still being on. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: introduce *_PIPE_ENABLED() macro] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-11drm/i915: Fix resume regression from 5d1d0ccChris Wilson
The irony of the patch to fix the resume regression on PineView causing a further regression on Ironlake is not lost on me. Reported-by: Jeff Chua <jeff.chua.linux@gmail.com> Reported-by: Björn Schließmann <chronoss@gmx.de> Tested-by: Björn Schließmann <chronoss@gmx.de> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28802 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-09drm/i915: Disable RC6 on IronlakeChris Wilson
The automatic powersaving feature is once again causing havoc, with 100% reliable hangs on boot and resume on affected machines. Reported-by: Francesco Allertsen <fallertsen@gmail.com> Reported-by: Gui Rui <chaos.proton@gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28582 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07drm/i915: cleanup per-pipe reg usageJesse Barnes
We had some conversions over to the _PIPE macros, but didn't get everything. So hide the per-pipe regs with an _ (still used in a few places for legacy) and add a few _PIPE based macros, then make sure everyone uses them. [update: remove usage of non-existent no-op macro] [update 2: keep modesetting suspend/resume code, update to new reg names] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: stylistic cleanups for checkpatch and taste] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07drm/i915: the PCH reference clocks are global, so don't clobber unconditionallyJesse Barnes
The PCH can drive several reference clocks simultaneously, and needs to with multiple display configurations. So we can't just clobber the existing state everytime we set a mode, we need to take into account what the other CRTCs are doing at the time. Doing so fixes an issue where you'd lose the LVDS display at boot if you had an LVDS+DP config. [updated: init bools and check CRTC status correctly] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07drm/i915: add port assertion check when disabling transcodersJesse Barnes
When a transcoder is disabled, any ports pointing at it should also be disabled. If they're not, we may fail to disable the transcoder, leading to blank displays. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07drm/i915: don't check plane vs pipe enable on ILK+Jesse Barnes
These bits have a different meaning on ILK+, where planes are hardwired to pipes. Fixing this avoid some spurious assertion failures. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07drm/i915: Set the transcoder port to none when disabling DP.Eric Anholt
The specs say to do so. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07drm/i915: Use DEBUG_KMS for the self-refresh watermarksChris Wilson
For consistency and segregation from the noisy DRM_DEBUG(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-01Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
Merge resume fixes from -fixes and an important fix for SDVO GMBUS.
2011-02-01drm/i915: Remove unreachable conditionChris Wilson
Fortunately unreachable. For Crestline, the watermarks must always be programmed to 8... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-01drm/i915: Trivial spelling mistake 'assertiing'Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25drm/i915: Reset crtc after resumeChris Wilson
Based on a patch by Takashi Iwai. Reported-by: Matthias Hopf <mat@mshopf.de> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=27272 Tested-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25drm/i915: Refactor self-refresh watermark calculationsChris Wilson
Move the plane->mode config to the point of use rather than repeatedly querying the same information. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25drm/i915: Silence a few -Wunused-but-set-variableChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-20Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
Apply the SandyBridge stability fixes from -fixes.
2011-01-19drm/i915: Include TLB miss latency in g4x watermark computationsChris Wilson
Reports of FIFO underruns are still persisting on gm45. References: https://bugs.freedesktop.org/show_bug.cgi?id=27589 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: Disable SSC for outputs other than LVDS or DPChris Wilson
For CRT and SDVO/HDMI, we need to use a normal, non-SSC, clock and so we must clear any enabling bits left-over from earlier outputs. And also seems to correct the LVDS panel on the Lenovo U160. However, at one point, it did cause an "ERROR failed to disable trancoder". So prolonged testing on top of Jesse's refactored and error-checking CRTC logic is desired. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: Honour LVDS sync polarity from EDIDBryan Freed
The i915 driver normally assumes the video bios has configured several of the LVDS panel registers, and it just inherits the values. If the vbios has not run, several of these will need to be setup. So we need to check that the LVDS sync polarity is correctly configured per any available modelines (e.g. EDID) and adjust if not, issuing a warning as we do. Signed-off-by: Mark Hayter <mdhayter@chromium.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: tune Sandy Bridge DRPS constantsJesse Barnes
These make us increase our frequency much more readily, and decrease them only after significant idle time, resulting in a 20% performance increase for nexuiz. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: Trivial sparse fixesChris Wilson
Move code around and invoke iomem annotation in a few more places in order to silence sparse. Still a few more iomem annotations to go... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: allow 945 to control self refresh (CxSR) automaticallyAlexander Lam
I changed 945's self refresh to work without the need for the driver to enable/disable self refresh manually based on the idle state of the gpu. This is much better than enabling/disabling self refresh for various reasons, including staying in a lower power state for more time and avoiding the need for cpu cycles. This was originally done manually to workaround issues with the hardware hanging. However, since 944001201: drm/i915: enable low power render writes on GEN3 hardware, automatic CxSR seems stable. Signed-off-by: Alexander Lam <lambchop468@gmail.com> Acked-by : Li Peng <peng.li@linux.intel.com> [ickle: play safe with the ordering and disable CxSR before tweaking any watermark and enable afterwards.] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: skip FDI & PCH enabling for DP_AJesse Barnes
eDP on the CPU doesn't need the PCH set up at all, it can in fact cause problems. So avoid FDI training and PCH PLL enabling in that case. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: set phase sync pointer override enable before setting phase sync ↵Jesse Barnes
pointer We need to unlock the phase sync pointer enable bit before we can actually enable the phase sync pointer workaround on Ironlake. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: factor out FDI disable and add FDI assertionsJesse Barnes
Factor out the FDI disable function (make it a mirror of ironlake_fdi_enable) and add some FDI related assertions to the FDI training code (we need an active pipe & plane before we start transmitting bits). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: add transcoder enable/disable functionsJesse Barnes
Along with assertion checks for the FDI transmitters and receivers (including PLLs). Modify the pipe enable function to check for FDI PLL status as well, when driving PCH ports. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: assert panel is unlocked before writing transcoder timing regsJesse Barnes
Otherwise our writes will be silently ignored. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: add PCH DPLL enable/disable functionsJesse Barnes
With assertions to check transcoder and reference clock state. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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