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path: root/drivers/clk/tegra/clk-tegra20.c
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2013-02-13clk: tegra: initialise parent of uart clocksLaxman Dewangan
Initialise the parent of UARTs to PLLP and disabling clock by default. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-02-13clk: tegra: fix driver to match DT bindingStephen Warren
enum tegra*_clk is intended to match the IDs listed in the Tegra clock bindings. There are a few mismatches, which this patch fixes: 1) pll_s and cop were left out of the Tegra20 enum. 2) spdif_in and spdif_out were swapped relative to the Tegra30 binding. 3) i2cslow was misnamed as i2c_slow, and a duplicate i2cslow clock added to the Tegra30 enum. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-02-12clk: tegra: Add missing spinlock for hclk and pclkPeter De Schrijver
The hclk and pclk clocks are controlled by the same register. Hence a lock is required to avoid corruption. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_opsJoseph Lo
Implementing suspend, resume and rail_off_ready API for tegra_cpu_car_ops. These functions were used for CPU powered-down state maintenance. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()sPrashant Gaikwad
With device tree support added for Tegra clocks look up is done from device tree, remove unused TEGRA_CLK_DUPLICATE()s. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28clk: tegra: add clock support for Tegra20Prashant Gaikwad
Add Tegra20 clock support based on common clock framework. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: s/1GHz/100MHz/ in call to tegra_clk_plle() to fix PCIe, implemented KBC clock, ensure all OF lookups return valid cookies i.e. an explicit error pointer or valid pointer not NULL, adapt to renames in earlier patches, fixed some checkpatch issues.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>