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2011-03-23MIPS: MTX-1: Make au1000_eth probe all PHY addressesFlorian Fainelli
commit bf3a1eb85967dcbaae42f4fcb53c2392cec32677 upstream. When au1000_eth probes the MII bus for PHY address, if we do not set au1000_eth platform data's phy_search_highest_address, the MII probing logic will exit early and will assume a valid PHY is found at address 0. For MTX-1, the PHY is at address 31, and without this patch, the link detection/speed/duplex would not work correctly. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2111/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-09-26MIPS: Sibyte: Fix M3 TLB exception handler workaround.Ralf Baechle
commit 3d45285dd1ff4d4a1361b95e2d6508579a4402b5 upstream. The M3 workaround needs to cmpare the region and VPN2 fields only. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-09-26MIPS: uasm: Add OR instruction.Ralf Baechle
commit 5808184f1b2fe06ef8a54a2b7fb1596d58098acf upstream. This is needed for the fix of the M3 workaround. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> [Backported by Aurelien Jarno <aurelien@aurel32.net>] Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-09-26MIPS: Set io_map_base for several PCI bridges lacking itBen Hutchings
commit 8faf2e6c201d95b780cd3b4674b7a55ede6dcbbb upstream. Several MIPS platforms don't set pci_controller::io_map_base for their PCI bridges. This results in a panic in pci_iomap(). (The panic is conditional on CONFIG_PCI_DOMAINS, but that is now enabled for all PCI MIPS systems.) Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Cc: linux-mips@linux-mips.org Cc: Martin Michlmayr <tbm@cyrius.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: 584784@bugs.debian.org Patchwork: https://patchwork.linux-mips.org/patch/1377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-09-26MIPS: Quit using undefined behavior of ADDU in 64-bit atomic operations.David Daney
commit f2a68272d799bf4092443357142f63b74f7669a1 upstream. For 64-bit, we must use DADDU and DSUBU. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-09-20compat: Make compat_alloc_user_space() incorporate the access_ok()H. Peter Anvin
commit c41d68a513c71e35a14f66d71782d27a79a81ea6 upstream. compat_alloc_user_space() expects the caller to independently call access_ok() to verify the returned area. A missing call could introduce problems on some architectures. This patch incorporates the access_ok() check into compat_alloc_user_space() and also adds a sanity check on the length. The existing compat_alloc_user_space() implementations are renamed arch_compat_alloc_user_space() and are used as part of the implementation of the new global function. This patch assumes NULL will cause __get_user()/__put_user() to either fail or access userspace on all architectures. This should be followed by checking the return value of compat_access_user_space() for NULL in the callers, at which time the access_ok() in the callers can also be removed. Reported-by: Ben Hawkes <hawkes@sota.gen.nz> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Ingo Molnar <mingo@elte.hu> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Tony Luck <tony.luck@intel.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: James Bottomley <jejb@parisc-linux.org> Cc: Kyle McMartin <kyle@mcmartin.ca> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-08-02MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1Shane McDonald
commit 95e8f634d7a3ea5af40ec3fa42c8a152fd3a0624 upstream. In the FPU emulator code of the MIPS, the Cause bits of the FCSR register are not currently writeable by the ctc1 instruction. In odd corner cases, this can cause problems. For example, a case existed where a divide-by-zero exception was generated by the FPU, and the signal handler attempted to restore the FPU registers to their state before the exception occurred. In this particular setup, writing the old value to the FCSR register would cause another divide-by-zero exception to occur immediately. The solution is to change the ctc1 instruction emulator code to allow the Cause bits of the FCSR register to be writeable. This is the behaviour of the hardware that the code is emulating. This problem was found by Shane McDonald, but the credit for the fix goes to Kevin Kissell. In Kevin's words: I submit that the bug is indeed in that ctc_op: case of the emulator. The Cause bits (17:12) are supposed to be writable by that instruction, but the CTC1 emulation won't let them be updated by the instruction. I think that actually if you just completely removed lines 387-388 [...] things would work a good deal better. At least, it would be a more accurate emulation of the architecturally defined FPU. If I wanted to be really, really pedantic (which I sometimes do), I'd also protect the reserved bits that aren't necessarily writable. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> To: anemo@mba.ocn.ne.jp To: kevink@paralogos.com To: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/1205/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-05-12MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.Ralf Baechle
(cherry picked from commit e65c7f33d75e977350ca350573d93c517ec02776) Previously it was unconditionally used on all Sibyte family SOCs. The M3 bug has to be handled in the TLB exception handler which is extremly performance sensitive, so this modification is expected to deliver around 2-3% performance improvment. This is important as required changes to the M3 workaround will make it more costly. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-04-01MIPS: Cleanup forgotten label_module_alloc in tlbex.cDavid Daney
commit abbdc3d88aa2d5c937b21044c336bcd056c1732f upstream. commit c8af165342e83a4eb078c9607d29a7c399d30a53 (lmo) rsp. e0cc87f59490d7d62a8ab2a76498dc8a2b64927a (kernel.org) left label_module_alloc unused. Remove it now. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/752/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2010-01-18untangle the do_mremap() messAl Viro
This backports the following upstream commits all as one patch: 54f5de709984bae0d31d823ff03de755f9dcac54 ecc1a8993751de4e82eb18640d631dae1f626bd6 1a0ef85f84feb13f07b604fcf5b90ef7c2b5c82f f106af4e90eadd76cfc0b5325f659619e08fb762 097eed103862f9c6a97f2e415e21d1134017b135 935874141df839c706cd6cdc438e85eb69d1525e 0ec62d290912bb4b989be7563851bc364ec73b56 c4caa778157dbbf04116f0ac2111e389b5cd7a29 2ea1d13f64efdf49319e86c87d9ba38c30902782 570dcf2c15463842e384eb597a87c1e39bead99b 564b3bffc619dcbdd160de597b0547a7017ea010 0067bd8a55862ac9dd212bd1c4f6f5bff1ca1301 f8b7256096a20436f6d0926747e3ac3d64c81d24 8c7b49b3ecd48923eb64ff57e07a1cdb74782970 9206de95b1ea68357996ec02be5db0638a0de2c1 2c6a10161d0b5fc047b5bd81b03693b9af99fab5 05d72faa6d13c9d857478a5d35c85db9adada685 bb52d6694002b9d632bb355f64daa045c6293a4e e77414e0aad6a1b063ba5e5750c582c75327ea6a aa65607373a4daf2010e8c3867b6317619f3c1a3 Backport done by Greg Kroah-Hartman. Only minor tweaks were needed. Cc: David S. Miller <davem@davemloft.net> Cc: Hugh Dickins <hugh.dickins@tiscali.co.uk> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-12-02MIPS: RB532: Fix devices.c compilation.Florian Fainelli
We should now use dev_set_drvdata to set the driver driver_data field. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/747/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-02MIPS: Fix MIPS I build.Ralf Baechle
Broken by d63c63e889bbeeaa461a8addf1245f89f3ce4ece (lmo) rsp. f1e39a4a616cd9981a9decfd5332fd07a01abb8b (kernel.org). Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/746/
2009-12-01MIPS: Loongson: Switch from flatmem to sparsememWu Zhangjin
With flatmem hibernation for Loongson will fail, and there are also some other problems such as broken files when using NFS or CIFS / Samba. The config help of sparsemem says: "This option provides some potential performance benefits, along with decreased code complexity." So to avoid the potential problems of FLATMEM, we disable FLATMEM directly and use SPARSEMEM instead. Related email thread: http://groups.google.com/group/loongson-dev/browse_thread/thread/b6b65890ec2b0f24/feb43e5aa7f55d9b?show_docid=feb43e5aa7f55d9b Reported-by: Tatu Kilappa <tatu.kilappa@gmail.com> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/737/ Cc: linux-mips@linux-mips.org Cc: zhangfx@lemote.com Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-01MIPS: Loongson: Disallow 4kB pagesWu Zhangjin
Currently, with PAGE_SIZE_4KB, the kernel for loongson will hang on: Kernel panic - not syncing: Attempted to kill init! The possible reason is the cache aliases problem: Loongson 2F has 64kb, 4 way L1 Cache, the way size is 16kb, which is bigger then 4kb. so, If using 4kb page size, there is cache aliases problem. To avoid this kind of problem, extra cache flushing. The 2nd possible solution is 16kb page size which avoids cache aliases without the need for extra cache flushes. So we disable 4kB pages until the aliasing issue is solved. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/736/ Cc: linux-mips@linux-mips.org Cc: zhangfx@lemote.com Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-01MIPS: Add missing definition for MADV_HWPOISON.Ralf Baechle
Thanks to Joseph S. Myers for reporting this. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: "Joseph S. Myers" <joseph@codesourcery.com> Patchwork: http://patchwork.linux-mips.org/patch/723/
2009-12-01MIPS: Fix build error if __xchg() is not getting inlined.Ralf Baechle
If __xchg() is not getting inlined the outline version of the function will have a reference to __xchg_called_with_bad_pointer() which does not exist remaining. Fixed by using BUILD_BUG_ON() to check for allowable operand sizes. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/705/
2009-12-01MIPS: IP22/IP28 Disable early printk to fix boot problems on some systems.Martin Michlmayr
Some Debian users have reported that the kernel hangs early during boot on some IP22 systems. Thomas Bogendoerfer found that this is due to a "bad interaction between CONFIG_EARLY_PRINTK and overwritten prom memory during early boot". Since there's no fix yet, disable CONFIG_EARLY_PRINTK for now. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Cc: linux-mips@linux-mips.org Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/702/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-13MIPS: SMTC: Fix lockup in smtc_distribute_timerKevin D. Kissell
1. At the end of smtc_distribute_timer, nextstamp is valid and has already passed so we goto repeat. 2. Nothing updates nextstamp (only updated if the timeout is in the future And we just decided it is in the past) 3. At the end nextstamp still has the same value so it is still valid and in the past. 4. This repeats until read_c0_count has a value which causes nextstamp to be in the future. Reported and initial patch and testing by Mikael Starvik <mikael.starvik@axis.com>. Signed-off-by: Kevin D. Kissell <kevink@paralogos.com> Cc: Mikael Starvik <mikael.starvik@axis.com> Cc: linux-mips@linux-mips.org Cc: Jesper Nilsson <Jesper.Nilsson@axis.com> Patchwork: http://patchwork.linux-mips.org/patch/621/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-13MIPS: TXx9: Update rbtx49xx_defconfigAtsushi Nemoto
Enable following features: * MTD (RBTX4939, NAND_TXX9NDFMC) * HW_RANDOM (HW_RANDOM_TX4939) * SOUND (SND_SOC_TXX9ACLC) * DMADEVICE (TXX9_DMAC) Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-13MIPS: Make local arrays with CL_SIZE static __initdataAtsushi Nemoto
Since commit 22242681cff52bfb7cba5d2a37b91802be7a4e4c ("MIPS: Extend COMMAND_LINE_SIZE"), CL_SIZE is 4096 and local array variables with this size will cause an build failure with default CONFIG_FRAME_WARN settings. Although current users of such array variables are all early bootstrap code and not likely to cause real stack overflow (thread_info corruption), it is preferable to to declare these arrays static with __initdata. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-13MIPS: Add DMA declare coherent memory supportYoichi Yuasa
The ohci-sm501 driver requires dma_declare_coherent_memory(). It is used by the driver's local memory allocation with dma_alloc_coherent(). Tested on TANBAC TB0287(VR4131 + SM501). [Ralf: Fixed reject in dma-default.c and removed the entire #if 0'ed block in dma-mapping.h instead of just the #if 0.] Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-13MIPS: Fix emulation of 64-bit FPU on FPU-less 64-bit CPUs.David Daney
Running a 64-bit kernel on a 64-bit CPU without an FPU would cause the emulator to run in 32-bit mode. The c0_Status.FR bit is wired to zero on systems without an FPU, so using that bit to decide how the emulator behaves doesn't allow for proper emulation on 64-bit FPU-less processors. Instead, we need to select the emulator mode based on the user-space ABI. Since the thread flag TIF_32BIT_REGS is used to set c0_Status.FR, we can just use it to decide if the emulator should be in 32-bit or 64-bit mode. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: O32: Fix ppollArnaud Patard
sys_ppoll syscall needs to use a compat handler on 64bit kernels with o32 user-space. Signed-off-by: Arnaud Patard <apatard@mandriva.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Oprofile: Rename cpu_type from godson2 to loongson2Wu Zhangjin
Unify the naming method between kernel and the user-space oprofile tool. Because loongson is used instead of godson in most of the places, we agreed to use loongson instead, which will simplify future maintenance. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Alchemy: Fix hang with high-frequency edge interruptsManuel Lauss
The handle_edge_irq() flowhandler disables edge int sources which occur too fast (i.e. another edge comes in before the irq handler function had a chance to finish). Currently, the mask_ack() callback does not ack the edges in hardware, leading to an endless loop in the flowhandler where it tries to shut up the irq source. When I rewrote the alchemy IRQ code I wrongly assumed the mask_ack() callback was only used by the level flowhandler, hence it omitted the (at the time pointless) edge acks. Turned out I was wrong; so here is a complete mask_ack implementation for Alchemy IC, which fixes the above mentioned problem. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: TXx9: Fix spi-baseclk valueAtsushi Nemoto
TXx9 SPI bit rate is calculated by: fBR = fSPI / 2 / (n + 1) (fSPI is SPI master clock freq, i.e. imbusclk freq.) So use imbus_clk / 2 as a spi-baseclk. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: bcm63xx: Set the correct BCM3302 CPU nameFlorian Fainelli
For consistency with other BCM63xx SoC set the CPU name to "Broadcom BCM6338" when actually running on that system. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_storeZhang Le
Loongson 2 does not have dcache aliases when is using 16k pages. and the And because Loongson 2 doesn't do SMP , cpu_icache_snoops_remote_store does not matter here. Signed-off-by: Zhang Le <r0bertz@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Avoid potential hazard on Context registerRalf Baechle
set_saved_sp reads Context register. Avoid reading stale value from earlier incomplete write. Issue found and fixed for head.S by Chris Dearman <chris@mips.com>. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Octeon: Use lockless interrupt controller operations when possible.David Daney
Some newer Octeon chips have registers that allow lockless operation of the interrupt controller. Take advantage of them. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinityDavid Daney
Since the locks are used from interrupt context we need the irqsave/irqrestore versions of the locking functions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Set S-cache linesize to 64-bytes for MTI's S-cacheRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: SMTC: Avoid queing multiple reschedule IPIsJaidev Patwardhan
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: GCMP: Avoid accessing registers when they are not presentJaidev Patwardhan
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: GIC: Random fixes and enhancements.Chris Dearman
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_startChris Dearman
Signed-off-by: Chris Dearman (chris@mips.com) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operandsNigel Stephens
This patch ensures that the sign bit is always updated for NaN operands. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: SPRAM: Clean up support code a littleChris Dearman
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: 1004K: Enable SPRAM support.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4Ralf Baechle
Based on original patch by Chris Dearman <chris@mips.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: MTI: Fix accesses to device registers on MIPS boardsChris Dearman
This fixes the remaining problems introduced by f197465384bf7ef1af184c2ed1a4e268911a91e3 (incorrect access length & byteswapping in bigendian mode) Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Fix machine check exception in kmap_coherent()Kevin Cernekee
On an SMP system with cache aliases, the following sequence of events may happen: 1) copy_user_highpage() runs on CPU0, invoking kmap_coherent() to create a temporary mapping in the fixmap region 2) copy_page() starts on CPU0 3) CPU1 sends CPU0 an IPI asking CPU0 to run local_r4k_flush_cache_page() 4) CPU0 takes the interrupt, interrupting copy_page() 5) local_r4k_flush_cache_page() on CPU0 calls kmap_coherent() again 6) The second invocation of kmap_coherent() on CPU0 tries to use the same fixmap virtual address that was being used by copy_user_highpage() 7) CPU0 throws a machine check exception for the TLB address conflict Fixed by creating an extra set of fixmap entries for use in interrupt handlers. This prevents fixmap VA conflicts between copy_user_highpage() running in user context, and local_r4k_flush_cache_page() invoked from an SMP IPI. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: MTX-1: Fix build if CONFIG_PCI is disabled.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: AR7: register watchdog device only if enabled in hw configurationFlorian Fainelli
This patch checks if the watchdog enable bit is set in the DCL register meaning that the hardware watchdog actually works and if so, register the ar7_wdt platform_device. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: BCM63xx: Prepare for watchdog supportFlorian Fainelli
This patch prepares the board code to register a bcm63xx_wdt platform_device that we are going to use in a subsequent patch. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: BCM63xx: Make bcm63xx_uart_register an initfuncFlorian Fainelli
This patch removes the calls to bcm63xx_uart_register in board_bcm963xx.c and make bcm63xx_uart_register an initfunc. Allows us to remove bcm63xx_dev_uart.h which was there to make checkpatch.pl happy. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: AU1000: Fix build failure for db1x00 configured for Au1100 SoCFlorian Fainelli
This patch fixes the following warning, which becomes an error due to -Werror to be turned on: CC arch/mips/alchemy/common/gpiolib-au1000.o cc1: warnings being treated as errors arch/mips/alchemy/common/gpiolib-au1000.c: In function 'au1100_gpio2_to_irq': /home/florian/dev/kernel/linux-queue/arch/mips/include/asm/mach-au1x00/gpio-au1000.h:107: warning: control reaches end of non-void function Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: BCM63xx: Fix soft-reset lockup on BCM6345Florian Fainelli
This patch fixes a lockup on BCM6345 where setting the PLL soft reset bit will also lock the other blocks including UART. Instead of setting only the PLL soft reset bit in the software reset register, set this bit but do not touch the others. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: TXx9: Fix error handling / Fix for noenexisting gpio_remove.Ralf Roesch
Error was introduced by commit 0385d1f3d394c6814be0b165c153fc3fc254469a. Signed-off-by: Ralf Roesch <ralf.roesch@rw-gmbh.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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