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2012-03-21Merge tag 'irqdomain-for-linus' of git://git.secretlab.ca/git/linux-2.6Linus Torvalds
Pull irq_domain support for all architectures from Grant Likely: "Generialize powerpc's irq_host as irq_domain This branch takes the PowerPC irq_host infrastructure (reverse mapping from Linux IRQ numbers to hardware irq numbering), generalizes it, renames it to irq_domain, and makes it available to all architectures. Originally the plan has been to create an all-new irq_domain implementation which addresses some of the powerpc shortcomings such as not handling 1:1 mappings well, but doing that proved to be far more difficult and invasive than generalizing the working code and refactoring it in-place. So, this branch rips out the 'new' irq_domain and replaces it with the modified powerpc version (in a fully bisectable way of course). It converts all users over to the new API and makes irq_domain selectable on any architecture. No architecture is forced to enable irq_domain, but the infrastructure is required for doing OpenFirmware style irq translations. It will even work on SPARC even though SPARC has it's own mechanism for translating irqs at boot time. MIPS, microblaze, embedded x86 and c6x are converted too. The resulting irq_domain code is probably still too verbose and can be optimized more, but that can be done incrementally and is a task for follow-on patches." * tag 'irqdomain-for-linus' of git://git.secretlab.ca/git/linux-2.6: (31 commits) dt: fix twl4030 for non-dt compile on x86 mfd: twl-core: Add IRQ_DOMAIN dependency devicetree: Add empty of_platform_populate() for !CONFIG_OF_ADDRESS (sparc) irq_domain: Centralize definition of irq_dispose_mapping() irq_domain/mips: Allow irq_domain on MIPS irq_domain/x86: Convert x86 (embedded) to use common irq_domain ppc-6xx: fix build failure in flipper-pic.c and hlwd-pic.c irq_domain/microblaze: Convert microblaze to use irq_domains irq_domain/powerpc: Replace custom xlate functions with library functions irq_domain/powerpc: constify irq_domain_ops irq_domain/c6x: Use library of xlate functions irq_domain/c6x: constify irq_domain structures irq_domain/c6x: Convert c6x to use generic irq_domain support. irq_domain: constify irq_domain_ops irq_domain: Create common xlate functions that device drivers can use irq_domain: Remove irq_domain_add_simple() irq_domain: Remove 'new' irq_domain in favour of the ppc one mfd: twl-core.c: Fix the number of interrupts managed by twl4030 of/address: add empty static inlines for !CONFIG_OF irq_domain: Add support for base irq and hwirq in legacy mappings ...
2012-03-16C6X: remove dead code from entry.SMark Salter
The ENDPROC() on sys_fadvise64_c6x() in arch/c6x/kernel/entry.S is outside of the conditional block with the matching ENTRY() macro. This leads a newer (v2.22 vs. v2.20) assembler to complain: /tmp/ccGZBaPT.s: Assembler messages: /tmp/ccGZBaPT.s: Error: .size expression for sys_fadvise64_c6x does not evaluate to a constant The conditional block became dead code when c6x switched to generic unistd.h and should be removed along with the offending ENDPROC(). Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: David Howells <dhowells@redhat.com>
2012-03-07C6X: fix KSTK_EIP and KSTK_ESP macrosMark Salter
There was a latent typo in the C6X KSTK_EIP and KSTK_ESP macros which caused a problem with a new patch which used them. The broken definitions were of the form: #define KSTK_FOO(tsk) (task_pt_regs(task)->foo) Note the use of task vs tsk. This actually worked before because the only place in the kernel which used these macros passed in a local pointer named task. Signed-off-by: Mark Salter <msalter@redhat.com>
2012-02-16irq_domain/c6x: Use library of xlate functionsGrant Likely
The c6x irq controllers don't need to define custom .xlate hooks Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Mark Salter <msalter@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2012-02-16irq_domain/c6x: constify irq_domain structuresGrant Likely
Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Cc: Mark Salter <msalter@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2012-02-16irq_domain/c6x: Convert c6x to use generic irq_domain support.Mark Salter
The C6X IRQ support was copied almost verbatim from the PowerPC virtual IRQ code. The PowerPC code was used as the basis for generic irq_domain support, so this patch mostly copies what what done to arch/powerpc by Grant Likely in his irq_domain patch series. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Cc: Aurelien Jacquiot <a-jacquiot@ti.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2012-02-14Kbuild: Use dtc's -d (dependency) optionStephen Warren
This hooks dtc into Kbuild's dependency system. Thus, for example, "make dtbs" will rebuild tegra-harmony.dtb if only tegra20.dtsi has changed yet tegra-harmony.dts has not. The previous lack of this feature recently caused me to have very confusing "git bisect" results. For ARM, it's obvious what to add to $(targets). I'm not familiar enough with other architectures to know what to add there. Powerpc appears to already add various .dtb files into $(targets), but the other archs may need something added to $(targets) to work. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Mark Salter <msalter@redhat.com>
2012-01-08C6X: replace tick_nohz_stop/restart_sched_tick callsMark Salter
The following commits replaced the tick_nohz_{stop,restart}_sched_tick API with separate tick and rcu calls: 280f06774afedf849f0b34248ed6aff57d0f6908 2bbb6817c0ac1b5f2a68d720f364f98eeb1ac4fd 1268fbc746ea1cd279886a740dcbad4ba5232225 This patch replaces the C6X use of the old API with the newer interfaces. Signed-off-by: Mark Salter <msalter@redhat.com>
2012-01-08C6X: add register_cpu callMark Salter
Commit ccbc60d3e19a1b6ae66ca0d89b3da02dde62088b requires CPU topology information even in !SMP cases. This requires C6X to add a call tp register_cpu() in order to avoid a panic at boot time. Signed-off-by: Mark Salter <msalter@redhat.com>
2012-01-08C6X: deal with memblock API changesMark Salter
Recent memblock related commits require the following C6X changes: * commit 24aa07882b672fff2da2f5c955759f0bd13d32d5 asm/memblock.h no longer required * commit 1440c4e2c918532f39131c3330fe2226e16be7b6 memblock_analyze() no longer needed to update total size * commit fe091c208a40299fba40e62292a610fb91e44b4e memblock_init() no longer needed Signed-off-by: Mark Salter <msalter@redhat.com>
2012-01-08C6X: fix timer64 initializationMark Salter
Some SoCs have a timer block enable controlled through the DSCR registers. There is a problem in the timer64 driver initialization where the code accesses a timer register to get the divisor used to calculate timer clock rate. If the timer block has not been enabled when this register read takes place, an exception is generated. This patch makes sure that the timer block is enabled before accessing the registers. Signed-off-by: Mark Salter <msalter@redhat.com>
2012-01-08C6X: fix layout of EMIFA registersMark Salter
Signed-off-by: Mark Salter <msalter@redhat.com>
2011-10-06C6X: DSCR - Device State Configuration RegistersMark Salter
All SoCs provide an area of device configuration registers called the DSCR. The location of specific registers as well as their use varies considerably from implementation to implementation. Rather than having to rely on additional SoC-specific DSCR code for each new supported SoC, this code generalize things as much as possible using device tree properties. Initialization must take place early on (setup_arch time) in case the event timer device needs to be enable via the DSCR. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: EMIF - External Memory InterfaceMark Salter
Several SoC parts provide a simple bridge to support external memory mapped devices. This code probes the device tree for an EMIF node and sets up the bridge registers if such a node is found. Beyond initial set up, there is no further need to access the bridge control registers. External devices on the bus are accessed through their MMIO registers using suitable drivers. The bridge hardware does provide for timeout and other error interrupts, but these are not yet supported. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: general SoC supportMark Salter
This patch provides a soc_ops struct which provides hooks for SoC functionality which doesn't fit well into other places. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: library codeAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: headersAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: ptrace supportAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: loadable module supportAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: cache controlAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: clocksMark Salter
The C6X SoCs contain several PLL controllers each with up to 16 clock outputs feeding into the cores or peripheral clock domains. The hardware is very similar to arm/mach-davinci clocks. This is still a work in progress which needs to be updated once device tree clock binding changes shake out. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: build infrastructureAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: syscallsAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> [msalter@redhat.com: add include of linux/module.h to sys_c6x.c] Signed-off-by: Mark Salter <msalter@redhat.com>
2011-10-06C6X: interrupt handlingAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: time managementAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: signal managementAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: process managementAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: memory management and DMA supportAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> The C6X architecture currently lacks an MMU so memory management is relatively simple. There is no bus snooping between L2 and main memory but coherent DMA memory is supported by making regions of main memory uncached. If such a region is desired, it can be specified on the commandline with a "memdma=" argument. Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: devicetree supportMark Salter
This is the basic devicetree support for C6X. Currently, four boards are supported. Each one uses a different SoC part. Two of the four supported SoCs are multicore. One with 3 cores and the other with 6 cores. There is no coherency between the core-level caches, so SMP is not an option. It is possible to run separate kernel instances on the various cores. There is currently no C6X bootloader support for device trees so we build in the DTB for now. There are some interesting twists to the hardware which are of note for device tree support. Each core has its own interrupt controller which is controlled by special purpose core registers. This core controller provides 12 general purpose prioritized interrupt sources. Each core is contained within a hardware "module" which provides L1 and L2 caches, power control, and another interrupt controller which cascades into the core interrupt controller. These core module functions are controlled by memory mapped registers. The addresses for these registers are the same for each core. That is, when coreN accesses a module-level MMIO register at a given address, it accesses the register for coreN even though other cores would use the same address to access the register in the module containing those cores. Other hardware modules (timers, enet, etc) which are memory mapped can be accessed by all cores. The timers need some further explanation for multicore SoCs. Even though all timer control registers are visible to all cores, interrupt routing or other considerations may make a given timer more suitable for use by a core than some other timer. Because of this and the desire to have the same image run on more than one core, the timer nodes have a "ti,core-mask" property which is used by the driver to scan for a suitable timer to use. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: early boot codeAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> This patch provides the early boot code for C6X architecture. There is a 16 entry vector table which is used to direct reset and interrupt events. The vector table entries contain a small amount of code (maximum of 8 opcodes) which simply branches to the actual event handling code. The head.S code simply clears BSS, setups up a few control registers, and calls machine_init followed by start_kernel. The machine_init code in setup.c does the early flat tree parsing (memory, commandline, etc). At setup_arch time, the code does the usual memory setup and minimally scans the devicetree for any needed information. Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-06C6X: build infrastructureAurelien Jacquiot
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>