diff options
Diffstat (limited to 'sound/pci')
| -rw-r--r-- | sound/pci/Kconfig | 12 | ||||
| -rw-r--r-- | sound/pci/Makefile | 2 | ||||
| -rw-r--r-- | sound/pci/ad1889.c | 1089 | ||||
| -rw-r--r-- | sound/pci/ad1889.h | 189 |
4 files changed, 1292 insertions, 0 deletions
diff --git a/sound/pci/Kconfig b/sound/pci/Kconfig index 1e458919cce..a5d593c66f9 100644 --- a/sound/pci/Kconfig +++ b/sound/pci/Kconfig @@ -316,6 +316,18 @@ config SND_YMFPCI To compile this driver as a module, choose M here: the module will be called snd-ymfpci. +config SND_AD1889 + tristate "Analog Devices AD1889" + depends on SND + select SND_AC97_CODEC + help + Say Y here to include support for the integrated AC97 sound + device found in particular on the Hewlett-Packard [BCJ]-xxx0 + class PA-RISC workstations, using the AD1819 codec. + + To compile this as a module, choose M here: the module + will be called snd-ad1889. + config SND_ALS4000 tristate "Avance Logic ALS4000" depends on SND && ISA_DMA_API diff --git a/sound/pci/Makefile b/sound/pci/Makefile index b40575c3349..42fabfcfc2a 100644 --- a/sound/pci/Makefile +++ b/sound/pci/Makefile @@ -3,6 +3,7 @@ # Copyright (c) 2001 by Jaroslav Kysela <perex@suse.cz> # +snd-ad1889-objs := ad1889.o snd-als4000-objs := als4000.o snd-atiixp-objs := atiixp.o snd-atiixp-modem-objs := atiixp_modem.o @@ -25,6 +26,7 @@ snd-via82xx-objs := via82xx.o snd-via82xx-modem-objs := via82xx_modem.o # Toplevel Module Dependency +obj-$(CONFIG_SND_AD1889) += snd-ad1889.o obj-$(CONFIG_SND_ALS4000) += snd-als4000.o obj-$(CONFIG_SND_ATIIXP) += snd-atiixp.o obj-$(CONFIG_SND_ATIIXP_MODEM) += snd-atiixp-modem.o diff --git a/sound/pci/ad1889.c b/sound/pci/ad1889.c new file mode 100644 index 00000000000..37e8df24711 --- /dev/null +++ b/sound/pci/ad1889.c @@ -0,0 +1,1089 @@ +/* Analog Devices 1889 audio driver + * + * This is a driver for the AD1889 PCI audio chipset found + * on the HP PA-RISC [BCJ]-xxx0 workstations. + * + * Copyright (C) 2004-2005, Kyle McMartin <kyle@parisc-linux.org> + * Copyright (C) 2005, Thibaut Varene <varenet@parisc-linux.org> + * Based on the OSS AD1889 driver by Randolph Chung <tausq@debian.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * TODO: + * Do we need to take care of CCS register? + * Maybe we could use finer grained locking (separate locks for pb/cap)? + * Wishlist: + * Control Interface (mixer) support + * Better AC97 support (VSR...)? + * PM support + * MIDI support + * Game Port support + * SG DMA support (this will need *alot* of work) + */ + +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/compiler.h> +#include <linux/delay.h> + +#include <sound/driver.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/initval.h> +#include <sound/ac97_codec.h> + +#include <asm/io.h> + +#include "ad1889.h" +#include "ac97/ac97_id.h" + +#define AD1889_DRVVER "$Revision: 1.1 $" + +MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>, Thibaut Varene <t-bone@parisc-linux.org>"); +MODULE_DESCRIPTION("Analog Devices AD1889 ALSA sound driver"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("{{Analog Devices,AD1889}}"); + +static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; +module_param_array(index, int, NULL, 0444); +MODULE_PARM_DESC(index, "Index value for the AD1889 soundcard."); + +static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; +module_param_array(id, charp, NULL, 0444); +MODULE_PARM_DESC(id, "ID string for the AD1889 soundcard."); + +static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; +module_param_array(enable, bool, NULL, 0444); +MODULE_PARM_DESC(enable, "Enable AD1889 soundcard."); + +static char *ac97_quirk[SNDRV_CARDS]; +module_param_array(ac97_quirk, charp, NULL, 0444); +MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); + +#define DEVNAME "ad1889" +#define PFX DEVNAME ": " + +/* let's use the global sound debug interfaces */ +#define ad1889_debug(fmt, arg...) snd_printd(KERN_DEBUG fmt, ## arg) + +/* keep track of some hw registers */ +struct ad1889_register_state { + u16 reg; /* reg setup */ + u32 addr; /* dma base address */ + unsigned long size; /* DMA buffer size */ +}; + +struct snd_ad1889 { + snd_card_t *card; + struct pci_dev *pci; + + int irq; + unsigned long bar; + void __iomem *iobase; + + ac97_t *ac97; + ac97_bus_t *ac97_bus; + snd_pcm_t *pcm; + snd_info_entry_t *proc; + + snd_pcm_substream_t *psubs; + snd_pcm_substream_t *csubs; + + /* playback register state */ + struct ad1889_register_state wave; + struct ad1889_register_state ramc; + + spinlock_t lock; +}; + +static inline u16 +ad1889_readw(struct snd_ad1889 *chip, unsigned reg) +{ + return readw(chip->iobase + reg); +} + +static inline void +ad1889_writew(struct snd_ad1889 *chip, unsigned reg, u16 val) +{ + writew(val, chip->iobase + reg); +} + +static inline u32 +ad1889_readl(struct snd_ad1889 *chip, unsigned reg) +{ + return readl(chip->iobase + reg); +} + +static inline void +ad1889_writel(struct snd_ad1889 *chip, unsigned reg, u32 val) +{ + writel(val, chip->iobase + reg); +} + +static inline void +ad1889_unmute(struct snd_ad1889 *chip) +{ + u16 st; + st = ad1889_readw(chip, AD_DS_WADA) & + ~(AD_DS_WADA_RWAM | AD_DS_WADA_LWAM); + ad1889_writew(chip, AD_DS_WADA, st); + ad1889_readw(chip, AD_DS_WADA); +} + +static inline void +ad1889_mute(struct snd_ad1889 *chip) +{ + u16 st; + st = ad1889_readw(chip, AD_DS_WADA) | AD_DS_WADA_RWAM | AD_DS_WADA_LWAM; + ad1889_writew(chip, AD_DS_WADA, st); + ad1889_readw(chip, AD_DS_WADA); +} + +static inline void +ad1889_load_adc_buffer_address(struct snd_ad1889 *chip, u32 address) +{ + ad1889_writel(chip, AD_DMA_ADCBA, address); + ad1889_writel(chip, AD_DMA_ADCCA, address); +} + +static inline void +ad1889_load_adc_buffer_count(struct snd_ad1889 *chip, u32 count) +{ + ad1889_writel(chip, AD_DMA_ADCBC, count); + ad1889_writel(chip, AD_DMA_ADCCC, count); +} + +static inline void +ad1889_load_adc_interrupt_count(struct snd_ad1889 *chip, u32 count) +{ + ad1889_writel(chip, AD_DMA_ADCIB, count); + ad1889_writel(chip, AD_DMA_ADCIC, count); +} + +static inline void +ad1889_load_wave_buffer_address(struct snd_ad1889 *chip, u32 address) +{ + ad1889_writel(chip, AD_DMA_WAVBA, address); + ad1889_writel(chip, AD_DMA_WAVCA, address); +} + +static inline void +ad1889_load_wave_buffer_count(struct snd_ad1889 *chip, u32 count) +{ + ad1889_writel(chip, AD_DMA_WAVBC, count); + ad1889_writel(chip, AD_DMA_WAVCC, count); +} + +static inline void +ad1889_load_wave_interrupt_count(struct snd_ad1889 *chip, u32 count) +{ + ad1889_writel(chip, AD_DMA_WAVIB, count); + ad1889_writel(chip, AD_DMA_WAVIC, count); +} + +static void +ad1889_channel_reset(struct snd_ad1889 *chip, unsigned int channel) +{ + u16 reg; + + if (channel & AD_CHAN_WAV) { + /* Disable wave channel */ + reg = ad1889_readw(chip, AD_DS_WSMC) & ~AD_DS_WSMC_WAEN; + ad1889_writew(chip, AD_DS_WSMC, reg); + chip->wave.reg = reg; + + /* disable IRQs */ + reg = ad1889_readw(chip, AD_DMA_WAV); + reg &= AD_DMA_IM_DIS; + reg &= ~AD_DMA_LOOP; + ad1889_writew(chip, AD_DMA_WAV, reg); + + /* clear IRQ and address counters and pointers */ + ad1889_load_wave_buffer_address(chip, 0x0); + ad1889_load_wave_buffer_count(chip, 0x0); + ad1889_load_wave_interrupt_count(chip, 0x0); + + /* flush */ + ad1889_readw(chip, AD_DMA_WAV); + } + + if (channel & AD_CHAN_ADC) { + /* Disable ADC channel */ + reg = ad1889_readw(chip, AD_DS_RAMC) & ~AD_DS_RAMC_ADEN; + ad1889_writew(chip, AD_DS_RAMC, reg); + chip->ramc.reg = reg; + + reg = ad1889_readw(chip, AD_DMA_ADC); + reg &= AD_DMA_IM_DIS; + reg &= ~AD_DMA_LOOP; + ad1889_writew(chip, AD_DMA_ADC, reg); + + ad1889_load_adc_buffer_address(chip, 0x0); + ad1889_load_adc_buffer_count(chip, 0x0); + ad1889_load_adc_interrupt_count(chip, 0x0); + + /* flush */ + ad1889_readw(chip, AD_DMA_ADC); + } +} + +static inline u16 +snd_ad1889_ac97_read(ac97_t *ac97, unsigned short reg) +{ + struct snd_ad1889 *chip = ac97->private_data; + return ad1889_readw(chip, AD_AC97_BASE + reg); +} + +static inline void +snd_ad1889_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val) +{ + struct snd_ad1889 *chip = ac97->private_data; + ad1889_writew(chip, AD_AC97_BASE + reg, val); +} + +static int +snd_ad1889_ac97_ready(struct snd_ad1889 *chip) +{ + int retry = 400; /* average needs 352 msec */ + + while (!(ad1889_readw(chip, AD_AC97_ACIC) & AD_AC97_ACIC_ACRDY) + && --retry) + mdelay(1); + if (!retry) { + snd_printk(KERN_ERR PFX "[%s] Link is not ready.\n", + __FUNCTION__); + return -EIO; + } + ad1889_debug("[%s] ready after %d ms\n", __FUNCTION__, 400 - retry); + + return 0; +} + +static int +snd_ad1889_hw_params(snd_pcm_substream_t *substream, + snd_pcm_hw_params_t *hw_params) +{ + return snd_pcm_lib_malloc_pages(substream, + params_buffer_bytes(hw_params)); +} + +static int +snd_ad1889_hw_free(snd_pcm_substream_t *substream) +{ + return snd_pcm_lib_free_pages(substream); +} + +static snd_pcm_hardware_t snd_ad1889_playback_hw = { + .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, + .rate_min = 8000, /* docs say 7000, but we're lazy */ + .rate_max = 48000, + .channels_min = 1, + .channels_max = 2, + .buffer_bytes_max = BUFFER_BYTES_MAX, + .period_bytes_min = PERIOD_BYTES_MIN, + .period_bytes_max = PERIOD_BYTES_MAX, + .periods_min = PERIODS_MIN, + .periods_max = PERIODS_MAX, + /*.fifo_size = 0,*/ +}; + +static snd_pcm_hardware_t snd_ad1889_capture_hw = { + .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, /* docs say we could to VSR, but we're lazy */ + .rate_max = 48000, + .channels_min = 1, + .channels_max = 2, + .buffer_bytes_max = BUFFER_BYTES_MAX, + .period_bytes_min = PERIOD_BYTES_MIN, + .period_bytes_max = PERIOD_BYTES_MAX, + .periods_min = PERIODS_MIN, + .periods_max = PERIODS_MAX, + /*.fifo_size = 0,*/ +}; + +static int +snd_ad1889_playback_open(snd_pcm_substream_t *ss) +{ + struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); + snd_pcm_runtime_t *rt = ss->runtime; + + chip->psubs = ss; + rt->hw = snd_ad1889_playback_hw; + + return 0; +} + +static int +snd_ad1889_capture_open(snd_pcm_substream_t *ss) +{ + struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); + snd_pcm_runtime_t *rt = ss->runtime; + + chip->csubs = ss; + rt->hw = snd_ad1889_capture_hw; + + return 0; +} + +static int +snd_ad1889_playback_close(snd_pcm_substream_t *ss) +{ + struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); + chip->psubs = NULL; + return 0; +} + +static int +snd_ad1889_capture_close(snd_pcm_substream_t *ss) +{ + struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); + chip->csubs = NULL; + return 0; +} + +static int +snd_ad1889_playback_prepare(snd_pcm_substream_t *ss) +{ + struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); + snd_pcm_runtime_t *rt = ss->runtime; + unsigned int size = snd_pcm_lib_buffer_bytes(ss); + unsigned int count = snd_pcm_lib_period_bytes(ss); + u16 reg; + + ad1889_channel_reset(chip, AD_CHAN_WAV); + + reg = ad1889_readw(chip, AD_DS_WSMC); + + /* Mask out 16-bit / Stereo */ + reg &= ~(AD_DS_WSMC_WA16 | AD_DS_WSMC_WAST); + + if (snd_pcm_format_width(rt->format) == 16) + reg |= AD_DS_WSMC_WA16; + + if (rt->channels > 1) + reg |= AD_DS_WSMC_WAST; + + /* let's make sure we don't clobber ourselves */ + spin_lock_irq(&chip->lock); + + chip->wave.size = size; + chip->wave.reg = reg; + chip->wave.addr = rt->dma_addr; + + ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg); + + /* Set sample rates on the codec */ + ad1889_writew(chip, AD_DS_WAS, rt->rate); + + /* Set up DMA */ + ad1889_load_wave_buffer_address(chip, chip->wave.addr); + ad1889_load_wave_buffer_count(chip, size); + ad1889_load_wave_interrupt_count(chip, count); + + /* writes flush */ + ad1889_readw(chip, AD_DS_WSMC); + + spin_unlock_irq(&chip->lock); + + ad1889_debug("prepare playback: addr = 0x%x, count = %u, " + "size = %u, reg = 0x%x, rate = %u\n", chip->wave.addr, + count, size, reg, rt->rate); + return 0; +} + +static int +snd_ad1889_capture_prepare(snd_pcm_substream_t *ss) +{ + struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); + snd_pcm_runtime_t *rt = ss->runtime; + unsigned int size = snd_pcm_lib_buffer_bytes(ss); + unsigned int count = snd_pcm_lib_period_bytes(ss); + u16 reg; + + ad1889_channel_reset(chip, AD_CHAN_ADC); + + reg = ad1889_readw(chip, AD_DS_RAMC); + + /* Mask out 16-bit / Stereo */ + reg &= ~(AD_DS_RAMC_AD16 | AD_DS_RAMC_ADST); + + if (snd_pcm_format_width(rt->format) == 16) + reg |= AD_DS_RAMC_AD16; + + if (rt->channels > 1) + reg |= AD_DS_RAMC_ADST; + + /* let's make sure we don't clobber ourselves */ + spin_lock_irq(&chip->lock); + + chip->ramc.size = size; + chip->ramc.reg = reg; + chip->ramc.addr = rt->dma_addr; + + ad1889_writew(chip, AD_DS_RAMC, chip->ramc.reg); + + /* Set up DMA */ + ad1889_load_adc_buffer_address(chip, chip->ramc.addr); + ad1889_load_adc_buffer_count(chip, size); + ad1889_load_adc_interrupt_count(chip, count); + + /* writes flush */ + ad1889_readw(chip, AD_DS_RAMC); + + spin_unlock_irq(&chip->lock); + + ad1889_debug("prepare capture: addr = 0x%x, count = %u, " + "size = %u, reg = 0x%x, rate = %u\n", chip->ramc.addr, + count, size, reg, rt->rate); + return 0; +} + +/* this is called in atomic context with IRQ disabled. + Must be as fast as possible and not sleep. + DMA should be *triggered* by this call. + The WSMC "WAEN" bit triggers DMA Wave On/Off */ +static int +snd_ad1889_playback_trigger(snd_pcm_substream_t *ss, int cmd) +{ + u16 wsmc; + struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); + + wsmc = ad1889_readw(chip, AD_DS_WSMC); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + /* enable DMA loop & interrupts */ + ad1889_writew(chip, AD_DMA_WAV, AD_DMA_LOOP | AD_DMA_IM_CNT); + wsmc |= AD_DS_WSMC_WAEN; + /* 1 to clear CHSS bit */ + ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_WAVS); + ad1889_unmute(chip); + break; + case SNDRV_PCM_TRIGGER_STOP: + ad1889_mute(chip); + wsmc &= ~AD_DS_WSMC_WAEN; + break; + default: + snd_BUG(); + return -EINVAL; + } + + chip->wave.reg = wsmc; + ad1889_writew(chip, AD_DS_WSMC, wsmc); + ad1889_readw(chip, AD_DS_WSMC); /* flush */ + + /* reset the chip when STOP - will disable IRQs */ + if (cmd == SNDRV_PCM_TRIGGER_STOP) + ad1889_channel_reset(chip, AD_CHAN_WAV); + + return 0; +} + +/* this is called in atomic context with IRQ disabled. + Must be as fast as possible and not sleep. + DMA should be *triggered* by this call. + The RAMC "ADEN" bit triggers DMA ADC On/Off */ +static int +snd_ad1889_capture_trigger(snd_pcm_substream_t *ss, int cmd) +{ + u16 ramc; + struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); + + ramc = ad1889_readw(chip, AD_DS_RAMC); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + /* enable DMA loop & interrupts */ + ad1889_writew(chip, AD_DMA_ADC, AD_DMA_LOOP | AD_DMA_IM_CNT); + ramc |= AD_DS_RAMC_ADEN; + /* 1 to clear CHSS bit */ + ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_ADCS); + break; + case SNDRV_PCM_TRIGGER_STOP: + ramc &= ~AD_DS_RAMC_ADEN; + break; + default: + return -EINVAL; + } + + chip->ramc.reg = ramc; + ad1889_writew(chip, AD_DS_RAMC, ramc); + ad1889_readw(chip, AD_DS_RAMC); /* flush */ + + /* reset the chip when STOP - will disable IRQs */ + if (cmd == SNDRV_PCM_TRIGGER_STOP) + ad1889_channel_reset(chip, AD_CHAN_ADC); + + return 0; +} + +/* Called in atomic context with IRQ disabled */ +static snd_pcm_uframes_t +snd_ad1889_playback_pointer(snd_pcm_substream_t *ss) +{ + size_t ptr = 0; + struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); + + if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN))) + return 0; + + ptr = ad1889_readl(chip, AD_DMA_WAVCA); + ptr -= chip->wave.addr; + + snd_assert((ptr >= 0) && (ptr < chip->wave.size), return 0); + + return bytes_to_frames(ss->runtime, ptr); +} + +/* Called in atomic context with IRQ disabled */ +static snd_pcm_uframes_t +snd_ad1889_capture_pointer(snd_pcm_substream_t *ss) +{ + size_t ptr = 0; + struct snd_ad1889 *chip = snd_pcm_substream_chip(ss); + + if (unlikely(!(chip->ramc.reg & AD_DS_RAMC_ADEN))) + return 0; + + ptr = ad1889_readl(chip, AD_DMA_ADCCA); + ptr -= chip->ramc.addr; + + snd_assert((ptr >= 0) && (ptr < chip->ramc.size), return 0); + + return bytes_to_frames(ss->runtime, ptr); +} + +static snd_pcm_ops_t snd_ad1889_playback_ops = { + .open = snd_ad1889_playback_open, + .close = snd_ad1889_playback_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_ad1889_hw_params, + .hw_free = snd_ad1889_hw_free, + .prepare = snd_ad1889_playback_prepare, + .trigger = snd_ad1889_playback_trigger, + .pointer = snd_ad1889_playback_pointer, +}; + +static snd_pcm_ops_t snd_ad1889_capture_ops = { + .open = snd_ad1889_capture_open, + .close = snd_ad1889_capture_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_ad1889_hw_params, + .hw_free = snd_ad1889_hw_free, + .prepare = snd_ad1889_capture_prepare, + .trigger = snd_ad1889_capture_trigger, + .pointer = snd_ad1889_capture_pointer, +}; + +static irqreturn_t +snd_ad1889_interrupt(int irq, + void *dev_id, + struct pt_regs *regs) +{ + unsigned long st; + struct snd_ad1889 *chip = dev_id; + + st = ad1889_readl(chip, AD_DMA_DISR); + + /* clear ISR */ + ad1889_writel(chip, AD_DMA_DISR, st); + + st &= AD_INTR_MASK; + + if (unlikely(!st)) + return IRQ_NONE; + + if (st & (AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI)) + ad1889_debug("Unexpected master or target abort interrupt!\n"); + + if ((st & AD_DMA_DISR_WAVI) && chip->psubs) + snd_pcm_period_elapsed(chip->psubs); + if ((st & AD_DMA_DISR_ADCI) && chip->csubs) + snd_pcm_period_elapsed(chip->csubs); + + return IRQ_HANDLED; +} + +static void +snd_ad1889_pcm_free(snd_pcm_t *pcm) +{ + struct snd_ad1889 *chip = pcm->private_data; + chip->pcm = NULL; + snd_pcm_lib_preallocate_free_for_all(pcm); +} + +static int __devinit +snd_ad1889_pcm_init(struct snd_ad1889 *chip, int device, snd_pcm_t **rpcm) +{ + int err; + snd_pcm_t *pcm; + + if (rpcm) + *rpcm = NULL; + + err = snd_pcm_new(chip->card, chip->card->driver, device, 1, 1, &pcm); + if (err < 0) + return err; + + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, + &snd_ad1889_playback_ops); + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, + &snd_ad1889_capture_ops); + + pcm->private_data = chip; + pcm->private_free = snd_ad1889_pcm_free; + pcm->info_flags = 0; + strcpy(pcm->name, chip->card->shortname); + + chip->pcm = pcm; + chip->psubs = NULL; + chip->csubs = NULL; + + err = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, + snd_dma_pci_data(chip->pci), + BUFFER_BYTES_MAX / 2, + BUFFER_BYTES_MAX); + + if (err < 0) { + snd_printk(KERN_ERR PFX "buffer allocation error: %d\n", err); + return err; + } + + if (rpcm) + *rpcm = pcm; + + return 0; +} + +static void +snd_ad1889_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer) +{ + struct snd_ad1889 *chip = entry->private_data; + u16 reg; + int tmp; + + reg = ad1889_readw(chip, AD_DS_WSMC); + snd_iprintf(buffer, "Wave output: %s\n", + (reg & AD_DS_WSMC_WAEN) ? "enabled" : "disabled"); + snd_iprintf(buffer, "Wave Channels: %s\n", + (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); + snd_iprintf(buffer, "Wave Quality: %d-bit linear\n", + (reg & AD_DS_WSMC_WA16) ? 16 : 8); + + /* WARQ is at offset 12 */ + tmp = (reg & AD_DS_WSMC_WARQ) ? + (((reg & AD_DS_WSMC_WARQ >> 12) & 0x01) ? 12 : 18) : 4; + tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1; + + snd_iprintf(buffer, "Wave FIFO: %d %s words\n\n", tmp, + (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); + + + snd_iprintf(buffer, "Synthesis output: %s\n", + reg & AD_DS_WSMC_SYEN ? "enabled" : "disabled"); + + /* SYRQ is at offset 4 */ + tmp = (reg & AD_DS_WSMC_SYRQ) ? + (((reg & AD_DS_WSMC_SYRQ >> 4) & 0x01) ? 12 : 18) : 4; + tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1; + + snd_iprintf(buffer, "Synthesis FIFO: %d %s words\n\n", tmp, + (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); + + reg = ad1889_readw(chip, AD_DS_RAMC); + snd_iprintf(buffer, "ADC input: %s\n", + (reg & AD_DS_RAMC_ADEN) ? "enabled" : "disabled"); + snd_iprintf(buffer, "ADC Channels: %s\n", + (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono"); + snd_iprintf(buffer, "ADC Quality: %d-bit linear\n", + (reg & AD_DS_RAMC_AD16) ? 16 : 8); + + /* ACRQ is at offset 4 */ + tmp = (reg & AD_DS_RAMC_ACRQ) ? + (((reg & AD_DS_RAMC_ACRQ >> 4) & 0x01) ? 12 : 18) : 4; + tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1; + + snd_iprintf(buffer, "ADC FIFO: %d %s words\n\n", tmp, + (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono"); + + snd_iprintf(buffer, "Resampler input: %s\n", + reg & AD_DS_RAMC_REEN ? "enabled" : "disabled"); + + /* RERQ is at offset 12 */ + tmp = (reg & AD_DS_RAMC_RERQ) ? + (((reg & AD_DS_RAMC_RERQ >> 12) & 0x01) ? 12 : 18) : 4; + tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1; + + snd_iprintf(buffer, "Resampler FIFO: %d %s words\n\n", tmp, + (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); + + + /* doc says LSB represents -1.5dB, but the max value (-94.5dB) + suggests that LSB is -3dB, which is more coherent with the logarithmic + nature of the dB scale */ + reg = ad1889_readw(chip, AD_DS_WADA); + snd_iprintf(buffer, "Left: %s, -%d dB\n", + (reg & AD_DS_WADA_LWAM) ? "mute" : "unmute", + ((reg & AD_DS_WADA_LWAA) >> 8) * 3); + reg = ad1889_readw(chip, AD_DS_WADA); + snd_iprintf(buffer, "Right: %s, -%d dB\n", + (reg & AD_DS_WADA_RWAM) ? "mute" : "unmute", + ((reg & AD_DS_WADA_RWAA) >> 8) * 3); + + reg = ad1889_readw(chip, AD_DS_WAS); + snd_iprintf(buffer, "Wave samplerate: %u Hz\n", reg); + reg = ad1889_readw(chip, AD_DS_RES); + snd_iprintf(buffer, "Resampler samplerate: %u Hz\n", reg); +} + +static void __devinit +snd_ad1889_proc_init(struct snd_ad1889 *chip) +{ + snd_info_entry_t *entry; + + if (!snd_card_proc_new(chip->card, chip->card->driver, &entry)) + snd_info_set_text_ops(entry, chip, 1024, snd_ad1889_proc_read); +} + +static struct ac97_quirk ac97_quirks[] = { + { + .subvendor = 0x11d4, /* AD */ + .subdevice = 0x1889, /* AD1889 */ + .codec_id = AC97_ID_AD1819, + .name = "AD1889", + .type = AC97_TUNE_HP_ONLY + }, + { } /* terminator */ +}; + +static void __devinit +snd_ad1889_ac97_xinit(struct snd_ad1889 *chip) +{ + u16 reg; + + reg = ad1889_readw(chip, AD_AC97_ACIC); + reg |= AD_AC97_ACIC_ACRD; /* Reset Disable */ + ad1889_writew(chip, AD_AC97_ACIC, reg); + ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */ + udelay(10); + /* Interface Enable */ + reg |= AD_AC97_ACIC_ACIE; + ad1889_writew(chip, AD_AC97_ACIC, reg); + + snd_ad1889_ac97_ready(chip); + + /* Audio Stream Output | Variable Sample Rate Mode */ + reg = ad1889_readw(chip, AD_AC97_ACIC); + reg |= AD_AC97_ACIC_ASOE | AD_AC97_ACIC_VSRM; + ad1889_writew(chip, AD_AC97_ACIC, reg); + ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */ + +} + +static void +snd_ad1889_ac97_bus_free(ac97_bus_t *bus) +{ + struct snd_ad1889 *chip = bus->private_data; + chip->ac97_bus = NULL; +} + +static void +snd_ad1889_ac97_free(ac97_t *ac97) +{ + struct snd_ad1889 *chip = ac97->private_data; + chip->ac97 = NULL; +} + +static int __devinit +snd_ad1889_ac97_init(struct snd_ad1889 *chip, const char *quirk_override) +{ + int err; + ac97_template_t ac97; + static ac97_bus_ops_t ops = { + .write = snd_ad1889_ac97_write, + .read = snd_ad1889_ac97_read, + }; + + /* doing that here, it works. */ + snd_ad1889_ac97_xinit(chip); + + err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus); + if (err < 0) + return err; + + chip->ac97_bus->private_free = snd_ad1889_ac97_bus_free; + + memset(&ac97, 0, sizeof(ac97)); + ac97.private_data = chip; + ac97.private_free = snd_ad1889_ac97_free; + ac97.pci = chip->pci; + + err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97); + if (err < 0) + return err; + + snd_ac97_tune_hardware(chip->ac97, ac97_quirks, quirk_override); + + return 0; +} + +static int +snd_ad1889_free(struct snd_ad1889 *chip) +{ + if (chip->irq < 0) + goto skip_hw; + + spin_lock_irq(&chip->lock); + + ad1889_mute(chip); + + /* Turn off interrupt on count and zero DMA registers */ + ad1889_channel_reset(chip, AD_CHAN_WAV | AD_CHAN_ADC); + + /* clear DISR. If we don't, we'd better jump off the Eiffel Tower */ + ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PTAI | AD_DMA_DISR_PMAI); + ad1889_readl(chip, AD_DMA_DISR); /* flush, dammit! */ + + spin_unlock_irq(&chip->lock); + + synchronize_irq(chip->irq); + + if (chip->irq >= 0) + free_irq(chip->irq, (void*)chip); + +skip_hw: + if (chip->iobase) + iounmap(chip->iobase); + + pci_release_regions(chip->pci); + pci_disable_device(chip->pci); + + kfree(chip); + return 0; +} + +static inline int +snd_ad1889_dev_free(snd_device_t *device) +{ + struct snd_ad1889 *chip = device->device_data; + return snd_ad1889_free(chip); +} + +static int __devinit +snd_ad1889_init(struct snd_ad1889 *chip) +{ + ad1889_writew(chip, AD_DS_CCS, AD_DS_CCS_CLKEN); /* turn on clock */ + ad1889_readw(chip, AD_DS_CCS); /* flush posted write */ + + mdelay(10); + + /* enable Master and Target abort interrupts */ + ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PMAE | AD_DMA_DISR_PTAE); + + return 0; +} + +static int __devinit +snd_ad1889_create(snd_card_t *card, + struct pci_dev *pci, + struct snd_ad1889 **rchip) +{ + int err; + + struct snd_ad1889 *chip; + static snd_device_ops_t ops = { + .dev_free = snd_ad1889_dev_free, + }; + + *rchip = NULL; + + if ((err = pci_enable_device(pci)) < 0) + return err; + + /* check PCI availability (32bit DMA) */ + if (pci_set_dma_mask(pci, 0xffffffff) < 0 || + pci_set_consistent_dma_mask(pci, 0xffffffff) < 0) { + printk(KERN_ERR PFX "error setting 32-bit DMA mask.\n"); + pci_disable_device(pci); + return -ENXIO; + } + + /* allocate chip specific data with zero-filled memory */ + if ((chip = kcalloc(1, sizeof(*chip), GFP_KERNEL)) == NULL) { + pci_disable_device(pci); + return -ENOMEM; + } + + chip->card = card; + card->private_data = chip; + chip->pci = pci; + chip->irq = -1; + + /* (1) PCI resource allocation */ + if ((err = pci_request_regions(pci, card->driver)) < 0) + goto free_and_ret; + + chip->bar = pci_resource_start(pci, 0); + chip->iobase = ioremap_nocache(chip->bar, pci_resource_len(pci, 0)); + if (chip->iobase == NULL) { + printk(KERN_ERR PFX "unable to reserve region.\n"); + err = -EBUSY; + goto free_and_ret; + } + + pci_set_master(pci); + + spin_lock_init(&chip->lock); /* only now can we call ad1889_free */ + + if (request_irq(pci->irq, snd_ad1889_interrupt, + SA_INTERRUPT|SA_SHIRQ, card->driver, (void*)chip)) { + printk(KERN_ERR PFX "cannot obtain IRQ %d\n", pci->irq); + snd_ad1889_free(chip); + return -EBUSY; + } + + chip->irq = pci->irq; + synchronize_irq(chip->irq); + + /* (2) initialization of the chip hardware */ + if ((err = snd_ad1889_init(chip)) < 0) { + snd_ad1889_free(chip); + return err; + } + + if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { + snd_ad1889_free(chip); + return err; + } + + snd_card_set_dev(card, &pci->dev); + + *rchip = chip; + + return 0; + +free_and_ret: + if (chip) + kfree(chip); + pci_disable_device(pci); + + return err; +} + +static int __devinit +snd_ad1889_probe(struct pci_dev *pci, + const struct pci_device_id *pci_id) +{ + int err; + static int devno; + snd_card_t *card; + struct snd_ad1889 *chip; + + /* (1) */ + if (devno >= SNDRV_CARDS) + return -ENODEV; + if (!enable[devno]) { + devno++; + return -ENOENT; + } + + /* (2) */ + card = snd_card_new(index[devno], id[devno], THIS_MODULE, 0); + /* XXX REVISIT: we can probably allocate chip in this call */ + if (card == NULL) + return -ENOMEM; + + strcpy(card->driver, "AD1889"); + strcpy(card->shortname, "Analog Devices AD1889"); + + /* (3) */ + err = snd_ad1889_create(card, pci, &chip); + if (err < 0) + goto free_and_ret; + + /* (4) */ + sprintf(card->longname, "%s at 0x%lx irq %i", + card->shortname, chip->bar, chip->irq); + + /* (5) */ + /* register AC97 mixer */ + err = snd_ad1889_ac97_init(chip, ac97_quirk[devno]); + if (err < 0) + goto free_and_ret; + + err = snd_ad1889_pcm_init(chip, 0, NULL); + if (err < 0) + goto free_and_ret; + + /* register proc interface */ + snd_ad1889_proc_init(chip); + + /* (6) */ + err = snd_card_register(card); + if (err < 0) + goto free_and_ret; + + /* (7) */ + pci_set_drvdata(pci, card); + + devno++; + return 0; + +free_and_ret: + snd_card_free(card); + return err; +} + +static void __devexit +snd_ad1889_remove(struct pci_dev *pci) +{ + snd_card_free(pci_get_drvdata(pci)); + pci_set_drvdata(pci, NULL); +} + +static struct pci_device_id snd_ad1889_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_ANALOG_DEVICES, PCI_DEVICE_ID_AD1889JS) }, + { 0, }, +}; +MODULE_DEVICE_TABLE(pci, snd_ad1889_ids); + +static struct pci_driver ad1889_pci = { + .name = "AD1889 Audio", + .id_table = snd_ad1889_ids, + .probe = snd_ad1889_probe, + .remove = __devexit_p(snd_ad1889_remove), +}; + +static int __init +alsa_ad1889_init(void) +{ + return pci_register_driver(&ad1889_pci); +} + +static void __exit +alsa_ad1889_fini(void) +{ + pci_unregister_driver(&ad1889_pci); +} + +module_init(alsa_ad1889_init); +module_exit(alsa_ad1889_fini); diff --git a/sound/pci/ad1889.h b/sound/pci/ad1889.h new file mode 100644 index 00000000000..5e6dad5341a --- /dev/null +++ b/sound/pci/ad1889.h @@ -0,0 +1,189 @@ +/* Analog Devices 1889 audio driver + * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org> + */ + +#ifndef __AD1889_H__ +#define __AD1889_H__ + +#define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */ +#define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */ +#define AD_DS_WSMC_SYRQ 0x0030 /* synth. fifo request point */ +#define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */ +#define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */ +#define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */ +#define AD_DS_WSMC_WARQ 0x3000 /* wave fifo request point */ + +#define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */ +#define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */ +#define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */ +#define AD_DS_RAMC_ADEN 0x0004 /* ADC channel enable */ +#define AD_DS_RAMC_ACRQ 0x0030 /* ADC fifo request point */ +#define AD_DS_RAMC_REEN 0x0400 /* resampler channel enable */ +#define AD_DS_RAMC_RERQ 0x3000 /* res. fifo request point */ + +#define AD_DS_WADA 0x04 /* wave channel mix attenuation */ +#define AD_DS_WADA_RWAM 0x0080 /* right wave mute */ +#define AD_DS_WADA_RWAA 0x001f /* right wave attenuation */ +#define AD_DS_WADA_LWAM 0x8000 /* left wave mute */ +#define AD_DS_WADA_LWAA 0x3e00 /* left wave attenuation */ + +#define AD_DS_SYDA 0x06 /* synthesis channel mix attenuation */ +#define AD_DS_SYDA_RSYM 0x0080 /* right synthesis mute */ +#define AD_DS_SYDA_RSYA 0x001f /* right synthesis attenuation */ +#define AD_DS_SYDA_LSYM 0x8000 /* left synthesis mute */ +#define AD_DS_SYDA_LSYA 0x3e00 /* left synthesis attenuation */ + +#define AD_DS_WAS 0x08 /* wave channel sample rate */ +#define AD_DS_WAS_WAS 0xffff /* sample rate mask */ + +#define AD_DS_RES 0x0a /* resampler channel sample rate */ +#define AD_DS_RES_RES 0xffff /* sample rate mask */ + +#define AD_DS_CCS 0x0c /* chip control/status */ +#define AD_DS_CCS_ADO 0x0001 /* ADC channel overflow */ +#define AD_DS_CCS_REO 0x0002 /* resampler channel overflow */ +#define AD_DS_CCS_SYU 0x0004 /* synthesis channel underflow */ +#define AD_DS_CCS_WAU 0x0008 /* wave channel underflow */ +/* bits 4 -> 7, 9, 11 -> 14 reserved */ +#define AD_DS_CCS_XTD 0x0100 /* xtd delay control (4096 clock cycles) */ +#define AD_DS_CCS_PDALL 0x0400 /* power */ +#define AD_DS_CCS_CLKEN 0x8000 /* clock */ + +#define AD_DMA_RESBA 0x40 /* RES base address */ +#define AD_DMA_RESCA 0x44 /* RES current address */ +#define AD_DMA_RESBC 0x48 /* RES base count */ +#define AD_DMA_RESCC 0x4c /* RES current count */ + +#define AD_DMA_ADCBA 0x50 /* ADC base address */ +#define AD_DMA_ADCCA 0x54 /* ADC current address */ +#define AD_DMA_ADCBC 0x58 /* ADC base count */ +#define AD_DMA_ADCCC 0x5c /* ADC current count */ + +#define AD_DMA_SYNBA 0x60 /* synth base address */ +#define AD_DMA_SYNCA 0x64 /* synth current address */ +#define AD_DMA_SYNBC 0x68 /* synth base count */ +#define AD_DMA_SYNCC 0x6c /* synth current count */ + +#define AD_DMA_WAVBA 0x70 /* wave base address */ +#define AD_DMA_WAVCA 0x74 /* wave current address */ +#define AD_DMA_WAVBC 0x78 /* wave base count */ +#define AD_DMA_WAVCC 0x7c /* wave current count */ + +#define AD_DMA_RESIC 0x80 /* RES dma interrupt current byte count */ +#define AD_DMA_RESIB 0x84 /* RES dma interrupt base byte count */ + +#define AD_DMA_ADCIC 0x88 /* ADC dma interrupt current byte count */ +#define AD_DMA_ADCIB 0x8c /* ADC dma interrupt base byte count */ + +#define AD_DMA_SYNIC 0x90 /* synth dma interrupt current byte count */ +#define AD_DMA_SYNIB 0x94 /* synth dma interrupt base byte count */ + +#define AD_DMA_WAVIC 0x98 /* wave dma interrupt current byte count */ +#define AD_DMA_WAVIB 0x9c /* wave dma interrupt base byte count */ + +#define AD_DMA_ICC 0xffffff /* current byte count mask */ +#define AD_DMA_IBC 0xffffff /* base byte count mask */ +/* bits 24 -> 31 reserved */ + +/* 4 bytes pad */ +#define AD_DMA_ADC 0xa8 /* ADC dma control and status */ +#define AD_DMA_SYNTH 0xb0 /* Synth dma control and status */ +#define AD_DMA_WAV 0xb8 /* wave dma control and status */ +#define AD_DMA_RES 0xa0 /* Resample dma control and status */ + +#define AD_DMA_SGDE 0x0001 /* SGD mode enable */ +#define AD_DMA_LOOP 0x0002 /* loop enable */ +#define AD_DMA_IM 0x000c /* interrupt mode mask */ +#define AD_DMA_IM_DIS (~AD_DMA_IM) /* disable */ +#define AD_DMA_IM_CNT 0x0004 /* interrupt on count */ +#define AD_DMA_IM_SGD 0x0008 /* interrupt on SGD flag */ +#define AD_DMA_IM_EOL 0x000c /* interrupt on End of Linked List */ +#define AD_DMA_SGDS 0x0030 /* SGD status */ +#define AD_DMA_SFLG 0x0040 /* SGD flag */ +#define AD_DMA_EOL 0x0080 /* SGD end of list */ +/* bits 8 -> 15 reserved */ + +#define AD_DMA_DISR 0xc0 /* dma interrupt status */ +#define AD_DMA_DISR_RESI 0x000001 /* resampler channel interrupt */ +#define AD_DMA_DISR_ADCI 0x000002 /* ADC channel interrupt */ +#define AD_DMA_DISR_SYNI 0x000004 /* synthesis channel interrupt */ +#define AD_DMA_DISR_WAVI 0x000008 /* wave channel interrupt */ +/* bits 4, 5 reserved */ +#define AD_DMA_DISR_SEPS 0x000040 /* serial eeprom status */ +/* bits 7 -> 13 reserved */ +#define AD_DMA_DISR_PMAI 0x004000 /* pci master abort interrupt */ +#define AD_DMA_DISR_PTAI 0x008000 /* pci target abort interrupt */ +#define AD_DMA_DISR_PTAE 0x010000 /* pci target abort interrupt enable */ +#define AD_DMA_DISR_PMAE 0x020000 /* pci master abort interrupt enable */ +/* bits 19 -> 31 reserved */ + +/* interrupt mask */ +#define AD_INTR_MASK (AD_DMA_DISR_RESI|AD_DMA_DISR_ADCI| \ + AD_DMA_DISR_WAVI|AD_DMA_DISR_SYNI| \ + AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI) + +#define AD_DMA_CHSS 0xc4 /* dma channel stop status */ +#define AD_DMA_CHSS_RESS 0x000001 /* resampler channel stopped */ +#define AD_DMA_CHSS_ADCS 0x000002 /* ADC channel stopped */ +#define AD_DMA_CHSS_SYNS 0x000004 /* synthesis channel stopped */ +#define AD_DMA_CHSS_WAVS 0x000008 /* wave channel stopped */ + +#define AD_GPIO_IPC 0xc8 /* gpio port control */ +#define AD_GPIO_OP 0xca /* gpio output port status */ +#define AD_GPIO_IP 0xcc /* gpio input port status */ + +#define AD_AC97_BASE 0x100 /* ac97 base register */ + +#define AD_AC97_RESET 0x100 /* reset */ + +#define AD_AC97_PWR_CTL 0x126 /* == AC97_POWERDOWN */ +#define AD_AC97_PWR_ADC 0x0001 /* ADC ready status */ +#define AD_AC97_PWR_DAC 0x0002 /* DAC ready status */ +#define AD_AC97_PWR_PR0 0x0100 /* PR0 (ADC) powerdown */ +#define AD_AC97_PWR_PR1 0x0200 /* PR1 (DAC) powerdown */ + +#define AD_MISC_CTL 0x176 /* misc control */ +#define AD_MISC_CTL_DACZ 0x8000 /* set for zero fill, unset for repeat */ +#define AD_MISC_CTL_ARSR 0x0001 /* set for SR1, unset for SR0 */ +#define AD_MISC_CTL_ALSR 0x0100 +#define AD_MISC_CTL_DLSR 0x0400 +#define AD_MISC_CTL_DRSR 0x0004 + +#define AD_AC97_SR0 0x178 /* sample rate 0, 0xbb80 == 48K */ +#define AD_AC97_SR0_48K 0xbb80 /* 48KHz */ +#define AD_AC97_SR1 0x17a /* sample rate 1 */ + +#define AD_AC97_ACIC 0x180 /* ac97 codec interface control */ +#define AD_AC97_ACIC_ACIE 0x0001 /* analog codec interface enable */ +#define AD_AC97_ACIC_ACRD 0x0002 /* analog codec reset disable */ +#define AD_AC97_ACIC_ASOE 0x0004 /* audio stream output enable */ +#define AD_AC97_ACIC_VSRM 0x0008 /* variable sample rate mode */ +#define AD_AC97_ACIC_FSDH 0x0100 /* force SDATA_OUT high */ +#define AD_AC97_ACIC_FSYH 0x0200 /* force sync high */ +#define AD_AC97_ACIC_ACRDY 0x8000 /* analog codec ready status */ +/* bits 10 -> 14 reserved */ + + +#define AD_DS_MEMSIZE 512 +#define AD_OPL_MEMSIZE 16 +#define AD_MIDI_MEMSIZE 16 + +#define AD_WAV_STATE 0 +#define AD_ADC_STATE 1 +#define AD_MAX_STATES 2 + +#define AD_CHAN_WAV 0x0001 +#define AD_CHAN_ADC 0x0002 +#define AD_CHAN_RES 0x0004 +#define AD_CHAN_SYN 0x0008 + + +/* The chip would support 4 GB buffers and 16 MB periods, + * but let's not overdo it ... */ +#define BUFFER_BYTES_MAX (256 * 1024) +#define PERIOD_BYTES_MIN 32 +#define PERIOD_BYTES_MAX (BUFFER_BYTES_MAX / 2) +#define PERIODS_MIN 2 +#define PERIODS_MAX (BUFFER_BYTES_MAX / PERIOD_BYTES_MIN) + +#endif /* __AD1889_H__ */ |