diff options
Diffstat (limited to 'include')
41 files changed, 1070 insertions, 6128 deletions
diff --git a/include/asm-xtensa/asmmacro.h b/include/asm-xtensa/asmmacro.h new file mode 100644 index 00000000000..76915cabad1 --- /dev/null +++ b/include/asm-xtensa/asmmacro.h @@ -0,0 +1,153 @@ +/* + * include/asm-xtensa/asmmacro.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 Tensilica Inc. + */ + +#ifndef _XTENSA_ASMMACRO_H +#define _XTENSA_ASMMACRO_H + +#include <asm/variant/core.h> + +/* + * Some little helpers for loops. Use zero-overhead-loops + * where applicable and if supported by the processor. + * + * __loopi ar, at, size, inc + * ar register initialized with the start address + * at scratch register used by macro + * size size immediate value + * inc increment + * + * __loops ar, as, at, inc_log2[, mask_log2][, cond][, ncond] + * ar register initialized with the start address + * as register initialized with the size + * at scratch register use by macro + * inc_log2 increment [in log2] + * mask_log2 mask [in log2] + * cond true condition (used in loop'cond') + * ncond false condition (used in b'ncond') + * + * __loop as + * restart loop. 'as' register must not have been modified! + * + * __endla ar, at, incr + * ar start address (modified) + * as scratch register used by macro + * inc increment + */ + +/* + * loop for given size as immediate + */ + + .macro __loopi ar, at, size, incr + +#if XCHAL_HAVE_LOOPS + movi \at, ((\size + \incr - 1) / (\incr)) + loop \at, 99f +#else + addi \at, \ar, \size + 98: +#endif + + .endm + +/* + * loop for given size in register + */ + + .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond + +#if XCHAL_HAVE_LOOPS + .ifgt \incr_log2 - 1 + addi \at, \as, (1 << \incr_log2) - 1 + .ifnc \mask_log2, + extui \at, \at, \incr_log2, \mask_log2 + .else + srli \at, \at, \incr_log2 + .endif + .endif + loop\cond \at, 99f +#else + .ifnc \mask_log2, + extui \at, \as, \incr_log2, \mask_log2 + .else + .ifnc \ncond, + srli \at, \as, \incr_log2 + .endif + .endif + .ifnc \ncond, + b\ncond \at, 99f + + .endif + .ifnc \mask_log2, + slli \at, \at, \incr_log2 + add \at, \ar, \at + .else + add \at, \ar, \as + .endif +#endif + 98: + + .endm + +/* + * loop from ar to ax + */ + + .macro __loopt ar, as, at, incr_log2 + +#if XCHAL_HAVE_LOOPS + sub \at, \as, \ar + .ifgt \incr_log2 - 1 + addi \at, \at, (1 << \incr_log2) - 1 + srli \at, \at, \incr_log2 + .endif + loop \at, 99f +#else + 98: +#endif + + .endm + +/* + * restart loop. registers must be unchanged + */ + + .macro __loop as + +#if XCHAL_HAVE_LOOPS + loop \as, 99f +#else + 98: +#endif + + .endm + +/* + * end of loop with no increment of the address. + */ + + .macro __endl ar, as +#if !XCHAL_HAVE_LOOPS + bltu \ar, \as, 98b +#endif + 99: + .endm + +/* + * end of loop with increment of the address. + */ + + .macro __endla ar, as, incr + addi \ar, \ar, \incr + __endl \ar \as + .endm + + +#endif /* _XTENSA_ASMMACRO_H */ diff --git a/include/asm-xtensa/byteorder.h b/include/asm-xtensa/byteorder.h index 0ba72ddbf88..0f540a5f4c0 100644 --- a/include/asm-xtensa/byteorder.h +++ b/include/asm-xtensa/byteorder.h @@ -11,7 +11,6 @@ #ifndef _XTENSA_BYTEORDER_H #define _XTENSA_BYTEORDER_H -#include <asm/processor.h> #include <asm/types.h> static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) diff --git a/include/asm-xtensa/cache.h b/include/asm-xtensa/cache.h index 1e79c0e2746..1c4a78f29ae 100644 --- a/include/asm-xtensa/cache.h +++ b/include/asm-xtensa/cache.h @@ -4,7 +4,6 @@ * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * 2 of the License, or (at your option) any later version. * * (C) 2001 - 2005 Tensilica Inc. */ @@ -12,21 +11,14 @@ #ifndef _XTENSA_CACHE_H #define _XTENSA_CACHE_H -#include <xtensa/config/core.h> +#include <asm/variant/core.h> -#if XCHAL_ICACHE_SIZE > 0 -# if (XCHAL_ICACHE_SIZE % (XCHAL_ICACHE_LINESIZE*XCHAL_ICACHE_WAYS*4)) != 0 -# error cache configuration outside expected/supported range! -# endif -#endif +#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH +#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE +#define SMP_CACHE_BYTES L1_CACHE_BYTES -#if XCHAL_DCACHE_SIZE > 0 -# if (XCHAL_DCACHE_SIZE % (XCHAL_DCACHE_LINESIZE*XCHAL_DCACHE_WAYS*4)) != 0 -# error cache configuration outside expected/supported range! -# endif -#endif +#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) +#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) -#define L1_CACHE_SHIFT XCHAL_CACHE_LINEWIDTH_MAX -#define L1_CACHE_BYTES XCHAL_CACHE_LINESIZE_MAX #endif /* _XTENSA_CACHE_H */ diff --git a/include/asm-xtensa/cacheasm.h b/include/asm-xtensa/cacheasm.h new file mode 100644 index 00000000000..2c20a58f94c --- /dev/null +++ b/include/asm-xtensa/cacheasm.h @@ -0,0 +1,177 @@ +/* + * include/asm-xtensa/cacheasm.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 Tensilica Inc. + */ + +#include <asm/cache.h> +#include <asm/asmmacro.h> +#include <linux/stringify.h> + +/* + * Define cache functions as macros here so that they can be used + * by the kernel and boot loader. We should consider moving them to a + * library that can be linked by both. + * + * Locking + * + * ___unlock_dcache_all + * ___unlock_icache_all + * + * Flush and invaldating + * + * ___flush_invalidate_dcache_{all|range|page} + * ___flush_dcache_{all|range|page} + * ___invalidate_dcache_{all|range|page} + * ___invalidate_icache_{all|range|page} + * + */ + + .macro __loop_cache_all ar at insn size line_width + + movi \ar, 0 + + __loopi \ar, \at, \size, (4 << (\line_width)) + \insn \ar, 0 << (\line_width) + \insn \ar, 1 << (\line_width) + \insn \ar, 2 << (\line_width) + \insn \ar, 3 << (\line_width) + __endla \ar, \at, 4 << (\line_width) + + .endm + + + .macro __loop_cache_range ar as at insn line_width + + extui \at, \ar, 0, \line_width + add \as, \as, \at + + __loops \ar, \as, \at, \line_width + \insn \ar, 0 + __endla \ar, \at, (1 << (\line_width)) + + .endm + + + .macro __loop_cache_page ar at insn line_width + + __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width) + \insn \ar, 0 << (\line_width) + \insn \ar, 1 << (\line_width) + \insn \ar, 2 << (\line_width) + \insn \ar, 3 << (\line_width) + __endla \ar, \at, 4 << (\line_width) + + .endm + + +#if XCHAL_DCACHE_LINE_LOCKABLE + + .macro ___unlock_dcache_all ar at + + __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH + + .endm + +#endif + +#if XCHAL_ICACHE_LINE_LOCKABLE + + .macro ___unlock_icache_all ar at + + __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH + + .endm +#endif + + .macro ___flush_invalidate_dcache_all ar at + + __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH + + .endm + + + .macro ___flush_dcache_all ar at + + __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH + + .endm + + + .macro ___invalidate_dcache_all ar at + + __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ + XCHAL_DCACHE_LINEWIDTH + + .endm + + + .macro ___invalidate_icache_all ar at + + __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ + XCHAL_ICACHE_LINEWIDTH + + .endm + + + + .macro ___flush_invalidate_dcache_range ar as at + + __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH + + .endm + + + .macro ___flush_dcache_range ar as at + + __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH + + .endm + + + .macro ___invalidate_dcache_range ar as at + + __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH + + .endm + + + .macro ___invalidate_icache_range ar as at + + __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH + + .endm + + + + .macro ___flush_invalidate_dcache_page ar as + + __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH + + .endm + + + .macro ___flush_dcache_page ar as + + __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH + + .endm + + + .macro ___invalidate_dcache_page ar as + + __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH + + .endm + + + .macro ___invalidate_icache_page ar as + + __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH + + .endm + diff --git a/include/asm-xtensa/cacheflush.h b/include/asm-xtensa/cacheflush.h index 44a36e08784..337765b629d 100644 --- a/include/asm-xtensa/cacheflush.h +++ b/include/asm-xtensa/cacheflush.h @@ -5,7 +5,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * (C) 2001 - 2005 Tensilica Inc. + * (C) 2001 - 2006 Tensilica Inc. */ #ifndef _XTENSA_CACHEFLUSH_H diff --git a/include/asm-xtensa/checksum.h b/include/asm-xtensa/checksum.h index 5435aff9a4b..23534c60b3a 100644 --- a/include/asm-xtensa/checksum.h +++ b/include/asm-xtensa/checksum.h @@ -12,7 +12,7 @@ #define _XTENSA_CHECKSUM_H #include <linux/in6.h> -#include <xtensa/config/core.h> +#include <asm/variant/core.h> /* * computes the checksum of a memory block at buff, length len, diff --git a/include/asm-xtensa/coprocessor.h b/include/asm-xtensa/coprocessor.h index 5093034723b..bd09ec02d57 100644 --- a/include/asm-xtensa/coprocessor.h +++ b/include/asm-xtensa/coprocessor.h @@ -11,7 +11,16 @@ #ifndef _XTENSA_COPROCESSOR_H #define _XTENSA_COPROCESSOR_H -#include <xtensa/config/core.h> +#include <asm/variant/core.h> +#include <asm/variant/tie.h> + +#if !XCHAL_HAVE_CP + +#define XTENSA_CP_EXTRA_OFFSET 0 +#define XTENSA_CP_EXTRA_ALIGN 1 /* must be a power of 2 */ +#define XTENSA_CP_EXTRA_SIZE 0 + +#else #define XTOFS(last_start,last_size,align) \ ((last_start+last_size+align-1) & -align) @@ -67,4 +76,6 @@ extern void save_coprocessor_registers(void*, int); # endif #endif +#endif + #endif /* _XTENSA_COPROCESSOR_H */ diff --git a/include/asm-xtensa/dma.h b/include/asm-xtensa/dma.h index db2633f6778..e30f3abf48f 100644 --- a/include/asm-xtensa/dma.h +++ b/include/asm-xtensa/dma.h @@ -12,7 +12,6 @@ #define _XTENSA_DMA_H #include <asm/io.h> /* need byte IO */ -#include <xtensa/config/core.h> /* * This is only to be defined if we have PC-like DMA. @@ -44,7 +43,9 @@ * enters another area, and virt_to_phys() may not return * the value desired). */ -#define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KSEG_CACHED_SIZE - 1) + +#define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KIO_SIZE - 1) + /* Reserve and release a DMA channel */ extern int request_dma(unsigned int dmanr, const char * device_id); diff --git a/include/asm-xtensa/elf.h b/include/asm-xtensa/elf.h index de0667453b2..f0f9fd8560a 100644 --- a/include/asm-xtensa/elf.h +++ b/include/asm-xtensa/elf.h @@ -13,9 +13,8 @@ #ifndef _XTENSA_ELF_H #define _XTENSA_ELF_H +#include <asm/variant/core.h> #include <asm/ptrace.h> -#include <asm/coprocessor.h> -#include <xtensa/config/core.h> /* Xtensa processor ELF architecture-magic number */ @@ -118,11 +117,15 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG]; * using memcpy(). But we do allow space for such alignment, * to allow optimizations of layout and copying. */ - +#if 0 #define TOTAL_FPREGS_SIZE \ (4 + XTENSA_CPE_LTABLE_SIZE + XTENSA_CP_EXTRA_SIZE) #define ELF_NFPREG \ ((TOTAL_FPREGS_SIZE + sizeof(elf_fpreg_t) - 1) / sizeof(elf_fpreg_t)) +#else +#define TOTAL_FPREGS_SIZE 0 +#define ELF_NFPREG 0 +#endif typedef unsigned int elf_fpreg_t; typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; diff --git a/include/asm-xtensa/fixmap.h b/include/asm-xtensa/fixmap.h deleted file mode 100644 index 4423b8ad495..00000000000 --- a/include/asm-xtensa/fixmap.h +++ /dev/null @@ -1,252 +0,0 @@ -/* - * include/asm-xtensa/fixmap.h - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001 - 2005 Tensilica Inc. - */ - -#ifndef _XTENSA_FIXMAP_H -#define _XTENSA_FIXMAP_H - -#include <asm/processor.h> - -#ifdef CONFIG_MMU - -/* - * Here we define all the compile-time virtual addresses. - */ - -#if XCHAL_SEG_MAPPABLE_VADDR != 0 -# error "Current port requires virtual user space starting at 0" -#endif -#if XCHAL_SEG_MAPPABLE_SIZE < 0x80000000 -# error "Current port requires at least 0x8000000 bytes for user space" -#endif - -/* Verify instruction/data ram/rom and xlmi don't overlay vmalloc space. */ - -#define __IN_VMALLOC(addr) \ - (((addr) >= VMALLOC_START) && ((addr) < VMALLOC_END)) -#define __SPAN_VMALLOC(start,end) \ - (((start) < VMALLOC_START) && ((end) >= VMALLOC_END)) -#define INSIDE_VMALLOC(start,end) \ - (__IN_VMALLOC((start)) || __IN_VMALLOC(end) || __SPAN_VMALLOC((start),(end))) - -#if XCHAL_NUM_INSTROM -# if XCHAL_NUM_INSTROM == 1 -# if INSIDE_VMALLOC(XCHAL_INSTROM0_VADDR,XCHAL_INSTROM0_VADDR+XCHAL_INSTROM0_SIZE) -# error vmalloc range conflicts with instrom0 -# endif -# endif -# if XCHAL_NUM_INSTROM == 2 -# if INSIDE_VMALLOC(XCHAL_INSTROM1_VADDR,XCHAL_INSTROM1_VADDR+XCHAL_INSTROM1_SIZE) -# error vmalloc range conflicts with instrom1 -# endif -# endif -#endif - -#if XCHAL_NUM_INSTRAM -# if XCHAL_NUM_INSTRAM == 1 -# if INSIDE_VMALLOC(XCHAL_INSTRAM0_VADDR,XCHAL_INSTRAM0_VADDR+XCHAL_INSTRAM0_SIZE) -# error vmalloc range conflicts with instram0 -# endif -# endif -# if XCHAL_NUM_INSTRAM == 2 -# if INSIDE_VMALLOC(XCHAL_INSTRAM1_VADDR,XCHAL_INSTRAM1_VADDR+XCHAL_INSTRAM1_SIZE) -# error vmalloc range conflicts with instram1 -# endif -# endif -#endif - -#if XCHAL_NUM_DATAROM -# if XCHAL_NUM_DATAROM == 1 -# if INSIDE_VMALLOC(XCHAL_DATAROM0_VADDR,XCHAL_DATAROM0_VADDR+XCHAL_DATAROM0_SIZE) -# error vmalloc range conflicts with datarom0 -# endif -# endif -# if XCHAL_NUM_DATAROM == 2 -# if INSIDE_VMALLOC(XCHAL_DATAROM1_VADDR,XCHAL_DATAROM1_VADDR+XCHAL_DATAROM1_SIZE) -# error vmalloc range conflicts with datarom1 -# endif -# endif -#endif - -#if XCHAL_NUM_DATARAM -# if XCHAL_NUM_DATARAM == 1 -# if INSIDE_VMALLOC(XCHAL_DATARAM0_VADDR,XCHAL_DATARAM0_VADDR+XCHAL_DATARAM0_SIZE) -# error vmalloc range conflicts with dataram0 -# endif -# endif -# if XCHAL_NUM_DATARAM == 2 -# if INSIDE_VMALLOC(XCHAL_DATARAM1_VADDR,XCHAL_DATARAM1_VADDR+XCHAL_DATARAM1_SIZE) -# error vmalloc range conflicts with dataram1 -# endif -# endif -#endif - -#if XCHAL_NUM_XLMI -# if XCHAL_NUM_XLMI == 1 -# if INSIDE_VMALLOC(XCHAL_XLMI0_VADDR,XCHAL_XLMI0_VADDR+XCHAL_XLMI0_SIZE) -# error vmalloc range conflicts with xlmi0 -# endif -# endif -# if XCHAL_NUM_XLMI == 2 -# if INSIDE_VMALLOC(XCHAL_XLMI1_VADDR,XCHAL_XLMI1_VADDR+XCHAL_XLMI1_SIZE) -# error vmalloc range conflicts with xlmi1 -# endif -# endif -#endif - -#if (XCHAL_NUM_INSTROM > 2) || \ - (XCHAL_NUM_INSTRAM > 2) || \ - (XCHAL_NUM_DATARAM > 2) || \ - (XCHAL_NUM_DATAROM > 2) || \ - (XCHAL_NUM_XLMI > 2) -# error Insufficient checks on vmalloc above for more than 2 devices -#endif - -/* - * USER_VM_SIZE does not necessarily equal TASK_SIZE. We bumped - * TASK_SIZE down to 0x4000000 to simplify the handling of windowed - * call instructions (currently limited to a range of 1 GByte). User - * tasks may very well reclaim the VM space from 0x40000000 to - * 0x7fffffff in the future, so we do not want the kernel becoming - * accustomed to having any of its stuff (e.g., page tables) in this - * region. This VM region is no-man's land for now. - */ - -#define USER_VM_START XCHAL_SEG_MAPPABLE_VADDR -#define USER_VM_SIZE 0x80000000 - -/* Size of page table: */ - -#define PGTABLE_SIZE_BITS (32 - XCHAL_MMU_MIN_PTE_PAGE_SIZE + 2) -#define PGTABLE_SIZE (1L << PGTABLE_SIZE_BITS) - -/* All kernel-mappable space: */ - -#define KERNEL_ALLMAP_START (USER_VM_START + USER_VM_SIZE) -#define KERNEL_ALLMAP_SIZE (XCHAL_SEG_MAPPABLE_SIZE - KERNEL_ALLMAP_START) - -/* Carve out page table at start of kernel-mappable area: */ - -#if KERNEL_ALLMAP_SIZE < PGTABLE_SIZE -#error "Gimme some space for page table!" -#endif -#define PGTABLE_START KERNEL_ALLMAP_START - -/* Remaining kernel-mappable space: */ - -#define KERNEL_MAPPED_START (KERNEL_ALLMAP_START + PGTABLE_SIZE) -#define KERNEL_MAPPED_SIZE (KERNEL_ALLMAP_SIZE - PGTABLE_SIZE) - -#if KERNEL_MAPPED_SIZE < 0x01000000 /* 16 MB is arbitrary for now */ -# error "Shouldn't the kernel have at least *some* mappable space?" -#endif - -#define MAX_LOW_MEMORY XCHAL_KSEG_CACHED_SIZE - -#endif - -/* - * Some constants used elsewhere, but perhaps only in Xtensa header - * files, so maybe we can get rid of some and access compile-time HAL - * directly... - * - * Note: We assume that system RAM is located at the very start of the - * kernel segments !! - */ -#define KERNEL_VM_LOW XCHAL_KSEG_CACHED_VADDR -#define KERNEL_VM_HIGH XCHAL_KSEG_BYPASS_VADDR -#define KERNEL_SPACE XCHAL_KSEG_CACHED_VADDR - -/* - * Returns the physical/virtual addresses of the kernel space - * (works with the cached kernel segment only, which is the - * one normally used for kernel operation). - */ - -/* PHYSICAL BYPASS CACHED - * - * bypass vaddr bypass paddr * cached vaddr - * cached vaddr cached paddr bypass vaddr * - * bypass paddr * bypass vaddr cached vaddr - * cached paddr * bypass vaddr cached vaddr - * other * * * - */ - -#define PHYSADDR(a) \ -(((unsigned)(a) >= XCHAL_KSEG_BYPASS_VADDR \ - && (unsigned)(a) < XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_BYPASS_SIZE) ? \ - (unsigned)(a) - XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_BYPASS_PADDR : \ - ((unsigned)(a) >= XCHAL_KSEG_CACHED_VADDR \ - && (unsigned)(a) < XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_CACHED_SIZE) ? \ - (unsigned)(a) - XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_CACHED_PADDR : \ - (unsigned)(a)) - -#define BYPASS_ADDR(a) \ -(((unsigned)(a) >= XCHAL_KSEG_BYPASS_PADDR \ - && (unsigned)(a) < XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_BYPASS_SIZE) ? \ - (unsigned)(a) - XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_BYPASS_VADDR : \ - ((unsigned)(a) >= XCHAL_KSEG_CACHED_PADDR \ - && (unsigned)(a) < XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_CACHED_SIZE) ? \ - (unsigned)(a) - XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_BYPASS_VADDR : \ - ((unsigned)(a) >= XCHAL_KSEG_CACHED_VADDR \ - && (unsigned)(a) < XCHAL_KSEG_CACHED_VADDR+XCHAL_KSEG_CACHED_SIZE)? \ - (unsigned)(a) - XCHAL_KSEG_CACHED_VADDR+XCHAL_KSEG_BYPASS_VADDR: \ - (unsigned)(a)) - -#define CACHED_ADDR(a) \ -(((unsigned)(a) >= XCHAL_KSEG_BYPASS_PADDR \ - && (unsigned)(a) < XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_BYPASS_SIZE) ? \ - (unsigned)(a) - XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_CACHED_VADDR : \ - ((unsigned)(a) >= XCHAL_KSEG_CACHED_PADDR \ - && (unsigned)(a) < XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_CACHED_SIZE) ? \ - (unsigned)(a) - XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_CACHED_VADDR : \ - ((unsigned)(a) >= XCHAL_KSEG_BYPASS_VADDR \ - && (unsigned)(a) < XCHAL_KSEG_BYPASS_VADDR+XCHAL_KSEG_BYPASS_SIZE) ? \ - (unsigned)(a) - XCHAL_KSEG_BYPASS_VADDR+XCHAL_KSEG_CACHED_VADDR : \ - (unsigned)(a)) - -#define PHYSADDR_IO(a) \ -(((unsigned)(a) >= XCHAL_KIO_BYPASS_VADDR \ - && (unsigned)(a) < XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_BYPASS_SIZE) ? \ - (unsigned)(a) - XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_BYPASS_PADDR : \ - ((unsigned)(a) >= XCHAL_KIO_CACHED_VADDR \ - && (unsigned)(a) < XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_CACHED_SIZE) ? \ - (unsigned)(a) - XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_CACHED_PADDR : \ - (unsigned)(a)) - -#define BYPASS_ADDR_IO(a) \ -(((unsigned)(a) >= XCHAL_KIO_BYPASS_PADDR \ - && (unsigned)(a) < XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_BYPASS_SIZE) ? \ - (unsigned)(a) - XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_BYPASS_VADDR : \ - ((unsigned)(a) >= XCHAL_KIO_CACHED_PADDR \ - && (unsigned)(a) < XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_CACHED_SIZE) ? \ - (unsigned)(a) - XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_BYPASS_VADDR : \ - ((unsigned)(a) >= XCHAL_KIO_CACHED_VADDR \ - && (unsigned)(a) < XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_CACHED_SIZE) ? \ - (unsigned)(a) - XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_BYPASS_VADDR : \ - (unsigned)(a)) - -#define CACHED_ADDR_IO(a) \ -(((unsigned)(a) >= XCHAL_KIO_BYPASS_PADDR \ - && (unsigned)(a) < XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_BYPASS_SIZE) ? \ - (unsigned)(a) - XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_CACHED_VADDR : \ - ((unsigned)(a) >= XCHAL_KIO_CACHED_PADDR \ - && (unsigned)(a) < XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_CACHED_SIZE) ? \ - (unsigned)(a) - XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_CACHED_VADDR : \ - ((unsigned)(a) >= XCHAL_KIO_BYPASS_VADDR \ - && (unsigned)(a) < XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_BYPASS_SIZE) ? \ - (unsigned)(a) - XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_CACHED_VADDR : \ - (unsigned)(a)) - -#endif /* _XTENSA_ADDRSPACE_H */ - - - - - diff --git a/include/asm-xtensa/io.h b/include/asm-xtensa/io.h index 556e5eed34f..31ffc3f119c 100644 --- a/include/asm-xtensa/io.h +++ b/include/asm-xtensa/io.h @@ -1,5 +1,5 @@ /* - * linux/include/asm-xtensa/io. |