diff options
Diffstat (limited to 'include/asm-mips/dec')
| -rw-r--r-- | include/asm-mips/dec/ecc.h | 55 | ||||
| -rw-r--r-- | include/asm-mips/dec/interrupts.h | 126 | ||||
| -rw-r--r-- | include/asm-mips/dec/ioasic.h | 38 | ||||
| -rw-r--r-- | include/asm-mips/dec/ioasic_addrs.h | 152 | ||||
| -rw-r--r-- | include/asm-mips/dec/ioasic_ints.h | 74 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn01.h | 90 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn02.h | 91 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn02ba.h | 67 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn02ca.h | 79 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn02xa.h | 84 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn03.h | 74 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn05.h | 76 | ||||
| -rw-r--r-- | include/asm-mips/dec/kn230.h | 26 | ||||
| -rw-r--r-- | include/asm-mips/dec/machtype.h | 27 | ||||
| -rw-r--r-- | include/asm-mips/dec/prom.h | 174 | ||||
| -rw-r--r-- | include/asm-mips/dec/system.h | 19 |
16 files changed, 0 insertions, 1252 deletions
diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h deleted file mode 100644 index 707ffdbc9ad..00000000000 --- a/include/asm-mips/dec/ecc.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * include/asm-mips/dec/ecc.h - * - * ECC handling logic definitions common to DECstation/DECsystem - * 5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and - * DECsystem 5900 (KN03), 5900/260 (KN05) systems. - * - * Copyright (C) 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_ECC_H -#define __ASM_MIPS_DEC_ECC_H - -/* - * Error Address Register bits. - * The register is r/wc -- any write clears it. - */ -#define KN0X_EAR_VALID (1<<31) /* error data valid, bus IRQ */ -#define KN0X_EAR_CPU (1<<30) /* CPU/DMA transaction */ -#define KN0X_EAR_WRITE (1<<29) /* write/read transaction */ -#define KN0X_EAR_ECCERR (1<<28) /* ECC/timeout or overrun */ -#define KN0X_EAR_RES_27 (1<<27) /* unused */ -#define KN0X_EAR_ADDRESS (0x7ffffff<<0) /* address involved */ - -/* - * Error Syndrome Register bits. - * The register is frozen when EAR.VALID is set, otherwise it records bits - * from the last memory read. The register is r/wc -- any write clears it. - */ -#define KN0X_ESR_VLDHI (1<<31) /* error data valid hi word */ -#define KN0X_ESR_CHKHI (0x7f<<24) /* check bits read from mem */ -#define KN0X_ESR_SNGHI (1<<23) /* single/double bit error */ -#define KN0X_ESR_SYNHI (0x7f<<16) /* syndrome from ECC logic */ -#define KN0X_ESR_VLDLO (1<<15) /* error data valid lo word */ -#define KN0X_ESR_CHKLO (0x7f<<8) /* check bits read from mem */ -#define KN0X_ESR_SNGLO (1<<7) /* single/double bit error */ -#define KN0X_ESR_SYNLO (0x7f<<0) /* syndrome from ECC logic */ - - -#ifndef __ASSEMBLY__ - -#include <linux/interrupt.h> - -struct pt_regs; - -extern void dec_ecc_be_init(void); -extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup); -extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id); -#endif - -#endif /* __ASM_MIPS_DEC_ECC_H */ diff --git a/include/asm-mips/dec/interrupts.h b/include/asm-mips/dec/interrupts.h deleted file mode 100644 index e10d341067c..00000000000 --- a/include/asm-mips/dec/interrupts.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Miscellaneous definitions used to initialise the interrupt vector table - * with the machine-specific interrupt routines. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997 by Paul M. Antoine. - * reworked 1998 by Harald Koerfgen. - * Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki - */ - -#ifndef __ASM_DEC_INTERRUPTS_H -#define __ASM_DEC_INTERRUPTS_H - -#include <irq.h> -#include <asm/mipsregs.h> - - -/* - * The list of possible system devices which provide an - * interrupt. Not all devices exist on a given system. - */ -#define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */ - -/* Ordinary interrupts */ -#define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */ -#define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */ -#define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */ -#define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */ -#define DEC_IRQ_FLOPPY 5 /* 82077 FDC */ -#define DEC_IRQ_FPU 6 /* R3k FPU */ -#define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */ -#define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */ -#define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */ -#define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */ -#define DEC_IRQ_PSU 11 /* power supply unit warning */ -#define DEC_IRQ_RTC 12 /* DS1287 RTC */ -#define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */ -#define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */ -#define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */ -#define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */ -#define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */ -#define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */ -#define DEC_IRQ_TIMER 19 /* ARC periodic timer */ -#define DEC_IRQ_VIDEO 20 /* framebuffer */ - -/* I/O ASIC DMA interrupts */ -#define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */ -#define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */ -#define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */ -#define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */ -#define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */ -#define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */ -#define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */ -#define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */ -#define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */ -#define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */ -#define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */ -#define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */ -#define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */ -#define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */ -#define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */ -#define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */ -#define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */ -#define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */ -#define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */ -#define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */ - -/* TC5 & TC6 are virtual slots for KN02's onboard devices */ -#define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */ -#define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */ - -#define DEC_NR_INTS 41 - - -/* Largest of cpu mask_nr tables. */ -#define DEC_MAX_CPU_INTS 6 -/* Largest of asic mask_nr tables. */ -#define DEC_MAX_ASIC_INTS 9 - - -/* - * CPU interrupt bits common to all systems. - */ -#define DEC_CPU_INR_FPU 7 /* R3k FPU */ -#define DEC_CPU_INR_SW1 1 /* software #1 */ -#define DEC_CPU_INR_SW0 0 /* software #0 */ - -#define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */ - -#define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE) -#define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP)) -#define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP) - - -#ifndef __ASSEMBLY__ - -/* - * Interrupt table structures to hide differences between systems. - */ -typedef union { int i; void *p; } int_ptr; -extern int dec_interrupt[DEC_NR_INTS]; -extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2]; -extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2]; -extern int cpu_fpu_mask; - - -/* - * Common interrupt routine prototypes for all DECStations - */ -extern void kn02_io_int(void); -extern void kn02xa_io_int(void); -extern void kn03_io_int(void); -extern void asic_dma_int(void); -extern void asic_all_int(void); -extern void kn02_all_int(void); -extern void cpu_all_int(void); - -extern void dec_intr_unimplemented(void); -extern void asic_intr_unimplemented(void); - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-mips/dec/ioasic.h b/include/asm-mips/dec/ioasic.h deleted file mode 100644 index 98badd6bf22..00000000000 --- a/include/asm-mips/dec/ioasic.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * include/asm-mips/dec/ioasic.h - * - * DEC I/O ASIC access operations. - * - * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef __ASM_DEC_IOASIC_H -#define __ASM_DEC_IOASIC_H - -#include <linux/spinlock.h> -#include <linux/types.h> - -extern spinlock_t ioasic_ssr_lock; - -extern volatile u32 *ioasic_base; - -static inline void ioasic_write(unsigned int reg, u32 v) -{ - ioasic_base[reg / 4] = v; -} - -static inline u32 ioasic_read(unsigned int reg) -{ - return ioasic_base[reg / 4]; -} - -extern void init_ioasic_irqs(int base); - -extern void dec_ioasic_clocksource_init(void); - -#endif /* __ASM_DEC_IOASIC_H */ diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h deleted file mode 100644 index 4cbc1f8a112..00000000000 --- a/include/asm-mips/dec/ioasic_addrs.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Definitions for the address map in the JUNKIO Asic - * - * Created with Information from: - * - * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual" - * - * and the Mach Sources - * - * Copyright (C) 199x the Anonymous - * Copyright (C) 2002, 2003 Maciej W. Rozycki - */ - -#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H -#define __ASM_MIPS_DEC_IOASIC_ADDRS_H - -#define IOASIC_SLOT_SIZE 0x00040000 - -/* - * Address ranges decoded by the I/O ASIC for onboard devices. - */ -#define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE) /* system board ROM */ -#define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ -#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ -#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ -#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */ -#define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE) /* VDAC (maxine) */ -#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */ -#define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE) /* VDAC (maxine) */ -#define IOASIC_TOY (8*IOASIC_SLOT_SIZE) /* RTC */ -#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE) /* ISDN (maxine) */ -#define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE) /* bus error address (3max+) */ -#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE) /* ECC syndrome (3max+) */ -#define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE) /* ACCESS.bus (maxine) */ -#define IOASIC_MCR (11*IOASIC_SLOT_SIZE) /* memory control (3max+) */ -#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */ -#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ -#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */ -#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */ -#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ - - -/* - * Offsets for I/O ASIC registers - * (relative to (dec_kn_slot_base + IOASIC_IOCTL)). - */ - /* all systems */ -#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */ -#define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */ -#define IO_REG_LANCE_DMA_P 0x20 /* LANCE DMA Pointer */ -#define IO_REG_SCC0A_T_DMA_P 0x30 /* SCC0A Transmit DMA Pointer */ -#define IO_REG_SCC0A_R_DMA_P 0x40 /* SCC0A Receive DMA Pointer */ - - /* except Maxine */ -#define IO_REG_SCC1A_T_DMA_P 0x50 /* SCC1A Transmit DMA Pointer */ -#define IO_REG_SCC1A_R_DMA_P 0x60 /* SCC1A Receive DMA Pointer */ - - /* Maxine */ -#define IO_REG_AB_T_DMA_P 0x50 /* ACCESS.bus Transmit DMA Pointer */ -#define IO_REG_AB_R_DMA_P 0x60 /* ACCESS.bus Receive DMA Pointer */ -#define IO_REG_FLOPPY_DMA_P 0x70 /* Floppy DMA Pointer */ -#define IO_REG_ISDN_T_DMA_P 0x80 /* ISDN Transmit DMA Pointer */ -#define IO_REG_ISDN_T_DMA_BP 0x90 /* ISDN Transmit DMA Buffer Pointer */ -#define IO_REG_ISDN_R_DMA_P 0xa0 /* ISDN Receive DMA Pointer */ -#define IO_REG_ISDN_R_DMA_BP 0xb0 /* ISDN Receive DMA Buffer Pointer */ - - /* all systems */ -#define IO_REG_DATA_0 0xc0 /* System Data Buffer 0 */ -#define IO_REG_DATA_1 0xd0 /* System Data Buffer 1 */ -#define IO_REG_DATA_2 0xe0 /* System Data Buffer 2 */ -#define IO_REG_DATA_3 0xf0 /* System Data Buffer 3 */ - - /* all systems */ -#define IO_REG_SSR 0x100 /* System Support Register */ -#define IO_REG_SIR 0x110 /* System Interrupt Register */ -#define IO_REG_SIMR 0x120 /* System Interrupt Mask Reg. */ -#define IO_REG_SAR 0x130 /* System Address Register */ - - /* Maxine */ -#define IO_REG_ISDN_T_DATA 0x140 /* ISDN Xmit Data Register */ -#define IO_REG_ISDN_R_DATA 0x150 /* ISDN Receive Data Register */ - - /* all systems */ -#define IO_REG_LANCE_SLOT 0x160 /* LANCE I/O Slot Register */ -#define IO_REG_SCSI_SLOT 0x170 /* SCSI Slot Register */ -#define IO_REG_SCC0A_SLOT 0x180 /* SCC0A DMA Slot Register */ - - /* except Maxine */ -#define IO_REG_SCC1A_SLOT 0x190 /* SCC1A DMA Slot Register */ - - /* Maxine */ -#define IO_REG_AB_SLOT 0x190 /* ACCESS.bus DMA Slot Register */ -#define IO_REG_FLOPPY_SLOT 0x1a0 /* Floppy Slot Register */ - - /* all systems */ -#define IO_REG_SCSI_SCR 0x1b0 /* SCSI Partial-Word DMA Control */ -#define IO_REG_SCSI_SDR0 0x1c0 /* SCSI DMA Partial Word 0 */ -#define IO_REG_SCSI_SDR1 0x1d0 /* SCSI DMA Partial Word 1 */ -#define IO_REG_FCTR 0x1e0 /* Free-Running Counter */ -#define IO_REG_RES_31 0x1f0 /* unused */ - - -/* - * The upper 16 bits of the System Support Register are a part of the - * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC - * machines. The exception is the Maxine, which makes use of the - * FLOPPY and ISDN bits (otherwise unused) and has a different SCC - * wiring. - */ - /* all systems */ -#define IO_SSR_SCC0A_TX_DMA_EN (1<<31) /* SCC0A transmit DMA enable */ -#define IO_SSR_SCC0A_RX_DMA_EN (1<<30) /* SCC0A receive DMA enable */ -#define IO_SSR_RES_27 (1<<27) /* unused */ -#define IO_SSR_RES_26 (1<<26) /* unused */ -#define IO_SSR_RES_25 (1<<25) /* unused */ -#define IO_SSR_RES_24 (1<<24) /* unused */ -#define IO_SSR_RES_23 (1<<23) /* unused */ -#define IO_SSR_SCSI_DMA_DIR (1<<18) /* SCSI DMA direction */ -#define IO_SSR_SCSI_DMA_EN (1<<17) /* SCSI DMA enable */ -#define IO_SSR_LANCE_DMA_EN (1<<16) /* LANCE DMA enable */ - - /* except Maxine */ -#define IO_SSR_SCC1A_TX_DMA_EN (1<<29) /* SCC1A transmit DMA enable */ -#define IO_SSR_SCC1A_RX_DMA_EN (1<<28) /* SCC1A receive DMA enable */ -#define IO_SSR_RES_22 (1<<22) /* unused */ -#define IO_SSR_RES_21 (1<<21) /* unused */ -#define IO_SSR_RES_20 (1<<20) /* unused */ -#define IO_SSR_RES_19 (1<<19) /* unused */ - - /* Maxine */ -#define IO_SSR_AB_TX_DMA_EN (1<<29) /* ACCESS.bus xmit DMA enable */ -#define IO_SSR_AB_RX_DMA_EN (1<<28) /* ACCESS.bus recv DMA enable */ -#define IO_SSR_FLOPPY_DMA_DIR (1<<22) /* Floppy DMA direction */ -#define IO_SSR_FLOPPY_DMA_EN (1<<21) /* Floppy DMA enable */ -#define IO_SSR_ISDN_TX_DMA_EN (1<<20) /* ISDN transmit DMA enable */ -#define IO_SSR_ISDN_RX_DMA_EN (1<<19) /* ISDN receive DMA enable */ - -/* - * The lower 16 bits are system-specific. Bits 15,11:8 are common and - * defined here. The rest is defined in system-specific headers. - */ -#define KN0X_IO_SSR_DIAGDN (1<<15) /* diagnostic jumper */ -#define KN0X_IO_SSR_SCC_RST (1<<11) /* ~SCC0,1 (Z85C30) reset */ -#define KN0X_IO_SSR_RTC_RST (1<<10) /* ~RTC (DS1287) reset */ -#define KN0X_IO_SSR_ASC_RST (1<<9) /* ~ASC (NCR53C94) reset */ -#define KN0X_IO_SSR_LANCE_RST (1<<8) /* ~LANCE (Am7990) reset */ - -#endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */ diff --git a/include/asm-mips/dec/ioasic_ints.h b/include/asm-mips/dec/ioasic_ints.h deleted file mode 100644 index 9aaa9869615..00000000000 --- a/include/asm-mips/dec/ioasic_ints.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Definitions for the interrupt related bits in the I/O ASIC - * interrupt status register (and the interrupt mask register, of course) - * - * Created with Information from: - * - * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual" - * - * and the Mach Sources - * - * Copyright (C) 199x the Anonymous - * Copyright (C) 2002 Maciej W. Rozycki - */ - -#ifndef __ASM_DEC_IOASIC_INTS_H -#define __ASM_DEC_IOASIC_INTS_H - -/* - * The upper 16 bits are a part of the I/O ASIC's internal DMA engine - * and thus are common to all I/O ASIC machines. The exception is - * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise - * unused) and has a different SCC wiring. - */ - /* all systems */ -#define IO_INR_SCC0A_TXDMA 31 /* SCC0A transmit page end */ -#define IO_INR_SCC0A_TXERR 30 /* SCC0A transmit memory read error */ -#define IO_INR_SCC0A_RXDMA 29 /* SCC0A receive half page */ -#define IO_INR_SCC0A_RXERR 28 /* SCC0A receive overrun */ -#define IO_INR_ASC_DMA 19 /* ASC buffer pointer loaded */ -#define IO_INR_ASC_ERR 18 /* ASC page overrun */ -#define IO_INR_ASC_MERR 17 /* ASC memory read error */ -#define IO_INR_LANCE_MERR 16 /* LANCE memory read error */ - - /* except Maxine */ -#define IO_INR_SCC1A_TXDMA 27 /* SCC1A transmit page end */ -#define IO_INR_SCC1A_TXERR 26 /* SCC1A transmit memory read error */ -#define IO_INR_SCC1A_RXDMA 25 /* SCC1A receive half page */ -#define IO_INR_SCC1A_RXERR 24 /* SCC1A receive overrun */ -#define IO_INR_RES_23 23 /* unused */ -#define IO_INR_RES_22 22 /* unused */ -#define IO_INR_RES_21 21 /* unused */ -#define IO_INR_RES_20 20 /* unused */ - - /* Maxine */ -#define IO_INR_AB_TXDMA 27 /* ACCESS.bus transmit page end */ -#define IO_INR_AB_TXERR 26 /* ACCESS.bus xmit memory read error */ -#define IO_INR_AB_RXDMA 25 /* ACCESS.bus receive half page */ -#define IO_INR_AB_RXERR 24 /* ACCESS.bus receive overrun */ -#define IO_INR_FLOPPY_ERR 23 /* FDC error */ -#define IO_INR_ISDN_TXDMA 22 /* ISDN xmit buffer pointer loaded */ -#define IO_INR_ISDN_RXDMA 21 /* ISDN recv buffer pointer loaded */ -#define IO_INR_ISDN_ERR 20 /* ISDN memory read/overrun error */ - -#define IO_INR_DMA 16 /* first DMA IRQ */ - -/* - * The lower 16 bits are system-specific and thus defined in - * system-specific headers. - */ - - -#define IO_IRQ_BASE 8 /* first IRQ assigned to I/O ASIC */ -#define IO_IRQ_LINES 32 /* number of I/O ASIC interrupts */ - -#define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE) -#define IO_IRQ_MASK(n) (1 << (n)) -#define IO_IRQ_ALL 0x0000ffff -#define IO_IRQ_DMA 0xffff0000 - -#endif /* __ASM_DEC_IOASIC_INTS_H */ diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h deleted file mode 100644 index 28fa717ac42..00000000000 --- a/include/asm-mips/dec/kn01.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Hardware info about DECstation DS2100/3100 systems (otherwise known as - * pmin/pmax or KN01). - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions - * are by courtesy of Chris Fraser. - * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki - */ -#ifndef __ASM_MIPS_DEC_KN01_H -#define __ASM_MIPS_DEC_KN01_H - -#define KN01_SLOT_BASE 0x10000000 -#define KN01_SLOT_SIZE 0x01000000 - -/* - * Address ranges for devices. - */ -#define KN01_PMASK (0*KN01_SLOT_SIZE) /* color plane mask */ -#define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */ -#define KN01_VDAC (2*KN01_SLOT_SIZE) /* color map */ -#define KN01_RES_3 (3*KN01_SLOT_SIZE) /* unused */ -#define KN01_RES_4 (4*KN01_SLOT_SIZE) /* unused */ -#define KN01_RES_5 (5*KN01_SLOT_SIZE) /* unused */ -#define KN01_RES_6 (6*KN01_SLOT_SIZE) /* unused */ -#define KN01_ERRADDR (7*KN01_SLOT_SIZE) /* write error address */ -#define KN01_LANCE (8*KN01_SLOT_SIZE) /* LANCE (Am7990) Ethernet */ -#define KN01_LANCE_MEM (9*KN01_SLOT_SIZE) /* LANCE buffer memory */ -#define KN01_SII (10*KN01_SLOT_SIZE) /* SII (DC7061) SCSI */ -#define KN01_SII_MEM (11*KN01_SLOT_SIZE) /* SII buffer memory */ -#define KN01_DZ11 (12*KN01_SLOT_SIZE) /* DZ11 (DC7085) serial */ -#define KN01_RTC (13*KN01_SLOT_SIZE) /* DS1287 RTC (bytes #0) */ -#define KN01_ESAR (13*KN01_SLOT_SIZE) /* MAC address (bytes #1) */ -#define KN01_CSR (14*KN01_SLOT_SIZE) /* system ctrl & status reg */ -#define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */ - - -/* - * Frame buffer memory address. - */ -#define KN01_VFB_MEM 0x0fc00000 - -/* - * CPU interrupt bits. - */ -#define KN01_CPU_INR_BUS 6 /* memory, I/O bus read/write errors */ -#define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */ -#define KN01_CPU_INR_RTC 5 /* DS1287 RTC */ -#define KN01_CPU_INR_DZ11 4 /* DZ11 (DC7085) serial */ -#define KN01_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */ -#define KN01_CPU_INR_SII 2 /* SII (DC7061) SCSI */ - - -/* - * System Control & Status Register bits. - */ -#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */ -#define KN01_CSR_STATUS (1<<14) /* self-test result status output */ -#define KN01_CSR_PARDIS (1<<13) /* parity error disable */ -#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */ -#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */ -#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/ -#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */ -#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */ -#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */ -#define KN01_CSR_VRGTRG (1<<1) /* red DAC voltage over green (r/o) */ -#define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */ -#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ - - -#ifndef __ASSEMBLY__ - -#include <linux/interrupt.h> -#include <linux/spinlock.h> -#include <linux/types.h> - -struct pt_regs; - -extern u16 cached_kn01_csr; -extern spinlock_t kn01_lock; - -extern void dec_kn01_be_init(void); -extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup); -extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id); -#endif - -#endif /* __ASM_MIPS_DEC_KN01_H */ diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h deleted file mode 100644 index 93430b5f472..00000000000 --- a/include/asm-mips/dec/kn02.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Hardware info about DECstation 5000/200 systems (otherwise known as - * 3max or KN02). - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions - * are by courtesy of Chris Fraser. - * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki - */ -#ifndef __ASM_MIPS_DEC_KN02_H -#define __ASM_MIPS_DEC_KN02_H - -#define KN02_SLOT_BASE 0x1fc00000 -#define KN02_SLOT_SIZE 0x00080000 - -/* - * Address ranges decoded by the "system slot" logic for onboard devices. - */ -#define KN02_SYS_ROM (0*KN02_SLOT_SIZE) /* system board ROM */ -#define KN02_RES_1 (1*KN02_SLOT_SIZE) /* unused */ -#define KN02_CHKSYN (2*KN02_SLOT_SIZE) /* ECC syndrome */ -#define KN02_ERRADDR (3*KN02_SLOT_SIZE) /* bus error address */ -#define KN02_DZ11 (4*KN02_SLOT_SIZE) /* DZ11 (DC7085) serial */ -#define KN02_RTC (5*KN02_SLOT_SIZE) /* DS1287 RTC */ -#define KN02_CSR (6*KN02_SLOT_SIZE) /* system ctrl & status reg */ -#define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */ - - -/* - * System Control & Status Register bits. - */ -#define KN02_CSR_RES_28 (0xf<<28) /* unused */ -#define KN02_CSR_PSU (1<<27) /* power supply unit warning */ -#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */ -#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */ -#define KN02_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */ -#define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */ -#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */ -#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */ -#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */ -#define KN02_CSR_LEDIAG (1<<12) /* ECC diagn. latch strobe */ -#define KN02_CSR_TXDIS (1<<11) /* DZ11 transmit disable */ -#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */ -#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */ -#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */ -#define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */ -#define KN02_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ - - -/* - * CPU interrupt bits. - */ -#define KN02_CPU_INR_RES_6 6 /* unused */ -#define KN02_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */ -#define KN02_CPU_INR_RES_4 4 /* unused */ -#define KN02_CPU_INR_RTC 3 /* DS1287 RTC */ -#define KN02_CPU_INR_CASCADE 2 /* CSR cascade */ - -/* - * CSR interrupt bits. - */ -#define KN02_CSR_INR_DZ11 7 /* DZ11 (DC7085) serial */ -#define KN02_CSR_INR_LANCE 6 /* LANCE (Am7990) Ethernet */ -#define KN02_CSR_INR_ASC 5 /* ASC (NCR53C94) SCSI */ -#define KN02_CSR_INR_RES_4 4 /* unused */ -#define KN02_CSR_INR_RES_3 3 /* unused */ -#define KN02_CSR_INR_TC2 2 /* TURBOchannel slot #2 */ -#define KN02_CSR_INR_TC1 1 /* TURBOchannel slot #1 */ -#define KN02_CSR_INR_TC0 0 /* TURBOchannel slot #0 */ - - -#define KN02_IRQ_BASE 8 /* first IRQ assigned to CSR */ -#define KN02_IRQ_LINES 8 /* number of CSR interrupts */ - -#define KN02_IRQ_NR(n) ((n) + KN02_IRQ_BASE) -#define KN02_IRQ_MASK(n) (1 << (n)) -#define KN02_IRQ_ALL 0xff - - -#ifndef __ASSEMBLY__ - -#include <linux/types.h> - -extern u32 cached_kn02_csr; -extern void init_kn02_irqs(int base); -#endif - -#endif /* __ASM_MIPS_DEC_KN02_H */ diff --git a/include/asm-mips/dec/kn02ba.h b/include/asm-mips/dec/kn02ba.h deleted file mode 100644 index c957a4f1b32..00000000000 --- a/include/asm-mips/dec/kn02ba.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * include/asm-mips/dec/kn02ba.h - * - * DECstation 5000/1xx (3min or KN02-BA) definitions. - * - * Copyright (C) 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_KN02BA_H -#define __ASM_MIPS_DEC_KN02BA_H - -#include <asm/dec/kn02xa.h> /* For common definitions. */ - -/* - * CPU interrupt bits. - */ -#define KN02BA_CPU_INR_HALT 6 /* HALT button */ -#define KN02BA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */ -#define KN02BA_CPU_INR_TC2 4 /* TURBOchannel slot #2 */ -#define KN02BA_CPU_INR_TC1 3 /* TURBOchannel slot #1 */ -#define KN02BA_CPU_INR_TC0 2 /* TURBOchannel slot #0 */ - -/* - * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits. - */ -#define KN02BA_IO_INR_RES_15 15 /* unused */ -#define KN02BA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */ -#define KN02BA_IO_INR_RES_13 13 /* unused */ -#define KN02BA_IO_INR_BUS 12 /* memory, I/O bus read/write errors */ -#define KN02BA_IO_INR_RES_11 11 /* unused */ -#define KN02BA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */ -#define KN02BA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */ -#define KN02BA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */ -#define KN02BA_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */ -#define KN02BA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */ -#define KN02BA_IO_INR_RTC 5 /* DS1287 RTC */ -#define KN02BA_IO_INR_PSU 4 /* power supply unit warning */ -#define KN02BA_IO_INR_RES_3 3 /* unused */ -#define KN02BA_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */ -#define KN02BA_IO_INR_PBNC 1 /* ~HALT button debouncer */ -#define KN02BA_IO_INR_PBNO 0 /* HALT button debouncer */ - - -/* - * Memory Error Register bits. - */ -#define KN02BA_MER_RES_27 (1<<27) /* unused */ - -/* - * Memory Size Register bits. - */ -#define KN02BA_MSR_RES_17 (0x3ff<<17) /* unused */ - -/* - * I/O ASIC System Support Register bits. - */ -#define KN02BA_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */ -#define KN02BA_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */ -#define KN02BA_IO_SSR_RES_12 (1<<12) /* unused */ - -#define KN02BA_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */ - -#endif /* __ASM_MIPS_DEC_KN02BA_H */ diff --git a/include/asm-mips/dec/kn02ca.h b/include/asm-mips/dec/kn02ca.h deleted file mode 100644 index 92c0fe25609..00000000000 --- a/include/asm-mips/dec/kn02ca.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * include/asm-mips/dec/kn02ca.h - * - * Personal DECstation 5000/xx (Maxine or KN02-CA) definitions. - * - * Copyright (C) 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_KN02CA_H -#define __ASM_MIPS_DEC_KN02CA_H - -#include <asm/dec/kn02xa.h> /* For common definitions. */ - -/* - * CPU interrupt bits. - */ -#define KN02CA_CPU_INR_HALT 6 /* HALT from ACCESS.Bus */ -#define KN02CA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */ -#define KN02CA_CPU_INR_BUS 4 /* memory, I/O bus read/write errors */ -#define KN02CA_CPU_INR_RTC 3 /* DS1287 RTC */ -#define KN02CA_CPU_INR_TIMER 2 /* ARC periodic timer */ - -/* - * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits. - */ -#define KN02CA_IO_INR_FLOPPY 15 /* 82077 FDC */ -#define KN02CA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */ -#define KN02CA_IO_INR_POWERON 13 /* (*) ACCESS.Bus/power-on reset */ -#define KN02CA_IO_INR_TC0 12 /* TURBOchannel slot #0 */ -#define KN02CA_IO_INR_TIMER 12 /* ARC periodic timer (?) */ -#define KN02CA_IO_INR_ISDN 11 /* Am79C30A ISDN */ -#define KN02CA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */ -#define KN02CA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */ -#define KN02CA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */ -#define KN02CA_IO_INR_HDFLOPPY 7 /* (*) HD (1.44MB) floppy status */ -#define KN02CA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */ -#define KN02CA_IO_INR_TC1 5 /* TURBOchannel slot #1 */ -#define KN02CA_IO_INR_XDFLOPPY 4 /* (*) XD (2.88MB) floppy status */ -#define KN02CA_IO_INR_VIDEO 3 /* framebuffer */ -#define KN02CA_IO_INR_XVIDEO 2 /* ~framebuffer */ -#define KN02CA_IO_INR_AB_XMIT 1 /* ACCESS.bus transmit */ -#define KN02CA_IO_INR_AB_RECV 0 /* ACCESS.bus receive */ - - -/* - * Memory Error Register bits. - */ -#define KN02CA_MER_INTR (1<<27) /* ARC IRQ status & ack */ - -/* - * Memory Size Register bits. - */ -#define KN02CA_MSR_INTREN (1<<26) /* ARC periodic IRQ enable */ -#define KN02CA_MSR_MS10EN (1<<25) /* 10/1ms IRQ period select */ -#define KN02CA_MSR_PFORCE (0xf<<21) /* byte lane error force */ -#define KN02CA_MSR_MABEN (1<<20) /* A side VFB address enable */ -#define KN02CA_MSR_LASTBANK (0x7<<17) /* onboard RAM bank # */ - -/* - * I/O ASIC System Support Register bits. - */ -#define KN03CA_IO_SSR_RES_14 (1<<14) /* unused */ -#define KN03CA_IO_SSR_RES_13 (1<<13) /* unused */ -#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */ - -#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */ -#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */ -#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */ -#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */ -#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */ -#define KN03CA_IO_SSR_RES_2 (1<<2) /* unused */ -#define KN03CA_IO_SSR_RES_1 (1<<1) /* unused */ -#define KN03CA_IO_SSR_LED (1<<0) /* power LED */ - -#endif /* __ASM_MIPS_DEC_KN02CA_H */ diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h deleted file mode 100644 index b56b4577f6e..00000000000 --- a/include/asm-mips/dec/kn02xa.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Hardware info common to DECstation 5000/1xx systems (otherwise - * known as 3min or kn02ba) and Personal DECstations 5000/xx ones - * (otherwise known as maxine or kn02ca). - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions - * are by courtesy of Chris Fraser. - * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki - * - * These are addresses which have to be known early in the boot process. - * For other addresses refer to tc.h, ioasic_addrs.h and friends. - */ -#ifndef __ASM_MIPS_DEC_KN02XA_H -#define __ASM_MIPS_DEC_KN02XA_H - -#include <asm/dec/ioasic_addrs.h> - -#define KN02XA_SLOT_BASE 0x1c000000 - -/* - * Memory control ASIC registers. - */ -#define KN02XA_MER 0x0c400000 /* memory error register */ -#define KN02XA_MSR 0x0c800000 /* memory size register */ - -/* - * CPU control ASIC registers. - */ -#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */ -#define KN02XA_EAR 0x0e000004 /* error address register */ -#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */ -#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */ - -/* - * Memory Error Register bits, common definitions. - * The rest is defined in system-specific headers. - */ -#define KN02XA_MER_RES_28 (0xf<<28) /* unused */ -#define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */ -#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */ -#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */ -#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */ -#define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */ -#define KN02XA_MER_RES_12 (1<<12) /* unused */ -#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */ -#define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */ |