diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf548/defBF549.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/defBF549.h | 763 |
1 files changed, 13 insertions, 750 deletions
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h index b1cc1c073b4..c2f4734da48 100644 --- a/include/asm-blackfin/mach-bf548/defBF549.h +++ b/include/asm-blackfin/mach-bf548/defBF549.h @@ -1070,21 +1070,13 @@ /* Bit masks for PIXC_CTL */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 #define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 #define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 #define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 #define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 #define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 #define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 #define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 #define IMG_STAT 0x300 /* Image FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define WM_LVL 0x3000 /* FIFO Watermark Level */ @@ -1132,13 +1124,9 @@ /* Bit masks for PIXC_INTRSTAT */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 /* Bit masks for PIXC_RYCON */ @@ -1146,7 +1134,6 @@ #define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 /* Bit masks for PIXC_GUCON */ @@ -1154,7 +1141,6 @@ #define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 /* Bit masks for PIXC_BVCON */ @@ -1162,7 +1148,6 @@ #define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 /* Bit masks for PIXC_CCBIAS */ @@ -1179,48 +1164,28 @@ /* Bit masks for HOST_CONTROL */ #define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 #define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 #define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 #define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 #define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 #define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 #define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 #define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 #define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 #define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 #define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 -#define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 +#define DMA_COMPLETE 0x8 /* DMA Complete */ #define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 #define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 #define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 #define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 #define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 #define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 /* Bit masks for HOST_TIMEOUT */ @@ -1229,71 +1194,41 @@ /* Bit masks for MXVR_CONFIG */ #define MXVREN 0x1 /* MXVR Enable */ -#define nMXVREN 0x0 #define MMSM 0x2 /* MXVR Master/Slave Mode Select */ -#define nMMSM 0x0 #define ACTIVE 0x4 /* Active Mode */ -#define nACTIVE 0x0 #define SDELAY 0x8 /* Synchronous Data Delay */ -#define nSDELAY 0x0 #define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ -#define nNCMRXEN 0x0 #define RWRRXEN 0x20 /* Remote Write Receive Enable */ -#define nRWRRXEN 0x0 #define MTXEN 0x40 /* MXVR Transmit Data Enable */ -#define nMTXEN 0x0 #define MTXONB 0x80 /* MXVR Phy Transmitter On */ -#define nMTXONB 0x0 #define EPARITY 0x100 /* Even Parity Select */ -#define nEPARITY 0x0 #define MSB 0x1e00 /* Master Synchronous Boundary */ #define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ -#define nAPRXEN 0x0 #define WAKEUP 0x4000 /* Wake-Up */ -#define nWAKEUP 0x0 #define LMECH 0x8000 /* Lock Mechanism Select */ -#define nLMECH 0x0 /* Bit masks for MXVR_STATE_0 */ #define NACT 0x1 /* Network Activity */ -#define nNACT 0x0 #define SBLOCK 0x2 /* Super Block Lock */ -#define nSBLOCK 0x0 #define FMPLLST 0xc /* Frequency Multiply PLL SM State */ #define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ #define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ -#define nAPBSY 0x0 #define APARB 0x200 /* Asynchronous Packet Arbitrating */ -#define nAPARB 0x0 #define APTX 0x400 /* Asynchronous Packet Transmitting */ -#define nAPTX 0x0 #define APRX 0x800 /* Receiving Asynchronous Packet */ -#define nAPRX 0x0 #define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ -#define nCMBSY 0x0 #define CMARB 0x2000 /* Control Message Arbitrating */ -#define nCMARB 0x0 #define CMTX 0x4000 /* Control Message Transmitting */ -#define nCMTX 0x0 #define CMRX 0x8000 /* Receiving Control Message */ -#define nCMRX 0x0 #define MRXONB 0x10000 /* MRXONB Pin State */ -#define nMRXONB 0x0 #define RGSIP 0x20000 /* Remote Get Source In Progress */ -#define nRGSIP 0x0 #define DALIP 0x40000 /* Resource Deallocate In Progress */ -#define nDALIP 0x0 #define ALIP 0x80000 /* Resource Allocate In Progress */ -#define nALIP 0x0 #define RRDIP 0x100000 /* Remote Read In Progress */ -#define nRRDIP 0x0 #define RWRIP 0x200000 /* Remote Write In Progress */ -#define nRWRIP 0x0 #define FLOCK 0x400000 /* Frame Lock */ -#define nFLOCK 0x0 #define BLOCK 0x800000 /* Block Lock */ -#define nBLOCK 0x0 #define RSB 0xf000000 /* Received Synchronous Boundary */ #define DERRNUM 0xf0000000 /* DMA Error Channel Number */ @@ -1302,535 +1237,343 @@ #define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ #define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ #define APCONT 0x100 /* Asynchronous Packet Continuation */ -#define nAPCONT 0x0 #define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ #define DMAACTIVE0 0x10000 /* DMA0 Active */ -#define nDMAACTIVE0 0x0 #define DMAACTIVE1 0x20000 /* DMA1 Active */ -#define nDMAACTIVE1 0x0 #define DMAACTIVE2 0x40000 /* DMA2 Active */ -#define nDMAACTIVE2 0x0 #define DMAACTIVE3 0x80000 /* DMA3 Active */ -#define nDMAACTIVE3 0x0 #define DMAACTIVE4 0x100000 /* DMA4 Active */ -#define nDMAACTIVE4 0x0 #define DMAACTIVE5 0x200000 /* DMA5 Active */ -#define nDMAACTIVE5 0x0 #define DMAACTIVE6 0x400000 /* DMA6 Active */ -#define nDMAACTIVE6 0x0 #define DMAACTIVE7 0x800000 /* DMA7 Active */ -#define nDMAACTIVE7 0x0 #define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ -#define nDMAPMEN0 0x0 #define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ -#define nDMAPMEN1 0x0 #define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ -#define nDMAPMEN2 0x0 #define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ -#define nDMAPMEN3 0x0 #define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ -#define nDMAPMEN4 0x0 #define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ -#define nDMAPMEN5 0x0 #define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ -#define nDMAPMEN6 0x0 #define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ -#define nDMAPMEN7 0x0 /* Bit masks for MXVR_INT_STAT_0 */ #define NI2A 0x1 /* Network Inactive to Active */ -#define nNI2A 0x0 #define NA2I 0x2 /* Network Active to Inactive */ -#define nNA2I 0x0 #define SBU2L 0x4 /* Super Block Unlock to Lock */ -#define nSBU2L 0x0 #define SBL2U 0x8 /* Super Block Lock to Unlock */ -#define nSBL2U 0x0 #define PRU 0x10 /* Position Register Updated */ -#define nPRU 0x0 #define MPRU 0x20 /* Maximum Position Register Updated */ -#define nMPRU 0x0 #define DRU 0x40 /* Delay Register Updated */ -#define nDRU 0x0 #define MDRU 0x80 /* Maximum Delay Register Updated */ -#define nMDRU 0x0 #define SBU 0x100 /* Synchronous Boundary Updated */ -#define nSBU 0x0 #define ATU 0x200 /* Allocation Table Updated */ -#define nATU 0x0 #define FCZ0 0x400 /* Frame Counter 0 Zero */ -#define nFCZ0 0x0 #define FCZ1 0x800 /* Frame Counter 1 Zero */ -#define nFCZ1 0x0 #define PERR 0x1000 /* Parity Error */ -#define nPERR 0x0 #define MH2L 0x2000 /* MRXONB High to Low */ -#define nMH2L 0x0 #define ML2H 0x4000 /* MRXONB Low to High */ -#define nML2H 0x0 #define WUP 0x8000 /* Wake-Up Preamble Received */ -#define nWUP 0x0 #define FU2L 0x10000 /* Frame Unlock to Lock */ -#define nFU2L 0x0 #define FL2U 0x20000 /* Frame Lock to Unlock */ -#define nFL2U 0x0 #define BU2L 0x40000 /* Block Unlock to Lock */ -#define nBU2L 0x0 #define BL2U 0x80000 /* Block Lock to Unlock */ -#define nBL2U 0x0 #define OBERR 0x100000 /* DMA Out of Bounds Error */ -#define nOBERR 0x0 #define PFL 0x200000 /* PLL Frequency Locked */ -#define nPFL 0x0 #define SCZ 0x400000 /* System Clock Counter Zero */ -#define nSCZ 0x0 #define FERR 0x800000 /* FIFO Error */ -#define nFERR 0x0 #define CMR 0x1000000 /* Control Message Received */ -#define nCMR 0x0 #define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ -#define nCMROF 0x0 #define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ -#define nCMTS 0x0 #define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ -#define nCMTC 0x0 #define RWRC 0x10000000 /* Remote Write Control Message Completed */ -#define nRWRC 0x0 #define BCZ 0x20000000 /* Block Counter Zero */ -#define nBCZ 0x0 #define BMERR 0x40000000 /* Biphase Mark Coding Error */ -#define nBMERR 0x0 #define DERR 0x80000000 /* DMA Error */ -#define nDERR 0x0 /* Bit masks for MXVR_INT_STAT_1 */ #define HDONE0 0x1 /* DMA0 Half Done */ -#define nHDONE0 0x0 #define DONE0 0x2 /* DMA0 Done */ -#define nDONE0 0x0 #define APR 0x4 /* Asynchronous Packet Received */ -#define nAPR 0x0 #define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ -#define nAPROF 0x0 #define HDONE1 0x10 /* DMA1 Half Done */ -#define nHDONE1 0x0 #define DONE1 0x20 /* DMA1 Done */ -#define nDONE1 0x0 #define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ -#define nAPTS 0x0 #define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ -#define nAPTC 0x0 #define HDONE2 0x100 /* DMA2 Half Done */ -#define nHDONE2 0x0 #define DONE2 0x200 /* DMA2 Done */ -#define nDONE2 0x0 #define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ -#define nAPRCE 0x0 #define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ -#define nAPRPE 0x0 #define HDONE3 0x1000 /* DMA3 Half Done */ -#define nHDONE3 0x0 #define DONE3 0x2000 /* DMA3 Done */ -#define nDONE3 0x0 #define HDONE4 0x10000 /* DMA4 Half Done */ -#define nHDONE4 0x0 #define DONE4 0x20000 /* DMA4 Done */ -#define nDONE4 0x0 #define HDONE5 0x100000 /* DMA5 Half Done */ -#define nHDONE5 0x0 #define DONE5 0x200000 /* DMA5 Done */ -#define nDONE5 0x0 #define HDONE6 0x1000000 /* DMA6 Half Done */ -#define nHDONE6 0x0 #define DONE6 0x2000000 /* DMA6 Done */ -#define nDONE6 0x0 #define HDONE7 0x10000000 /* DMA7 Half Done */ -#define nHDONE7 0x0 #define DONE7 0x20000000 /* DMA7 Done */ -#define nDONE7 0x0 /* Bit masks for MXVR_INT_EN_0 */ #define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ -#define nNI2AEN 0x0 #define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ -#define nNA2IEN 0x0 #define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ -#define nSBU2LEN 0x0 #define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ -#define nSBL2UEN 0x0 #define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ -#define nPRUEN 0x0 #define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ -#define nMPRUEN 0x0 #define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ -#define nDRUEN 0x0 #define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ -#define nMDRUEN 0x0 #define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ -#define nSBUEN 0x0 #define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ -#define nATUEN 0x0 #define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ -#define nFCZ0EN 0x0 #define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ -#define nFCZ1EN 0x0 #define PERREN 0x1000 /* Parity Error Interrupt Enable */ -#define nPERREN 0x0 #define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ -#define nMH2LEN 0x0 #define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ -#define nML2HEN 0x0 #define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ -#define nWUPEN 0x0 #define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ -#define nFU2LEN 0x0 #define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ -#define nFL2UEN 0x0 #define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ -#define nBU2LEN 0x0 #define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ -#define nBL2UEN 0x0 #define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ -#define nOBERREN 0x0 #define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ -#define nPFLEN 0x0 #define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ -#define nSCZEN 0x0 #define FERREN 0x800000 /* FIFO Error Interrupt Enable */ -#define nFERREN 0x0 #define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ -#define nCMREN 0x0 #define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ -#define nCMROFEN 0x0 #define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ -#define nCMTSEN 0x0 #define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ -#define nCMTCEN 0x0 #define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ -#define nRWRCEN 0x0 #define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ -#define nBCZEN 0x0 #define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ -#define nBMERREN 0x0 #define DERREN 0x80000000 /* DMA Error Interrupt Enable */ -#define nDERREN 0x0 /* Bit masks for MXVR_INT_EN_1 */ #define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ -#define nHDONEEN0 0x0 #define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ -#define nDONEEN0 0x0 #define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ -#define nAPREN 0x0 #define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ -#define nAPROFEN 0x0 #define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ -#define nHDONEEN1 0x0 #define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ -#define nDONEEN1 0x0 #define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ -#define nAPTSEN 0x0 #define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ -#define nAPTCEN 0x0 #define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ -#define nHDONEEN2 0x0 #define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ -#define nDONEEN2 0x0 #define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ -#define nAPRCEEN 0x0 #define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ -#define nAPRPEEN 0x0 #define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ -#define nHDONEEN3 0x0 #define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ -#define nDONEEN3 0x0 #define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ -#define nHDONEEN4 0x0 #define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ -#define nDONEEN4 0x0 #define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ -#define nHDONEEN5 0x0 #define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ -#define nDONEEN5 0x0 #define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ -#define nHDONEEN6 0x0 #define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ -#define nDONEEN6 0x0 #define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ -#define nHDONEEN7 0x0 #define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ -#define nDONEEN7 0x0 /* Bit masks for MXVR_POSITION */ #define POSITION 0x3f /* Node Position */ #define PVALID 0x8000 /* Node Position Valid */ -#define nPVALID 0x0 /* Bit masks for MXVR_MAX_POSITION */ #define MPOSITION 0x3f /* Maximum Node Position */ #define MPVALID 0x8000 /* Maximum Node Position Valid */ -#define nMPVALID 0x0 /* Bit masks for MXVR_DELAY */ #define DELAY 0x3f /* Node Frame Delay */ #define DVALID 0x8000 /* Node Frame Delay Valid */ -#define nDVALID 0x0 /* Bit masks for MXVR_MAX_DELAY */ #define MDELAY 0x3f /* Maximum Node Frame Delay */ #define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ -#define nMDVALID 0x0 /* Bit masks for MXVR_LADDR */ #define LADDR 0xffff /* Logical Address */ #define LVALID 0x80000000 /* Logical Address Valid */ -#define nLVALID 0x0 /* Bit masks for MXVR_GADDR */ #define GADDRL 0xff /* Group Address Lower Byte */ #define GVALID 0x8000 /* Group Address Valid */ -#define nGVALID 0x0 /* Bit masks for MXVR_AADDR */ #define AADDR 0xffff /* Alternate Address */ #define AVALID 0x80000000 /* Alternate Address Valid */ -#define nAVALID 0x0 /* Bit masks for MXVR_ALLOC_0 */ #define CL0 0x7f /* Channel 0 Connection Label */ #define CIU0 0x80 /* Channel 0 In Use */ -#define nCIU0 0x0 #define CL1 0x7f00 /* Channel 0 Connection Label */ #define CIU1 0x8000 /* Channel 0 In Use */ -#define nCIU1 0x0 #define CL2 0x7f0000 /* Channel 0 Connection Label */ #define CIU2 0x800000 /* Channel 0 In Use */ -#define nCIU2 0x0 #define CL3 0x7f000000 /* Channel 0 Connection Label */ #define CIU3 0x80000000 /* Channel 0 In Use */ -#define nCIU3 0x0 /* Bit masks for MXVR_ALLOC_1 */ #define CL4 0x7f /* Channel 4 Connection Label */ #define CIU4 0x80 /* Channel 4 In Use */ -#define nCIU4 0x0 #define CL5 0x7f00 /* Channel 5 Connection Label */ #define CIU5 0x8000 /* Channel 5 In Use */ -#define nCIU5 0x0 #define CL6 0x7f0000 /* Channel 6 Connection Label */ #define CIU6 0x800000 /* Channel 6 In Use */ -#define nCIU6 0x0 #define CL7 0x7f000000 /* Channel 7 Connection Label */ #define CIU7 0x80000000 /* Channel 7 In Use */ -#define nCIU7 0x0 /* Bit masks for MXVR_ALLOC_2 */ #define CL8 0x7f /* Channel 8 Connection Label */ #define CIU8 0x80 /* Channel 8 In Use */ -#define nCIU8 0x0 #define CL9 0x7f00 /* Channel 9 Connection Label */ #define CIU9 0x8000 /* Channel 9 In Use */ -#define nCIU9 0x0 #define CL10 0x7f0000 /* Channel 10 Connection Label */ #define CIU10 0x800000 /* Channel 10 In Use */ -#define nCIU10 0x0 #define CL11 0x7f000000 /* Channel 11 Connection Label */ #define CIU11 0x80000000 /* Channel 11 In Use */ -#define nCIU11 0x0 /* Bit masks for MXVR_ALLOC_3 */ #define CL12 0x7f /* Channel 12 Connection Label */ #define CIU12 0x80 /* Channel 12 In Use */ -#define nCIU12 0x0 #define CL13 0x7f00 /* Channel 13 Connection Label */ #define CIU13 0x8000 /* Channel 13 In Use */ -#define nCIU13 0x0 #define CL14 0x7f0000 /* Channel 14 Connection Label */ #define CIU14 0x800000 /* Channel 14 In Use */ -#define nCIU14 0x0 #define CL15 0x7f000000 /* Channel 15 Connection Label */ #define CIU15 0x80000000 /* Channel 15 In Use */ -#define nCIU15 0x0 /* Bit masks for MXVR_ALLOC_4 */ #define CL16 0x7f /* Channel 16 Connection Label */ #define CIU16 0x80 /* Channel 16 In Use */ -#define nCIU16 0x0 #define CL17 0x7f00 /* Channel 17 Connection Label */ #define CIU17 0x8000 /* Channel 17 In Use */ -#define nCIU17 0x0 #define CL18 0x7f0000 /* Channel 18 Connection Label */ #define CIU18 0x800000 /* Channel 18 In Use */ -#define nCIU18 0x0 #define CL19 0x7f000000 /* Channel 19 Connection Label */ #define CIU19 0x80000000 /* Channel 19 In Use */ -#define nCIU19 0x0 /* Bit masks for MXVR_ALLOC_5 */ #define CL20 0x7f /* Channel 20 Connection Label */ #define CIU20 0x80 /* Channel 20 In Use */ -#define nCIU20 0x0 #define CL21 0x7f00 /* Channel 21 Connection Label */ #define CIU21 0x8000 /* Channel 21 In Use */ -#define nCIU21 0x0 #define CL22 0x7f0000 /* Channel 22 Connection Label */ #define CIU22 0x800000 /* Channel 22 In Use */ -#define nCIU22 0x0 #define CL23 0x7f000000 /* Channel 23 Connection Label */ #define CIU23 0x80000000 /* Channel 23 In Use */ -#define nCIU23 0x0 /* Bit masks for MXVR_ALLOC_6 */ #define CL24 0x7f /* Channel 24 Connection Label */ #define CIU24 0x80 /* Channel 24 In Use */ -#define nCIU24 0x0 #define CL25 0x7f00 /* Channel 25 Connection Label */ #define CIU25 0x8000 /* Channel 25 In Use */ -#define nCIU25 0x0 #define CL26 0x7f0000 /* Channel 26 Connection Label */ #define CIU26 0x800000 /* Channel 26 In Use */ -#define nCIU26 0x0 #define CL27 0x7f000000 /* Channel 27 Connection Label */ #define CIU27 0x80000000 /* Channel 27 In Use */ -#define nCIU27 0x0 /* Bit masks for MXVR_ALLOC_7 */ #define CL28 0x7f /* Channel 28 Connection Label */ #define CIU28 0x80 /* Channel 28 In Use */ -#define nCIU28 0x0 #define CL29 0x7f00 /* Channel 29 Connection Label */ #define CIU29 0x8000 /* Channel 29 In Use */ -#define nCIU29 0x0 #define CL30 0x7f0000 /* Channel 30 Connection Label */ #define CIU30 0x800000 /* Channel 30 In Use */ -#define nCIU30 0x0 #define CL31 0x7f000000 /* Channel 31 Connection Label */ #define CIU31 0x80000000 /* Channel 31 In Use */ -#define nCIU31 0x0 /* Bit masks for MXVR_ALLOC_8 */ #define CL32 0x7f /* Channel 32 Connection Label */ #define CIU32 0x80 /* Channel 32 In Use */ -#define nCIU32 0x0 #define CL33 0x7f00 /* Channel 33 Connection Label */ #define CIU33 0x8000 /* Channel 33 In Use */ -#define nCIU33 0x0 #define CL34 0x7f0000 /* Channel 34 Connection Label */ #define CIU34 0x800000 /* Channel 34 In Use */ -#define nCIU34 0x0 #define CL35 0x7f000000 /* Channel 35 Connection Label */ #define CIU35 0x80000000 /* Channel 35 In Use */ -#define nCIU35 0x0 /* Bit masks for MXVR_ALLOC_9 */ #define CL36 0x7f /* Channel 36 Connection Label */ #define CIU36 0x80 /* Channel 36 In Use */ -#define nCIU36 0x0 #define CL37 0x7f00 /* Channel 37 Connection Label */ #define CIU37 0x8000 /* Channel 37 In Use */ -#define nCIU37 0x0 #define CL38 0x7f0000 /* Channel 38 Connection Label */ #define CIU38 0x800000 /* Channel 38 In Use */ -#define nCIU38 0x0 #define CL39 0x7f000000 /* Channel 39 Connection Label */ #define CIU39 0x80000000 /* Channel 39 In Use */ -#define nCIU39 0x0 /* Bit masks for MXVR_ALLOC_10 */ #define CL40 0x7f /* Channel 40 Connection Label */ #define CIU40 0x80 /* Channel 40 In Use */ -#define nCIU40 0x0 #define CL41 0x7f00 /* Channel 41 Connection Label */ #define CIU41 0x8000 /* Channel 41 In Use */ -#define nCIU41 0x0 #define CL42 0x7f0000 /* Channel 42 Connection Label */ #define CIU42 0x800000 /* Channel 42 In Use */ -#define nCIU42 0x0 #define CL43 0x7f000000 /* Channel 43 Connection Label */ #define CIU43 0x80000000 /* Channel 43 In Use */ -#define nCIU43 0x0 /* Bit masks for MXVR_ALLOC_11 */ #define CL44 0x7f /* Channel 44 Connection Label */ #define CIU44 0x80 /* Channel 44 In Use */ -#define nCIU44 0x0 #define CL45 0x7f00 /* Channel 45 Connection Label */ #define CIU45 0x8000 /* Channel 45 In Use */ -#define nCIU45 0x0 #define CL46 0x7f0000 /* Channel 46 Connection Label */ #define CIU46 0x800000 /* Channel 46 In Use */ -#define nCIU46 0x0 #define CL47 0x7f000000 /* Channel 47 Connection Label */ #define CIU47 0x80000000 /* Channel 47 In Use */ -#define nCIU47 0x0 /* Bit masks for MXVR_ALLOC_12 */ #define CL48 0x7f /* Channel 48 Connection Label */ #define CIU48 0x80 /* Channel 48 In Use */ -#define nCIU48 0x0 #define CL49 0x7f00 /* Channel 49 Connection Label */ #define CIU49 0x8000 /* Channel 49 In Use */ -#define nCIU49 0x0 #define CL50 0x7f0000 /* Channel 50 Connection Label */ #define CIU50 0x800000 /* Channel 50 In Use */ -#define nCIU50 0x0 #define CL51 0x7f000000 /* Channel 51 Connection Label */ #define CIU51 0x80000000 /* Channel 51 In Use */ -#define nCIU51 0x0 /* Bit masks for MXVR_ALLOC_13 */ #define CL52 0x7f /* Channel 52 Connection Label */ #define CIU52 0x80 /* Channel 52 In Use */ -#define nCIU52 0x0 #define CL53 0x7f00 /* Channel 53 Connection Label */ #define CIU53 0x8000 /* Channel 53 In Use */ -#define nCIU53 0x0 #define CL54 0x7f0000 /* Channel 54 Connection Label */ #define CIU54 0x800000 /* Channel 54 In Use */ -#define nCIU54 0x0 #define CL55 0x7f000000 /* Channel 55 Connection Label */ #define CIU55 0x80000000 /* Channel 55 In Use */ -#define nCIU55 0x0 /* Bit masks for MXVR_ALLOC_14 */ #define CL56 0x7f /* Channel 56 Connection Label */ #define CIU56 0x80 /* Channel 56 In Use */ -#define nCIU56 0x0 #define CL57 0x7f00 /* Channel 57 Connection Label */ #define CIU57 0x8000 /* Channel 57 In Use */ -#define nCIU57 0x0 #define CL58 0x7f0000 /* Channel 58 Connection Label */ #define CIU58 0x800000 /* Channel 58 In Use */ -#define nCIU58 0x0 #define CL59 0x7f000000 /* Channel 59 Connection Label */ #define CIU59 0x80000000 /* Channel 59 In Use */ -#define nCIU59 0x0 /* MXVR_SYNC_LCHAN_0 Masks */ @@ -1926,19 +1669,13 @@ /* Bit masks for MXVR_DMAx_CONFIG */ #define MDMAEN 0x1 /* DMA Channel Enable */ -#define nMDMAEN 0x0 #define DD 0x2 /* DMA Channel Direction */ -#define nDD 0x0 #define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ -#define nBY4SWAPEN 0x0 #define LCHAN 0x3c0 /* DMA Channel Logical Channel */ #define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ -#define nBITSWAPEN 0x0 #define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ -#define nBY2SWAPEN 0x0 #define MFLOW 0x7000 /* DMA Channel Operation Flow */ #define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ -#define nFIXEDPM 0x0 #define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ #define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ #define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ @@ -1946,94 +1683,71 @@ /* Bit masks for MXVR_AP_CTL */ #define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ -#define nSTARTAP 0x0 #define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ -#define nCANCELAP 0x0 #define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ -#define nRESETAP 0x0 #define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ -#define nAPRBE0 0x0 #define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ -#define nAPRBE1 0x0 /* Bit masks for MXVR_APRB_START_ADDR */ -#define MXVR_APRB_START_ADDR 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ +#define M |