diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/dma/Kconfig | 24 | ||||
| -rw-r--r-- | drivers/dma/Makefile | 3 | ||||
| -rw-r--r-- | drivers/dma/amba-pl08x.c | 2167 | ||||
| -rw-r--r-- | drivers/dma/dmaengine.c | 4 | ||||
| -rw-r--r-- | drivers/dma/fsldma.c | 328 | ||||
| -rw-r--r-- | drivers/dma/imx-dma.c | 422 | ||||
| -rw-r--r-- | drivers/dma/imx-sdma.c | 1392 | ||||
| -rw-r--r-- | drivers/dma/intel_mid_dma.c | 476 | ||||
| -rw-r--r-- | drivers/dma/intel_mid_dma_regs.h | 53 | ||||
| -rw-r--r-- | drivers/dma/mv_xor.c | 2 | ||||
| -rw-r--r-- | drivers/dma/shdma.c | 3 | ||||
| -rw-r--r-- | drivers/dma/ste_dma40.c | 17 |
12 files changed, 4625 insertions, 266 deletions
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 9520cf02edc..ab28f609341 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -49,6 +49,14 @@ config INTEL_MID_DMAC config ASYNC_TX_DISABLE_CHANNEL_SWITCH bool +config AMBA_PL08X + bool "ARM PrimeCell PL080 or PL081 support" + depends on ARM_AMBA && EXPERIMENTAL + select DMA_ENGINE + help + Platform has a PL08x DMAC device + which can provide DMA engine support + config INTEL_IOATDMA tristate "Intel I/OAT DMA support" depends on PCI && X86 @@ -195,6 +203,22 @@ config PCH_DMA help Enable support for the Topcliff PCH DMA engine. +config IMX_SDMA + tristate "i.MX SDMA support" + depends on ARCH_MX25 || ARCH_MX3 || ARCH_MX5 + select DMA_ENGINE + help + Support the i.MX SDMA engine. This engine is integrated into + Freescale i.MX25/31/35/51 chips. + +config IMX_DMA + tristate "i.MX DMA support" + depends on ARCH_MX1 || ARCH_MX21 || MACH_MX27 + select DMA_ENGINE + help + Support the i.MX DMA engine. This engine is integrated into + Freescale i.MX1/21/27 chips. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 72bd70384d8..a8a84f4587f 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -21,7 +21,10 @@ obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o obj-$(CONFIG_SH_DMAE) += shdma.o obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/ +obj-$(CONFIG_IMX_SDMA) += imx-sdma.o +obj-$(CONFIG_IMX_DMA) += imx-dma.o obj-$(CONFIG_TIMB_DMA) += timb_dma.o obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o obj-$(CONFIG_PL330_DMA) += pl330.o obj-$(CONFIG_PCH_DMA) += pch_dma.o +obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c new file mode 100644 index 00000000000..b605cc9ac3a --- /dev/null +++ b/drivers/dma/amba-pl08x.c @@ -0,0 +1,2167 @@ +/* + * Copyright (c) 2006 ARM Ltd. + * Copyright (c) 2010 ST-Ericsson SA + * + * Author: Peter Pearse <peter.pearse@arm.com> + * Author: Linus Walleij <linus.walleij@stericsson.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * The full GNU General Public License is iin this distribution in the + * file called COPYING. + * + * Documentation: ARM DDI 0196G == PL080 + * Documentation: ARM DDI 0218E == PL081 + * + * PL080 & PL081 both have 16 sets of DMA signals that can be routed to + * any channel. + * + * The PL080 has 8 channels available for simultaneous use, and the PL081 + * has only two channels. So on these DMA controllers the number of channels + * and the number of incoming DMA signals are two totally different things. + * It is usually not possible to theoretically handle all physical signals, + * so a multiplexing scheme with possible denial of use is necessary. + * + * The PL080 has a dual bus master, PL081 has a single master. + * + * Memory to peripheral transfer may be visualized as + * Get data from memory to DMAC + * Until no data left + * On burst request from peripheral + * Destination burst from DMAC to peripheral + * Clear burst request + * Raise terminal count interrupt + * + * For peripherals with a FIFO: + * Source burst size == half the depth of the peripheral FIFO + * Destination burst size == the depth of the peripheral FIFO + * + * (Bursts are irrelevant for mem to mem transfers - there are no burst + * signals, the DMA controller will simply facilitate its AHB master.) + * + * ASSUMES default (little) endianness for DMA transfers + * + * Only DMAC flow control is implemented + * + * Global TODO: + * - Break out common code from arch/arm/mach-s3c64xx and share + */ +#include <linux/device.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/interrupt.h> +#include <linux/slab.h> +#include <linux/dmapool.h> +#include <linux/amba/bus.h> +#include <linux/dmaengine.h> +#include <linux/amba/pl08x.h> +#include <linux/debugfs.h> +#include <linux/seq_file.h> + +#include <asm/hardware/pl080.h> +#include <asm/dma.h> +#include <asm/mach/dma.h> +#include <asm/atomic.h> +#include <asm/processor.h> +#include <asm/cacheflush.h> + +#define DRIVER_NAME "pl08xdmac" + +/** + * struct vendor_data - vendor-specific config parameters + * for PL08x derivates + * @name: the name of this specific variant + * @channels: the number of channels available in this variant + * @dualmaster: whether this version supports dual AHB masters + * or not. + */ +struct vendor_data { + char *name; + u8 channels; + bool dualmaster; +}; + +/* + * PL08X private data structures + * An LLI struct - see pl08x TRM + * Note that next uses bit[0] as a bus bit, + * start & end do not - their bus bit info + * is in cctl + */ +struct lli { + dma_addr_t src; + dma_addr_t dst; + dma_addr_t next; + u32 cctl; +}; + +/** + * struct pl08x_driver_data - the local state holder for the PL08x + * @slave: slave engine for this instance + * @memcpy: memcpy engine for this instance + * @base: virtual memory base (remapped) for the PL08x + * @adev: the corresponding AMBA (PrimeCell) bus entry + * @vd: vendor data for this PL08x variant + * @pd: platform data passed in from the platform/machine + * @phy_chans: array of data for the physical channels + * @pool: a pool for the LLI descriptors + * @pool_ctr: counter of LLIs in the pool + * @lock: a spinlock for this struct + */ +struct pl08x_driver_data { + struct dma_device slave; + struct dma_device memcpy; + void __iomem *base; + struct amba_device *adev; + struct vendor_data *vd; + struct pl08x_platform_data *pd; + struct pl08x_phy_chan *phy_chans; + struct dma_pool *pool; + int pool_ctr; + spinlock_t lock; +}; + +/* + * PL08X specific defines + */ + +/* + * Memory boundaries: the manual for PL08x says that the controller + * cannot read past a 1KiB boundary, so these defines are used to + * create transfer LLIs that do not cross such boundaries. + */ +#define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */ +#define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT) + +/* Minimum period between work queue runs */ +#define PL08X_WQ_PERIODMIN 20 + +/* Size (bytes) of each LLI buffer allocated for one transfer */ +# define PL08X_LLI_TSFR_SIZE 0x2000 + +/* Maximimum times we call dma_pool_alloc on this pool without freeing */ +#define PL08X_MAX_ALLOCS 0x40 +#define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct lli)) +#define PL08X_ALIGN 8 + +static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) +{ + return container_of(chan, struct pl08x_dma_chan, chan); +} + +/* + * Physical channel handling + */ + +/* Whether a certain channel is busy or not */ +static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) +{ + unsigned int val; + + val = readl(ch->base + PL080_CH_CONFIG); + return val & PL080_CONFIG_ACTIVE; +} + +/* + * Set the initial DMA register values i.e. those for the first LLI + * The next lli pointer and the configuration interrupt bit have + * been set when the LLIs were constructed + */ +static void pl08x_set_cregs(struct pl08x_driver_data *pl08x, + struct pl08x_phy_chan *ch) +{ + /* Wait for channel inactive */ + while (pl08x_phy_channel_busy(ch)) + ; + + dev_vdbg(&pl08x->adev->dev, + "WRITE channel %d: csrc=%08x, cdst=%08x, " + "cctl=%08x, clli=%08x, ccfg=%08x\n", + ch->id, + ch->csrc, + ch->cdst, + ch->cctl, + ch->clli, + ch->ccfg); + + writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR); + writel(ch->cdst, ch->base + PL080_CH_DST_ADDR); + writel(ch->clli, ch->base + PL080_CH_LLI); + writel(ch->cctl, ch->base + PL080_CH_CONTROL); + writel(ch->ccfg, ch->base + PL080_CH_CONFIG); +} + +static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan) +{ + struct pl08x_channel_data *cd = plchan->cd; + struct pl08x_phy_chan *phychan = plchan->phychan; + struct pl08x_txd *txd = plchan->at; + + /* Copy the basic control register calculated at transfer config */ + phychan->csrc = txd->csrc; + phychan->cdst = txd->cdst; + phychan->clli = txd->clli; + phychan->cctl = txd->cctl; + + /* Assign the signal to the proper control registers */ + phychan->ccfg = cd->ccfg; + phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK; + phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK; + /* If it wasn't set from AMBA, ignore it */ + if (txd->direction == DMA_TO_DEVICE) + /* Select signal as destination */ + phychan->ccfg |= + (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT); + else if (txd->direction == DMA_FROM_DEVICE) + /* Select signal as source */ + phychan->ccfg |= + (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT); + /* Always enable error interrupts */ + phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK; + /* Always enable terminal interrupts */ + phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK; +} + +/* + * Enable the DMA channel + * Assumes all other configuration bits have been set + * as desired before this code is called + */ +static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x, + struct pl08x_phy_chan *ch) +{ + u32 val; + + /* + * Do not access config register until channel shows as disabled + */ + while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id)) + ; + + /* + * Do not access config register until channel shows as inactive + */ + val = readl(ch->base + PL080_CH_CONFIG); + while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) + val = readl(ch->base + PL080_CH_CONFIG); + + writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG); +} + +/* + * Overall DMAC remains enabled always. + * + * Disabling individual channels could lose data. + * + * Disable the peripheral DMA after disabling the DMAC + * in order to allow the DMAC FIFO to drain, and + * hence allow the channel to show inactive + * + */ +static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) +{ + u32 val; + + /* Set the HALT bit and wait for the FIFO to drain */ + val = readl(ch->base + PL080_CH_CONFIG); + val |= PL080_CONFIG_HALT; + writel(val, ch->base + PL080_CH_CONFIG); + + /* Wait for channel inactive */ + while (pl08x_phy_channel_busy(ch)) + ; +} + +static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) +{ + u32 val; + + /* Clear the HALT bit */ + val = readl(ch->base + PL080_CH_CONFIG); + val &= ~PL080_CONFIG_HALT; + writel(val, ch->base + PL080_CH_CONFIG); +} + + +/* Stops the channel */ +static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch) +{ + u32 val; + + pl08x_pause_phy_chan(ch); + + /* Disable channel */ + val = readl(ch->base + PL080_CH_CONFIG); + val &= ~PL080_CONFIG_ENABLE; + val &= ~PL080_CONFIG_ERR_IRQ_MASK; + val &= ~PL080_CONFIG_TC_IRQ_MASK; + writel(val, ch->base + PL080_CH_CONFIG); +} + +static inline u32 get_bytes_in_cctl(u32 cctl) +{ + /* The source width defines the number of bytes */ + u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; + + switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { + case PL080_WIDTH_8BIT: + break; + case PL080_WIDTH_16BIT: + bytes *= 2; + break; + case PL080_WIDTH_32BIT: + bytes *= 4; + break; + } + return bytes; +} + +/* The channel should be paused when calling this */ +static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) +{ + struct pl08x_phy_chan *ch; + struct pl08x_txd *txdi = NULL; + struct pl08x_txd *txd; + unsigned long flags; + u32 bytes = 0; + + spin_lock_irqsave(&plchan->lock, flags); + + ch = plchan->phychan; + txd = plchan->at; + + /* + * Next follow the LLIs to get the number of pending bytes in the + * currently active transaction. + */ + if (ch && txd) { + struct lli *llis_va = txd->llis_va; + struct lli *llis_bus = (struct lli *) txd->llis_bus; + u32 clli = readl(ch->base + PL080_CH_LLI); + + /* First get the bytes in the current active LLI */ + bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); + + if (clli) { + int i = 0; + + /* Forward to the LLI pointed to by clli */ + while ((clli != (u32) &(llis_bus[i])) && + (i < MAX_NUM_TSFR_LLIS)) + i++; + + while (clli) { + bytes += get_bytes_in_cctl(llis_va[i].cctl); + /* + * A clli of 0x00000000 will terminate the + * LLI list + */ + clli = llis_va[i].next; + i++; + } + } + } + + /* Sum up all queued transactions */ + if (!list_empty(&plchan->desc_list)) { + list_for_each_entry(txdi, &plchan->desc_list, node) { + bytes += txdi->len; + } + + } + + spin_unlock_irqrestore(&plchan->lock, flags); + + return bytes; +} + +/* + * Allocate a physical channel for a virtual channel + */ +static struct pl08x_phy_chan * +pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, + struct pl08x_dma_chan *virt_chan) +{ + struct pl08x_phy_chan *ch = NULL; + unsigned long flags; + int i; + + /* + * Try to locate a physical channel to be used for + * this transfer. If all are taken return NULL and + * the requester will have to cope by using some fallback + * PIO mode or retrying later. + */ + for (i = 0; i < pl08x->vd->channels; i++) { + ch = &pl08x->phy_chans[i]; + + spin_lock_irqsave(&ch->lock, flags); + + if (!ch->serving) { + ch->serving = virt_chan; + ch->signal = -1; + spin_unlock_irqrestore(&ch->lock, flags); + break; + } + + spin_unlock_irqrestore(&ch->lock, flags); + } + + if (i == pl08x->vd->channels) { + /* No physical channel available, cope with it */ + return NULL; + } + + return ch; +} + +static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, + struct pl08x_phy_chan *ch) +{ + unsigned long flags; + + /* Stop the channel and clear its interrupts */ + pl08x_stop_phy_chan(ch); + writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR); + writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR); + + /* Mark it as free */ + spin_lock_irqsave(&ch->lock, flags); + ch->serving = NULL; + spin_unlock_irqrestore(&ch->lock, flags); +} + +/* + * LLI handling + */ + +static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) +{ + switch (coded) { + case PL080_WIDTH_8BIT: + return 1; + case PL080_WIDTH_16BIT: + return 2; + case PL080_WIDTH_32BIT: + return 4; + default: + break; + } + BUG(); + return 0; +} + +static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, + u32 tsize) +{ + u32 retbits = cctl; + + /* Remove all src, dst and transfersize bits */ + retbits &= ~PL080_CONTROL_DWIDTH_MASK; + retbits &= ~PL080_CONTROL_SWIDTH_MASK; + retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; + + /* Then set the bits according to the parameters */ + switch (srcwidth) { + case 1: + retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; + break; + case 2: + retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; + break; + case 4: + retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; + break; + default: + BUG(); + break; + } + + switch (dstwidth) { + case 1: + retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; + break; + case 2: + retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; + break; + case 4: + retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; + break; + default: + BUG(); + break; + } + + retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; + return retbits; +} + +/* + * Autoselect a master bus to use for the transfer + * this prefers the destination bus if both available + * if fixed address on one bus the other will be chosen + */ +void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus, + struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus, + struct pl08x_bus_data **sbus, u32 cctl) +{ + if (!(cctl & PL080_CONTROL_DST_INCR)) { + *mbus = src_bus; + *sbus = dst_bus; + } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { + *mbus = dst_bus; + *sbus = src_bus; + } else { + if (dst_bus->buswidth == 4) { + *mbus = dst_bus; + *sbus = src_bus; + } else if (src_bus->buswidth == 4) { + *mbus = src_bus; + *sbus = dst_bus; + } else if (dst_bus->buswidth == 2) { + *mbus = dst_bus; + *sbus = src_bus; + } else if (src_bus->buswidth == 2) { + *mbus = src_bus; + *sbus = dst_bus; + } else { + /* src_bus->buswidth == 1 */ + *mbus = dst_bus; + *sbus = src_bus; + } + } +} + +/* + * Fills in one LLI for a certain transfer descriptor + * and advance the counter + */ +int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x, + struct pl08x_txd *txd, int num_llis, int len, + u32 cctl, u32 *remainder) +{ + struct lli *llis_va = txd->llis_va; + struct lli *llis_bus = (struct lli *) txd->llis_bus; + + BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); + + llis_va[num_llis].cctl = cctl; + llis_va[num_llis].src = txd->srcbus.addr; + llis_va[num_llis].dst = txd->dstbus.addr; + + /* + * On versions with dual masters, you can optionally AND on + * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read + * in new LLIs with that controller, but we always try to + * choose AHB1 to point into memory. The idea is to have AHB2 + * fixed on the peripheral and AHB1 messing around in the + * memory. So we don't manipulate this bit currently. + */ + + llis_va[num_llis].next = + (dma_addr_t)((u32) &(llis_bus[num_llis + 1])); + + if (cctl & PL080_CONTROL_SRC_INCR) + txd->srcbus.addr += len; + if (cctl & PL080_CONTROL_DST_INCR) + txd->dstbus.addr += len; + + *remainder -= len; + + return num_llis + 1; +} + +/* + * Return number of bytes to fill to boundary, or len + */ +static inline u32 pl08x_pre_boundary(u32 addr, u32 len) +{ + u32 boundary; + + boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1) + << PL08X_BOUNDARY_SHIFT; + + if (boundary < addr + len) + return boundary - addr; + else + return len; +} + +/* + * This fills in the table of LLIs for the transfer descriptor + * Note that we assume we never have to change the burst sizes + * Return 0 for error + */ +static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, + struct pl08x_txd *txd) +{ + struct pl08x_channel_data *cd = txd->cd; + struct pl08x_bus_data *mbus, *sbus; + u32 remainder; + int num_llis = 0; + u32 cctl; + int max_bytes_per_lli; + int total_bytes = 0; + struct lli *llis_va; + struct lli *llis_bus; + + if (!txd) { + dev_err(&pl08x->adev->dev, "%s no descriptor\n", __func__); + return 0; + } + + txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, + &txd->llis_bus); + if (!txd->llis_va) { + dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); + return 0; + } + + pl08x->pool_ctr++; + + /* + * Initialize bus values for this transfer + * from the passed optimal values + */ + if (!cd) { + dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__); + return 0; + } + + /* Get the default CCTL from the platform data */ + cctl = cd->cctl; + + /* + * On the PL080 we have two bus masters and we + * should select one for source and one for + * destination. We try to use AHB2 for the + * bus which does not increment (typically the + * peripheral) else we just choose something. + */ + cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); + if (pl08x->vd->dualmaster) { + if (cctl & PL080_CONTROL_SRC_INCR) + /* Source increments, use AHB2 for destination */ + cctl |= PL080_CONTROL_DST_AHB2; + else if (cctl & PL080_CONTROL_DST_INCR) + /* Destination increments, use AHB2 for source */ + cctl |= PL080_CONTROL_SRC_AHB2; + else + /* Just pick something, source AHB1 dest AHB2 */ + cctl |= PL080_CONTROL_DST_AHB2; + } + + /* Find maximum width of the source bus */ + txd->srcbus.maxwidth = + pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> + PL080_CONTROL_SWIDTH_SHIFT); + + /* Find maximum width of the destination bus */ + txd->dstbus.maxwidth = + pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> + PL080_CONTROL_DWIDTH_SHIFT); + + /* Set up the bus widths to the maximum */ + txd->srcbus.buswidth = txd->srcbus.maxwidth; + txd->dstbus.buswidth = txd->dstbus.maxwidth; + dev_vdbg(&pl08x->adev->dev, + "%s source bus is %d bytes wide, dest bus is %d bytes wide\n", + __func__, txd->srcbus.buswidth, txd->dstbus.buswidth); + + + /* + * Bytes transferred == tsize * MIN(buswidths), not max(buswidths) + */ + max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) * + PL080_CONTROL_TRANSFER_SIZE_MASK; + dev_vdbg(&pl08x->adev->dev, + "%s max bytes per lli = %d\n", + __func__, max_bytes_per_lli); + + /* We need to count this down to zero */ + remainder = txd->len; + dev_vdbg(&pl08x->adev->dev, + "%s remainder = %d\n", + __func__, remainder); + + /* + * Choose bus to align to + * - prefers destination bus if both available + * - if fixed address on one bus chooses other + * - modifies cctl to choose an apropriate master + */ + pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus, + &mbus, &sbus, cctl); + + + /* + * The lowest bit of the LLI register + * is also used to indicate which master to + * use for reading the LLIs. + */ + + if (txd->len < mbus->buswidth) { + /* + * Less than a bus width available + * - send as single bytes + */ + while (remainder) { + dev_vdbg(&pl08x->adev->dev, + "%s single byte LLIs for a transfer of " + "less than a bus width (remain %08x)\n", + __func__, remainder); + cctl = pl08x_cctl_bits(cctl, 1, 1, 1); + num_llis = + pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1, + cctl, &remainder); + total_bytes++; + } + } else { + /* + * Make one byte LLIs until master bus is aligned + * - slave will then be aligned also + */ + while ((mbus->addr) % (mbus->buswidth)) { + dev_vdbg(&pl08x->adev->dev, + "%s adjustment lli for less than bus width " + "(remain %08x)\n", + __func__, remainder); + cctl = pl08x_cctl_bits(cctl, 1, 1, 1); + num_llis = pl08x_fill_lli_for_desc + (pl08x, txd, num_llis, 1, cctl, &remainder); + total_bytes++; + } + + /* + * Master now aligned + * - if slave is not then we must set its width down + */ + if (sbus->addr % sbus->buswidth) { + dev_dbg(&pl08x->adev->dev, + "%s set down bus width to one byte\n", + __func__); + + sbus->buswidth = 1; + } + + /* + * Make largest possible LLIs until less than one bus + * width left + */ + while (remainder > (mbus->buswidth - 1)) { + int lli_len, target_len; + int tsize; + int odd_bytes; + + /* + * If enough left try to send max possible, + * otherwise try to send the remainder + */ + target_len = remainder; + if (remainder > max_bytes_per_lli) + target_len = max_bytes_per_lli; + + /* + * Set bus lengths for incrementing busses + * to number of bytes which fill to next memory + * boundary + */ + if (cctl & PL080_CONTROL_SRC_INCR) + txd->srcbus.fill_bytes = + pl08x_pre_boundary( + txd->srcbus.addr, + remainder); + else + txd->srcbus.fill_bytes = + max_bytes_per_lli; + + if (cctl & PL080_CONTROL_DST_INCR) + txd->dstbus.fill_bytes = + pl08x_pre_boundary( + txd->dstbus.addr, + remainder); + else + txd->dstbus.fill_bytes = + max_bytes_per_lli; + + /* + * Find the nearest + */ + lli_len = min(txd->srcbus.fill_bytes, + txd->dstbus.fill_bytes); + + BUG_ON(lli_len > remainder); + + if (lli_len <= 0) { + dev_err(&pl08x->adev->dev, + "%s lli_len is %d, <= 0\n", + __func__, lli_len); + return 0; + } + + if (lli_len == target_len) { + /* + * Can send what we wanted + */ + /* + * Maintain alignment + */ + lli_len = (lli_len/mbus->buswidth) * + mbus->buswidth; + odd_bytes = 0; + } else { + /* + * So now we know how many bytes to transfer + * to get to the nearest boundary + * The next lli will past the boundary + * - however we may be working to a boundary + * on the slave bus + * We need to ensure the master stays aligned + */ + odd_bytes = lli_len % mbus->buswidth; + /* + * - and that we are working in multiples + * of the bus widths + */ + lli_len -= odd_bytes; + + } + + if (lli_len) { + /* + * Check against minimum bus alignment: + * Calculate actual transfer size in relation + * to bus width an get a maximum remainder of + * the smallest bus width - 1 + */ + /* FIXME: use round_down()? */ + tsize = lli_len / min(mbus->buswidth, + sbus->buswidth); + lli_len = tsize * min(mbus->buswidth, + sbus->buswidth); + + if (target_len != lli_len) { + dev_vdbg(&pl08x->adev->dev, + "%s can't send what we want. Desired %08x, lli of %08x bytes in txd of %08x\n", + __func__, target_len, lli_len, txd->len); + } + + cctl = pl08x_cctl_bits(cctl, + txd->srcbus.buswidth, + txd->dstbus.buswidth, + tsize); + + dev_vdbg(&pl08x->adev->dev, + "%s fill lli with single lli chunk of size %08x (remainder %08x)\n", + __func__, lli_len, remainder); + num_llis = pl08x_fill_lli_for_desc(pl08x, txd, + num_llis, lli_len, cctl, + &remainder); + total_bytes += lli_len; + } + + + if (odd_bytes) { + /* + * Creep past the boundary, + * maintaining master alignment + */ + int j; + for (j = 0; (j < mbus->buswidth) + && (remainder); j++) { + cctl = pl08x_cctl_bits(cctl, 1, 1, 1); + dev_vdbg(&pl08x->adev->dev, + "%s align with boundardy, single byte (remain %08x)\n", + __func__, remainder); + num_llis = + pl08x_fill_lli_for_desc(pl08x, + txd, num_llis, 1, + cctl, &remainder); + total_bytes++; + } + } + } + + /* + * Send any odd bytes + */ + if (remainder < 0) { + dev_err(&pl08x->adev->dev, "%s remainder not fitted 0x%08x bytes\n", + __func__, remainder); + return 0; + } + + while (remainder) { + cctl = pl08x_cctl_bits(cctl, 1, 1, 1); + dev_vdbg(&pl08x->adev->dev, + "%s align with boundardy, single odd byte (remain %d)\n", + __func__, remainder); + num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis, + 1, cctl, &remainder); + total_bytes++; + } + } + if (total_bytes != txd->len) { + dev_err(&pl08x->adev->dev, + "%s size of encoded lli:s don't match total txd, transferred 0x%08x from size 0x%08x\n", + __func__, total_bytes, txd->len); + return 0; + } + + if (num_llis >= MAX_NUM_TSFR_LLIS) { + dev_err(&pl08x->adev->dev, + "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", + __func__, (u32) MAX_NUM_TSFR_LLIS); + return 0; + } + /* + * Decide whether this is a loop or a terminated transfer + */ + llis_va = txd->llis_va; + llis_bus = (struct lli *) txd->llis_bus; + + if (cd->circular_buffer) { + /* + * Loop the circular buffer so that the next element + * points back to the beginning of the LLI. + */ + llis_va[num_llis - 1].next = + (dma_addr_t)((unsigned int)&(llis_bus[0])); + } else { + /* + * On non-circular buffers, the final LLI terminates + * the LLI. + */ + llis_va[num_llis - 1].next = 0; + /* + * The final LLI element shall also fire an interrupt + */ + llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN; + } + + /* Now store the channel register values */ + txd->csrc = llis_va[0].src; + txd->cdst = llis_va[0].dst; + if (num_llis > 1) + txd->clli = llis_va[0].next; + else + txd->clli = 0; + + txd->cctl = llis_va[0].cctl; + /* ccfg will be set at physical channel allocation time */ + +#ifdef VERBOSE_DEBUG + { + int i; + + for (i = 0; i < num_llis; i++) { + dev_vdbg(&pl08x->adev->dev, + "lli %d @%p: csrc=%08x, cdst=%08x, cctl=%08x, clli=%08x\n", + i, + &llis_va[i], + llis_va[i].src, + llis_va[i].dst, + llis_va[i].cctl, + llis_va[i].next + ); + } + } +#endif + + return num_llis; +} + +/* You should call this with the struct pl08x lock held */ +static void pl08x_free_txd(struct pl08x_driver_data *pl08x, + struct pl08x_txd *txd) +{ + if (!txd) + dev_err(&pl08x->adev->dev, + "%s no descriptor to free\n", + __func__); + + /* Free the LLI */ + dma_pool_free(pl08x->pool, txd->llis_va, + txd->llis_bus); + + pl08x->pool_ctr--; + + kfree(txd); +} + +static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, + struct pl08x_dma_chan *plchan) +{ + struct pl08x_txd *txdi = NULL; + struct pl08x_txd *next; + + if (!list_empty(&plchan->desc_list)) { + list_for_each_entry_safe(txdi, + next, &plchan->desc_list, node) { + list_del(&txdi->node); + pl08x_free_txd(pl08x, txdi); + } + + } +} + +/* + * The DMA ENGINE API + */ +static int pl08x_alloc_chan_resources(struct dma_chan *chan) +{ + return 0; +} + +static void pl08x_free_chan_resources(struct dma_chan *chan) +{ +} + +/* + * This should be called with the channel plchan->lock held + */ +static int prep_phy_channel(struct pl08x_dma_chan *plchan, + struct pl08x_txd *txd) +{ + struct pl08x_driver_data *pl08x = plchan->host; + struct pl08x_phy_chan *ch; + int ret; + + /* Check if we already have a channel */ + if (plchan->phychan) + return 0; + + ch = pl08x_get_phy_channel(pl08x, plchan); + if (!ch) { + /* No physical channel available, cope with it */ + dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); + return -EBUSY; + } + + /* + * OK we have a physical channel: for memcpy() this is all we + * need, but for slaves the physical signals may be muxed! + * Can the platform allow us to use this channel? + */ |