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-rw-r--r--drivers/scsi/Kconfig1
-rw-r--r--drivers/scsi/Makefile1
-rw-r--r--drivers/scsi/qla4xxx/Kconfig7
-rw-r--r--drivers/scsi/qla4xxx/Makefile5
-rw-r--r--drivers/scsi/qla4xxx/ql4_dbg.c197
-rw-r--r--drivers/scsi/qla4xxx/ql4_dbg.h55
-rw-r--r--drivers/scsi/qla4xxx/ql4_def.h586
-rw-r--r--drivers/scsi/qla4xxx/ql4_fw.h843
-rw-r--r--drivers/scsi/qla4xxx/ql4_glbl.h78
-rw-r--r--drivers/scsi/qla4xxx/ql4_init.c1340
-rw-r--r--drivers/scsi/qla4xxx/ql4_inline.h84
-rw-r--r--drivers/scsi/qla4xxx/ql4_iocb.c368
-rw-r--r--drivers/scsi/qla4xxx/ql4_isr.c797
-rw-r--r--drivers/scsi/qla4xxx/ql4_mbx.c930
-rw-r--r--drivers/scsi/qla4xxx/ql4_nvram.c224
-rw-r--r--drivers/scsi/qla4xxx/ql4_nvram.h256
-rw-r--r--drivers/scsi/qla4xxx/ql4_os.c1755
-rw-r--r--drivers/scsi/qla4xxx/ql4_version.h13
18 files changed, 7540 insertions, 0 deletions
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 8a22a71280a..3ff5ec8f0d3 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -1244,6 +1244,7 @@ config SCSI_QLOGICPTI
module will be called qlogicpti.
source "drivers/scsi/qla2xxx/Kconfig"
+source "drivers/scsi/qla4xxx/Kconfig"
config SCSI_LPFC
tristate "Emulex LightPulse Fibre Channel Support"
diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
index 1ef951be7a5..bcca39c3bcb 100644
--- a/drivers/scsi/Makefile
+++ b/drivers/scsi/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_SCSI_QLOGIC_FAS) += qlogicfas408.o qlogicfas.o
obj-$(CONFIG_PCMCIA_QLOGIC) += qlogicfas408.o
obj-$(CONFIG_SCSI_QLOGIC_1280) += qla1280.o
obj-$(CONFIG_SCSI_QLA_FC) += qla2xxx/
+obj-$(CONFIG_SCSI_QLA_ISCSI) += qla4xxx/
obj-$(CONFIG_SCSI_LPFC) += lpfc/
obj-$(CONFIG_SCSI_PAS16) += pas16.o
obj-$(CONFIG_SCSI_SEAGATE) += seagate.o
diff --git a/drivers/scsi/qla4xxx/Kconfig b/drivers/scsi/qla4xxx/Kconfig
new file mode 100644
index 00000000000..08a07f0b8d9
--- /dev/null
+++ b/drivers/scsi/qla4xxx/Kconfig
@@ -0,0 +1,7 @@
+config SCSI_QLA_ISCSI
+ tristate "QLogic ISP4XXX host adapter family support"
+ depends on PCI && SCSI
+ select SCSI_ISCSI_ATTRS
+ ---help---
+ This driver supports the QLogic 40xx (ISP4XXX) iSCSI host
+ adapter family.
diff --git a/drivers/scsi/qla4xxx/Makefile b/drivers/scsi/qla4xxx/Makefile
new file mode 100644
index 00000000000..86ea37baa0f
--- /dev/null
+++ b/drivers/scsi/qla4xxx/Makefile
@@ -0,0 +1,5 @@
+qla4xxx-y := ql4_os.o ql4_init.o ql4_mbx.o ql4_iocb.o ql4_isr.o \
+ ql4_nvram.o ql4_dbg.o
+
+obj-$(CONFIG_SCSI_QLA_ISCSI) += qla4xxx.o
+
diff --git a/drivers/scsi/qla4xxx/ql4_dbg.c b/drivers/scsi/qla4xxx/ql4_dbg.c
new file mode 100644
index 00000000000..752031fadfe
--- /dev/null
+++ b/drivers/scsi/qla4xxx/ql4_dbg.c
@@ -0,0 +1,197 @@
+/*
+ * QLogic iSCSI HBA Driver
+ * Copyright (c) 2003-2006 QLogic Corporation
+ *
+ * See LICENSE.qla4xxx for copyright and licensing details.
+ */
+
+#include "ql4_def.h"
+#include <scsi/scsi_dbg.h>
+
+static void qla4xxx_print_srb_info(struct srb * srb)
+{
+ printk("%s: srb = 0x%p, flags=0x%02x\n", __func__, srb, srb->flags);
+ printk("%s: cmd = 0x%p, saved_dma_handle = 0x%lx\n",
+ __func__, srb->cmd, (unsigned long) srb->dma_handle);
+ printk("%s: fw_ddb_index = %d, lun = %d\n",
+ __func__, srb->fw_ddb_index, srb->cmd->device->lun);
+ printk("%s: iocb_tov = %d\n",
+ __func__, srb->iocb_tov);
+ printk("%s: cc_stat = 0x%x, r_start = 0x%lx, u_start = 0x%lx\n\n",
+ __func__, srb->cc_stat, srb->r_start, srb->u_start);
+}
+
+void qla4xxx_print_scsi_cmd(struct scsi_cmnd *cmd)
+{
+ printk("SCSI Command = 0x%p, Handle=0x%p\n", cmd, cmd->host_scribble);
+ printk(" b=%d, t=%02xh, l=%02xh, cmd_len = %02xh\n",
+ cmd->device->channel, cmd->device->id, cmd->device->lun,
+ cmd->cmd_len);
+ scsi_print_command(cmd);
+ printk(" seg_cnt = %d\n", cmd->use_sg);
+ printk(" request buffer = 0x%p, request buffer len = 0x%x\n",
+ cmd->request_buffer, cmd->request_bufflen);
+ if (cmd->use_sg) {
+ struct scatterlist *sg;
+ sg = (struct scatterlist *)cmd->request_buffer;
+ printk(" SG buffer: \n");
+ qla4xxx_dump_buffer((caddr_t) sg,
+ (cmd->use_sg * sizeof(*sg)));
+ }
+ printk(" tag = %d, transfersize = 0x%x \n", cmd->tag,
+ cmd->transfersize);
+ printk(" Pid = %d, SP = 0x%p\n", (int)cmd->pid, cmd->SCp.ptr);
+ printk(" underflow size = 0x%x, direction=0x%x\n", cmd->underflow,
+ cmd->sc_data_direction);
+ printk(" Current time (jiffies) = 0x%lx, "
+ "timeout expires = 0x%lx\n", jiffies, cmd->eh_timeout.expires);
+ qla4xxx_print_srb_info((struct srb *) cmd->SCp.ptr);
+}
+
+void __dump_registers(struct scsi_qla_host *ha)
+{
+ uint8_t i;
+ for (i = 0; i < MBOX_REG_COUNT; i++) {
+ printk(KERN_INFO "0x%02X mailbox[%d] = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg, mailbox[i]), i,
+ readw(&ha->reg->mailbox[i]));
+ }
+ printk(KERN_INFO "0x%02X flash_address = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg, flash_address),
+ readw(&ha->reg->flash_address));
+ printk(KERN_INFO "0x%02X flash_data = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg, flash_data),
+ readw(&ha->reg->flash_data));
+ printk(KERN_INFO "0x%02X ctrl_status = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg, ctrl_status),
+ readw(&ha->reg->ctrl_status));
+ if (is_qla4010(ha)) {
+ printk(KERN_INFO "0x%02X nvram = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg, u1.isp4010.nvram),
+ readw(&ha->reg->u1.isp4010.nvram));
+ }
+
+ else if (is_qla4022(ha)) {
+ printk(KERN_INFO "0x%02X intr_mask = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u1.isp4022.intr_mask),
+ readw(&ha->reg->u1.isp4022.intr_mask));
+ printk(KERN_INFO "0x%02X nvram = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg, u1.isp4022.nvram),
+ readw(&ha->reg->u1.isp4022.nvram));
+ printk(KERN_INFO "0x%02X semaphore = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u1.isp4022.semaphore),
+ readw(&ha->reg->u1.isp4022.semaphore));
+ }
+ printk(KERN_INFO "0x%02X req_q_in = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg, req_q_in),
+ readw(&ha->reg->req_q_in));
+ printk(KERN_INFO "0x%02X rsp_q_out = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg, rsp_q_out),
+ readw(&ha->reg->rsp_q_out));
+ if (is_qla4010(ha)) {
+ printk(KERN_INFO "0x%02X ext_hw_conf = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u2.isp4010.ext_hw_conf),
+ readw(&ha->reg->u2.isp4010.ext_hw_conf));
+ printk(KERN_INFO "0x%02X port_ctrl = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u2.isp4010.port_ctrl),
+ readw(&ha->reg->u2.isp4010.port_ctrl));
+ printk(KERN_INFO "0x%02X port_status = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u2.isp4010.port_status),
+ readw(&ha->reg->u2.isp4010.port_status));
+ printk(KERN_INFO "0x%02X req_q_out = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u2.isp4010.req_q_out),
+ readw(&ha->reg->u2.isp4010.req_q_out));
+ printk(KERN_INFO "0x%02X gp_out = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_out),
+ readw(&ha->reg->u2.isp4010.gp_out));
+ printk(KERN_INFO "0x%02X gp_in = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_in),
+ readw(&ha->reg->u2.isp4010.gp_in));
+ printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u2.isp4010.port_err_status),
+ readw(&ha->reg->u2.isp4010.port_err_status));
+ }
+
+ else if (is_qla4022(ha)) {
+ printk(KERN_INFO "Page 0 Registers:\n");
+ printk(KERN_INFO "0x%02X ext_hw_conf = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u2.isp4022.p0.ext_hw_conf),
+ readw(&ha->reg->u2.isp4022.p0.ext_hw_conf));
+ printk(KERN_INFO "0x%02X port_ctrl = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u2.isp4022.p0.port_ctrl),
+ readw(&ha->reg->u2.isp4022.p0.port_ctrl));
+ printk(KERN_INFO "0x%02X port_status = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u2.isp4022.p0.port_status),
+ readw(&ha->reg->u2.isp4022.p0.port_status));
+ printk(KERN_INFO "0x%02X gp_out = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u2.isp4022.p0.gp_out),
+ readw(&ha->reg->u2.isp4022.p0.gp_out));
+ printk(KERN_INFO "0x%02X gp_in = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_in),
+ readw(&ha->reg->u2.isp4022.p0.gp_in));
+ printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u2.isp4022.p0.port_err_status),
+ readw(&ha->reg->u2.isp4022.p0.port_err_status));
+ printk(KERN_INFO "Page 1 Registers:\n");
+ writel(HOST_MEM_CFG_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT),
+ &ha->reg->ctrl_status);
+ printk(KERN_INFO "0x%02X req_q_out = 0x%08X\n",
+ (uint8_t) offsetof(struct isp_reg,
+ u2.isp4022.p1.req_q_out),
+ readw(&ha->reg->u2.isp4022.p1.req_q_out));
+ writel(PORT_CTRL_STAT_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT),
+ &ha->reg->ctrl_status);
+ }
+}
+
+void qla4xxx_dump_mbox_registers(struct scsi_qla_host *ha)
+{
+ unsigned long flags = 0;
+ int i = 0;
+ spin_lock_irqsave(&ha->hardware_lock, flags);
+ for (i = 1; i < MBOX_REG_COUNT; i++)
+ printk(KERN_INFO " Mailbox[%d] = %08x\n", i,
+ readw(&ha->reg->mailbox[i]));
+ spin_unlock_irqrestore(&ha->hardware_lock, flags);
+}
+
+void qla4xxx_dump_registers(struct scsi_qla_host *ha)
+{
+ unsigned long flags = 0;
+ spin_lock_irqsave(&ha->hardware_lock, flags);
+ __dump_registers(ha);
+ spin_unlock_irqrestore(&ha->hardware_lock, flags);
+}
+
+void qla4xxx_dump_buffer(void *b, uint32_t size)
+{
+ uint32_t cnt;
+ uint8_t *c = b;
+
+ printk(" 0 1 2 3 4 5 6 7 8 9 Ah Bh Ch Dh Eh "
+ "Fh\n");
+ printk("------------------------------------------------------------"
+ "--\n");
+ for (cnt = 0; cnt < size; cnt++, c++) {
+ printk(KERN_DEBUG "%02x", *c);
+ if (!(cnt % 16))
+ printk(KERN_DEBUG "\n");
+
+ else
+ printk(KERN_DEBUG " ");
+ }
+ if (cnt % 16)
+ printk(KERN_DEBUG "\n");
+}
diff --git a/drivers/scsi/qla4xxx/ql4_dbg.h b/drivers/scsi/qla4xxx/ql4_dbg.h
new file mode 100644
index 00000000000..56ddc227f84
--- /dev/null
+++ b/drivers/scsi/qla4xxx/ql4_dbg.h
@@ -0,0 +1,55 @@
+/*
+ * QLogic iSCSI HBA Driver
+ * Copyright (c) 2003-2006 QLogic Corporation
+ *
+ * See LICENSE.qla4xxx for copyright and licensing details.
+ */
+
+/*
+ * Driver debug definitions.
+ */
+/* #define QL_DEBUG */ /* DEBUG messages */
+/* #define QL_DEBUG_LEVEL_3 */ /* Output function tracing */
+/* #define QL_DEBUG_LEVEL_4 */
+/* #define QL_DEBUG_LEVEL_5 */
+/* #define QL_DEBUG_LEVEL_9 */
+
+#define QL_DEBUG_LEVEL_2 /* ALways enable error messagess */
+#if defined(QL_DEBUG)
+#define DEBUG(x) do {x;} while (0);
+#else
+#define DEBUG(x) do {} while (0);
+#endif
+
+#if defined(QL_DEBUG_LEVEL_2)
+#define DEBUG2(x) do {if(extended_error_logging == 2) x;} while (0);
+#define DEBUG2_3(x) do {x;} while (0);
+#else /* */
+#define DEBUG2(x) do {} while (0);
+#endif /* */
+
+#if defined(QL_DEBUG_LEVEL_3)
+#define DEBUG3(x) do {if(extended_error_logging == 3) x;} while (0);
+#else /* */
+#define DEBUG3(x) do {} while (0);
+#if !defined(QL_DEBUG_LEVEL_2)
+#define DEBUG2_3(x) do {} while (0);
+#endif /* */
+#endif /* */
+#if defined(QL_DEBUG_LEVEL_4)
+#define DEBUG4(x) do {x;} while (0);
+#else /* */
+#define DEBUG4(x) do {} while (0);
+#endif /* */
+
+#if defined(QL_DEBUG_LEVEL_5)
+#define DEBUG5(x) do {x;} while (0);
+#else /* */
+#define DEBUG5(x) do {} while (0);
+#endif /* */
+
+#if defined(QL_DEBUG_LEVEL_9)
+#define DEBUG9(x) do {x;} while (0);
+#else /* */
+#define DEBUG9(x) do {} while (0);
+#endif /* */
diff --git a/drivers/scsi/qla4xxx/ql4_def.h b/drivers/scsi/qla4xxx/ql4_def.h
new file mode 100644
index 00000000000..a7f6c7b1c59
--- /dev/null
+++ b/drivers/scsi/qla4xxx/ql4_def.h
@@ -0,0 +1,586 @@
+/*
+ * QLogic iSCSI HBA Driver
+ * Copyright (c) 2003-2006 QLogic Corporation
+ *
+ * See LICENSE.qla4xxx for copyright and licensing details.
+ */
+
+#ifndef __QL4_DEF_H
+#define __QL4_DEF_H
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/dmapool.h>
+#include <linux/mempool.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/mutex.h>
+
+#include <net/tcp.h>
+#include <scsi/scsi.h>
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_device.h>
+#include <scsi/scsi_cmnd.h>
+#include <scsi/scsi_transport.h>
+#include <scsi/scsi_transport_iscsi.h>
+
+
+#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
+#define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
+#endif
+
+#ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
+#define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
+#endif /* */
+
+#define QLA_SUCCESS 0
+#define QLA_ERROR 1
+
+/*
+ * Data bit definitions
+ */
+#define BIT_0 0x1
+#define BIT_1 0x2
+#define BIT_2 0x4
+#define BIT_3 0x8
+#define BIT_4 0x10
+#define BIT_5 0x20
+#define BIT_6 0x40
+#define BIT_7 0x80
+#define BIT_8 0x100
+#define BIT_9 0x200
+#define BIT_10 0x400
+#define BIT_11 0x800
+#define BIT_12 0x1000
+#define BIT_13 0x2000
+#define BIT_14 0x4000
+#define BIT_15 0x8000
+#define BIT_16 0x10000
+#define BIT_17 0x20000
+#define BIT_18 0x40000
+#define BIT_19 0x80000
+#define BIT_20 0x100000
+#define BIT_21 0x200000
+#define BIT_22 0x400000
+#define BIT_23 0x800000
+#define BIT_24 0x1000000
+#define BIT_25 0x2000000
+#define BIT_26 0x4000000
+#define BIT_27 0x8000000
+#define BIT_28 0x10000000
+#define BIT_29 0x20000000
+#define BIT_30 0x40000000
+#define BIT_31 0x80000000
+
+/*
+ * Host adapter default definitions
+ ***********************************/
+#define MAX_HBAS 16
+#define MAX_BUSES 1
+#define MAX_TARGETS (MAX_PRST_DEV_DB_ENTRIES + MAX_DEV_DB_ENTRIES)
+#define MAX_LUNS 0xffff
+#define MAX_AEN_ENTRIES 256 /* should be > EXT_DEF_MAX_AEN_QUEUE */
+#define MAX_DDB_ENTRIES (MAX_PRST_DEV_DB_ENTRIES + MAX_DEV_DB_ENTRIES)
+#define MAX_PDU_ENTRIES 32
+#define INVALID_ENTRY 0xFFFF
+#define MAX_CMDS_TO_RISC 1024
+#define MAX_SRBS MAX_CMDS_TO_RISC
+#define MBOX_AEN_REG_COUNT 5
+#define MAX_INIT_RETRIES 5
+#define IOCB_HIWAT_CUSHION 16
+
+/*
+ * Buffer sizes
+ */
+#define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
+#define RESPONSE_QUEUE_DEPTH 64
+#define QUEUE_SIZE 64
+#define DMA_BUFFER_SIZE 512
+
+/*
+ * Misc
+ */
+#define MAC_ADDR_LEN 6 /* in bytes */
+#define IP_ADDR_LEN 4 /* in bytes */
+#define DRIVER_NAME "qla4xxx"
+
+#define MAX_LINKED_CMDS_PER_LUN 3
+#define MAX_REQS_SERVICED_PER_INTR 16
+
+#define ISCSI_IPADDR_SIZE 4 /* IP address size */
+#define ISCSI_ALIAS_SIZE 32 /* ISCSI Alais name size */
+#define ISCSI_NAME_SIZE 255 /* ISCSI Name size -
+ * usually a string */
+
+#define LSDW(x) ((u32)((u64)(x)))
+#define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
+
+/*
+ * Retry & Timeout Values
+ */
+#define MBOX_TOV 60
+#define SOFT_RESET_TOV 30
+#define RESET_INTR_TOV 3
+#define SEMAPHORE_TOV 10
+#define ADAPTER_INIT_TOV 120
+#define ADAPTER_RESET_TOV 180
+#define EXTEND_CMD_TOV 60
+#define WAIT_CMD_TOV 30
+#define EH_WAIT_CMD_TOV 120
+#define FIRMWARE_UP_TOV 60
+#define RESET_FIRMWARE_TOV 30
+#define LOGOUT_TOV 10
+#define IOCB_TOV_MARGIN 10
+#define RELOGIN_TOV 18
+#define ISNS_DEREG_TOV 5
+
+#define MAX_RESET_HA_RETRIES 2
+
+/*
+ * SCSI Request Block structure (srb) that is placed
+ * on cmd->SCp location of every I/O [We have 22 bytes available]
+ */
+struct srb {
+ struct list_head list; /* (8) */
+ struct scsi_qla_host *ha; /* HA the SP is queued on */
+ struct ddb_entry *ddb;
+ uint16_t flags; /* (1) Status flags. */
+
+#define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
+#define SRB_GOT_SENSE BIT_4 /* sense data recieved. */
+ uint8_t state; /* (1) Status flags. */
+
+#define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
+#define SRB_FREE_STATE 1
+#define SRB_ACTIVE_STATE 3
+#define SRB_ACTIVE_TIMEOUT_STATE 4
+#define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
+
+ struct scsi_cmnd *cmd; /* (4) SCSI command block */
+ dma_addr_t dma_handle; /* (4) for unmap of single transfers */
+ atomic_t ref_count; /* reference count for this srb */
+ uint32_t fw_ddb_index;
+ uint8_t err_id; /* error id */
+#define SRB_ERR_PORT 1 /* Request failed because "port down" */
+#define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
+#define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
+#define SRB_ERR_OTHER 4
+
+ uint16_t reserved;
+ uint16_t iocb_tov;
+ uint16_t iocb_cnt; /* Number of used iocbs */
+ uint16_t cc_stat;
+ u_long r_start; /* Time we recieve a cmd from OS */
+ u_long u_start; /* Time when we handed the cmd to F/W */
+};
+
+ /*
+ * Device Database (DDB) structure
+ */
+struct ddb_entry {
+ struct list_head list; /* ddb list */
+ struct scsi_qla_host *ha;
+ struct iscsi_cls_session *sess;
+ struct iscsi_cls_conn *conn;
+
+ atomic_t state; /* DDB State */
+
+ unsigned long flags; /* DDB Flags */
+
+ unsigned long dev_scan_wait_to_start_relogin;
+ unsigned long dev_scan_wait_to_complete_relogin;
+
+ uint16_t os_target_id; /* Target ID */
+ uint16_t fw_ddb_index; /* DDB firmware index */
+ uint8_t reserved[2];
+ uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
+
+ uint32_t CmdSn;
+ uint16_t target_session_id;
+ uint16_t connection_id;
+ uint16_t exe_throttle; /* Max mumber of cmds outstanding
+ * simultaneously */
+ uint16_t task_mgmt_timeout; /* Min time for task mgmt cmds to
+ * complete */
+ uint16_t default_relogin_timeout; /* Max time to wait for
+ * relogin to complete */
+ uint16_t tcp_source_port_num;
+ uint32_t default_time2wait; /* Default Min time between
+ * relogins (+aens) */
+
+ atomic_t port_down_timer; /* Device connection timer */
+ atomic_t retry_relogin_timer; /* Min Time between relogins
+ * (4000 only) */
+ atomic_t relogin_timer; /* Max Time to wait for relogin to complete */
+ atomic_t relogin_retry_count; /* Num of times relogin has been
+ * retried */
+
+ uint16_t port;
+ uint32_t tpgt;
+ uint8_t ip_addr[ISCSI_IPADDR_SIZE];
+ uint8_t iscsi_name[ISCSI_NAME_SIZE]; /* 72 x48 */
+ uint8_t iscsi_alias[0x20];
+};
+
+/*
+ * DDB states.
+ */
+#define DDB_STATE_DEAD 0 /* We can no longer talk to
+ * this device */
+#define DDB_STATE_ONLINE 1 /* Device ready to accept
+ * commands */
+#define DDB_STATE_MISSING 2 /* Device logged off, trying
+ * to re-login */
+
+/*
+ * DDB flags.
+ */
+#define DF_RELOGIN 0 /* Relogin to device */
+#define DF_NO_RELOGIN 1 /* Do not relogin if IOCTL
+ * logged it out */
+#define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
+#define DF_FO_MASKED 3
+
+/*
+ * Asynchronous Event Queue structure
+ */
+struct aen {
+ uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
+};
+
+
+#include "ql4_fw.h"
+#include "ql4_nvram.h"
+
+/*
+ * Linux Host Adapter structure
+ */
+struct scsi_qla_host {
+ /* Linux adapter configuration data */
+ struct Scsi_Host *host; /* pointer to host data */
+ uint32_t tot_ddbs;
+ unsigned long flags;
+
+#define AF_ONLINE 0 /* 0x00000001 */
+#define AF_INIT_DONE 1 /* 0x00000002 */
+#define AF_MBOX_COMMAND 2 /* 0x00000004 */
+#define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
+#define AF_INTERRUPTS_ON 6 /* 0x00000040 Not Used */
+#define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
+#define AF_LINK_UP 8 /* 0x00000100 */
+#define AF_TOPCAT_CHIP_PRESENT 9 /* 0x00000200 */
+#define AF_IRQ_ATTACHED 10 /* 0x00000400 */
+#define AF_ISNS_CMD_IN_PROCESS 12 /* 0x00001000 */
+#define AF_ISNS_CMD_DONE 13 /* 0x00002000 */
+
+ unsigned long dpc_flags;
+
+#define DPC_RESET_HA 1 /* 0x00000002 */
+#define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
+#define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
+#define DPC_RESET_HA_DESTROY_DDB_LIST 4 /* 0x00000010 */
+#define DPC_RESET_HA_INTR 5 /* 0x00000020 */
+#define DPC_ISNS_RESTART 7 /* 0x00000080 */
+#define DPC_AEN 9 /* 0x00000200 */
+#define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
+
+ uint16_t iocb_cnt;
+ uint16_t iocb_hiwat;
+
+ /* SRB cache. */
+#define SRB_MIN_REQ 128
+ mempool_t *srb_mempool;
+
+ /* pci information */
+ struct pci_dev *pdev;
+
+ struct isp_reg __iomem *reg; /* Base I/O address */
+ unsigned long pio_address;
+ unsigned long pio_length;
+#define MIN_IOBASE_LEN 0x100
+
+ uint16_t req_q_count;
+ uint8_t marker_needed;
+ uint8_t rsvd1;
+
+ unsigned long host_no;
+
+ /* NVRAM registers */
+ struct eeprom_data *nvram;
+ spinlock_t hardware_lock ____cacheline_aligned;
+ spinlock_t list_lock;
+ uint32_t eeprom_cmd_data;
+
+ /* Counters for general statistics */
+ uint64_t adapter_error_count;
+ uint64_t device_error_count;
+ uint64_t total_io_count;
+ uint64_t total_mbytes_xferred;
+ uint64_t link_failure_count;
+ uint64_t invalid_crc_count;
+ uint32_t spurious_int_count;
+ uint32_t aborted_io_count;
+ uint32_t io_timeout_count;
+ uint32_t mailbox_timeout_count;
+ uint32_t seconds_since_last_intr;
+ uint32_t seconds_since_last_heartbeat;
+ uint32_t mac_index;
+
+ /* Info Needed for Management App */
+ /* --- From GetFwVersion --- */
+ uint32_t firmware_version[2];
+ uint32_t patch_number;
+ uint32_t build_number;
+
+ /* --- From Init_FW --- */
+ /* init_cb_t *init_cb; */
+ uint16_t firmware_options;
+ uint16_t tcp_options;
+ uint8_t ip_address[IP_ADDR_LEN];
+ uint8_t subnet_mask[IP_ADDR_LEN];
+ uint8_t gateway[IP_ADDR_LEN];
+ uint8_t alias[32];
+ uint8_t name_string[256];
+ uint8_t heartbeat_interval;
+ uint8_t rsvd;
+
+ /* --- From FlashSysInfo --- */
+ uint8_t my_mac[MAC_ADDR_LEN];
+ uint8_t serial_number[16];
+
+ /* --- From GetFwState --- */
+ uint32_t firmware_state;
+ uint32_t board_id;
+ uint32_t addl_fw_state;
+
+ /* Linux kernel thread */
+ struct workqueue_struct *dpc_thread;
+ struct work_struct dpc_work;
+
+ /* Linux timer thread */
+ struct timer_list timer;
+ uint32_t timer_active;
+
+ /* Recovery Timers */
+ uint32_t port_down_retry_count;
+ uint32_t discovery_wait;
+ atomic_t check_relogin_timeouts;
+ uint32_t retry_reset_ha_cnt;
+ uint32_t isp_reset_timer; /* reset test timer */
+ uint32_t nic_reset_timer; /* simulated nic reset test timer */
+ int eh_start;
+ struct list_head free_srb_q;
+ uint16_t free_srb_q_count;
+ uint16_t num_srbs_allocated;
+
+ /* DMA Memory Block */
+ void *queues;
+ dma_addr_t queues_dma;
+ unsigned long queues_len;
+
+#define MEM_ALIGN_VALUE \
+ ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
+ sizeof(struct queue_entry))
+ /* request and response queue variables */
+ dma_addr_t request_dma;
+ struct queue_entry *request_ring;
+ struct queue_entry *request_ptr;
+ dma_addr_t response_dma;
+ struct queue_entry *response_ring;
+ struct queue_entry *response_ptr;
+ dma_addr_t shadow_regs_dma;
+ struct shadow_regs *shadow_regs;
+ uint16_t request_in; /* Current indexes. */
+ uint16_t request_out;
+ uint16_t response_in;
+ uint16_t response_out;
+
+ /* aen queue variables */
+ uint16_t aen_q_count; /* Number of available aen_q entries */
+ uint16_t aen_in; /* Current indexes */
+ uint16_t aen_out;
+ struct aen aen_q[MAX_AEN_ENTRIES];
+
+ /* This mutex protects several threads to do mailbox commands
+ * concurrently.
+ */
+ struct mutex mbox_sem;
+ wait_queue_head_t mailbox_wait_queue;
+
+ /* temporary mailbox status registers */
+ volatile uint8_t mbox_status_count;
+ volatile uint32_t mbox_status[MBOX_REG_COUNT];
+
+ /* local device database list (contains internal ddb entries) */
+ struct list_head ddb_list;
+
+ /* Map ddb_list entry by FW ddb index */
+ struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
+
+};
+
+static inline int is_qla4010(struct scsi_qla_host *ha)
+{
+ return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
+}
+
+static inline int is_qla4022(struct scsi_qla_host *ha)
+{
+ return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
+}
+
+static inline int adapter_up(struct scsi_qla_host *ha)
+{
+ return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
+ (test_bit(AF_LINK_UP, &ha->flags) != 0);
+}
+
+static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
+{
+ return (struct scsi_qla_host *)shost->hostdata;
+}
+
+static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
+{
+ return (is_qla4022(ha) ?
+ &ha->reg->u1.isp4022.semaphore :
+ &ha->reg->u1.isp4010.nvram);
+}
+
+static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
+{
+ return (is_qla4022(ha) ?
+ &ha->reg->u1.isp4022.nvram :
+ &ha->reg->u1.isp4010.nvram);
+}
+
+static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
+{
+ return (is_qla4022(ha) ?
+ &ha->reg->u2.isp4022.p0.ext_hw_conf :
+ &ha->reg->u2.isp4010.ext_hw_conf);
+}
+
+static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
+{
+ return (is_qla4022(ha) ?
+ &ha->reg->u2.isp4022.p0.port_status :
+ &ha->reg->u2.isp4010.port_status);
+}
+
+static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
+{
+ return (is_qla4022(ha) ?
+ &ha->reg->u2.isp4022.p0.port_ctrl :
+ &ha->reg->u2.isp4010.port_ctrl);
+}
+
+static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
+{
+ return (is_qla4022(ha) ?
+ &ha->reg->u2.isp4022.p0.port_err_status :
+ &ha->reg->u2.isp4010.port_err_status);
+}
+
+static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
+{
+ return (is_qla4022(ha) ?
+ &ha->reg->u2.isp4022.p0.gp_out :
+ &ha->reg->u2.isp4010.gp_out);
+}
+
+static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
+{
+ return (is_qla4022(ha) ?
+ offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2 :
+ offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2);
+}
+
+int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
+void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
+int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
+
+static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
+{
+ if (is_qla4022(a))
+ return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
+ (QL4022_RESOURCE_BITS_BASE_CODE |
+ (a->mac_index)) << 13);
+ else
+ return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
+ QL4010_FLASH_SEM_BITS);
+}
+
+static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
+{
+ if (is_qla4022(a))
+ ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
+ else
+ ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
+}
+
+static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
+{
+ if (is_qla4022(a))
+ return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
+ (QL4022_RESOURCE_BITS_BASE_CODE |
+ (a->mac_index)) << 10);
+ else
+ return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
+ QL4010_NVRAM_SEM_BITS);
+}
+
+static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
+{
+ if (is_qla4022(a))
+ ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
+ else
+ ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
+}
+
+static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
+{
+ if (is_qla4022(a))
+ return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
+ (QL4022_RESOURCE_BITS_BASE_CODE |
+ (a->mac_index)) << 1);
+ else
+ return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
+ QL4010_DRVR_SEM_BITS);
+}
+
+static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
+{
+ if (is_qla4022(a))
+ ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
+ else
+ ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
+}
+
+/*---------------------------------------------------------------------------*/
+
+/* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
+#define PRESERVE_DDB_LIST 0
+#define REBUILD_DDB_LIST 1
+
+/* Defines for process_aen() */
+#define PROCESS_ALL_AENS 0
+#define FLUSH_DDB_CHANGED_AENS 1
+#define RELOGIN_DDB_CHANGED_AENS 2
+
+#include "ql4_version.h"
+#include "ql4_glbl.h"
+#include "ql4_dbg.h"
+#include "ql4_inline.h"
+
+
+#endif /*_QLA4XXX_H */
diff --git a/drivers/scsi/qla4xxx/ql4_fw.h b/drivers/scsi/qla4xxx/ql4_fw.h
new file mode 100644
index 00000000000..427489de64b
--- /dev/null
+++ b/drivers/scsi/qla4xxx/ql4_fw.h
@@ -0,0 +1,843 @@
+/*
+ * QLogic iSCSI HBA Driver
+ * Copyright (c) 2003-2006 QLogic Corporation
+ *
+ * See LICENSE.qla4xxx for copyright and licensing details.
+ */
+
+#ifndef _QLA4X_FW_H
+#define _QLA4X_FW_H
+
+
+#define MAX_PRST_DEV_DB_ENTRIES 64
+#define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES
+#define MAX_DEV_DB_ENTRIES 512
+
+/*************************************************************************
+ *
+ * ISP 4010 I/O Register Set Structure and Definitions
+ *
+ *************************************************************************/
+
+struct port_ctrl_stat_regs {
+ __le32 ext_hw_conf; /* 80 x50 R/W */
+ __le32 intChipConfiguration; /* 84 x54 */
+ __le32 port_ctrl; /* 88 x58 */
+ __le32 port_status; /* 92 x5c */
+ __le32 HostPrimMACHi; /* 96 x60 */
+ __le32 HostPrimMACLow; /* 100 x64 */
+ __le32 HostSecMACHi; /* 104 x68 */
+ __le32 HostSecMACLow; /* 108 x6c */
+ __le32 EPPrimMACHi; /* 112 x70 */
+ __le32 EPPrimMACLow; /* 116 x74 */
+ __le32 EPSecMACHi; /* 120 x78 */
+ __le32 EPSecMACLow; /* 124 x7c */
+ __le32 HostPrimIPHi; /* 128 x80 */
+ __le32 HostPrimIPMidHi; /* 132 x84 */
+ __le32 HostPrimIPMidLow; /* 136 x88 */
+ __le32 HostPrimIPLow; /* 140 x8c */
+ __le32 HostSecIPHi; /* 144 x90 */
+ __le32 HostSecIPMidHi; /* 148 x94 */
+ __le32 HostSecIPMidLow; /* 152 x98 */
+ __le32 HostSecIPLow; /* 156 x9c */
+ __le32 EPPrimIPHi; /* 160 xa0 */
+ __le32 EPPrimIPMidHi; /* 164 xa4 */
+ __le32 EPPrimIPMidLow; /* 168 xa8 */
+ __le32 EPPrimIPLow; /* 172 xac */
+ __le32 EPSecIPHi; /* 176 xb0 */
+ __le32 EPSecIPMidHi; /* 180 xb4 */
+ __le32 EPSecIPMidLow; /* 184 xb8 */
+ __le32 EPSecIPLow; /* 188 xbc */
+ __le32 IPReassemblyTimeout; /* 192 xc0 */
+ __le32 EthMaxFramePayload; /* 196 xc4 */
+ __le32 TCPMaxWindowSize; /* 200 xc8 */
+ __le32 TCPCurrentTimestampHi; /* 204 xcc */
+ __le32 TCPCurrentTimestampLow; /* 208 xd0 */
+ __le32 LocalRAMAddress; /* 212 xd4 */
+ __le32 LocalRAMData; /* 216 xd8 */
+ __le32 PCSReserved1; /* 220 xdc */
+ __le32 gp_out; /* 224 xe0 */
+ __le32 gp_in; /* 228 xe4 */
+ __le32 ProbeMuxAddr; /* 232 xe8 */
+ __le32 ProbeMuxData; /* 236 xec */
+ __le32 ERMQueueBaseAddr0; /* 240 xf0 */
+ __le32 ERMQueueBaseAddr1; /* 244 xf4 */
+ __le32 MACConfiguration; /* 248 xf8 */
+ __le32 port_err_status; /* 252 xfc COR */
+};
+
+struct host_mem_cfg_regs {
+ __le32 NetRequestQueueOut; /* 80 x50 */
+ __le32 NetRequestQueueOutAddrHi; /* 84 x54 */
+ __le32 NetRequestQueueOutAddrLow; /* 88 x58 */
+ __le32 NetRequestQueueBaseAddrHi; /* 92 x5c */
+ __le32 NetRequestQueueBaseAddrLow; /* 96 x60 */
+ __le32 NetRequestQueueLength; /* 100 x64 */