diff options
Diffstat (limited to 'drivers/scsi/FlashPoint.c')
| -rw-r--r-- | drivers/scsi/FlashPoint.c | 9811 |
1 files changed, 4613 insertions, 5198 deletions
diff --git a/drivers/scsi/FlashPoint.c b/drivers/scsi/FlashPoint.c index 8d64f0bed62..8e3d949b711 100644 --- a/drivers/scsi/FlashPoint.c +++ b/drivers/scsi/FlashPoint.c @@ -15,116 +15,46 @@ */ - #include <linux/config.h> - #ifndef CONFIG_SCSI_OMIT_FLASHPOINT - #define MAX_CARDS 8 #undef BUSTYPE_PCI - -#define OS_InPortByte(port) inb(port) -#define OS_InPortWord(port) inw(port) -#define OS_InPortLong(port) inl(port) -#define OS_OutPortByte(port, value) outb(value, port) -#define OS_OutPortWord(port, value) outw(value, port) -#define OS_OutPortLong(port, value) outl(value, port) - - -/* - Define name replacements for compatibility with the Linux BusLogic Driver. -*/ - -#define SccbMgr_sense_adapter FlashPoint_ProbeHostAdapter -#define SccbMgr_config_adapter FlashPoint_HardwareResetHostAdapter -#define SccbMgr_unload_card FlashPoint_ReleaseHostAdapter -#define SccbMgr_start_sccb FlashPoint_StartCCB -#define SccbMgr_abort_sccb FlashPoint_AbortCCB -#define SccbMgr_my_int FlashPoint_InterruptPending -#define SccbMgr_isr FlashPoint_HandleInterrupt - - -#define MAX_CDBLEN 12 - -#define SCAM_LEV_2 1 - #define CRCMASK 0xA001 -#define BL_VENDOR_ID 0x104B -#define FP_DEVICE_ID 0x8130 -#define MM_DEVICE_ID 0x1040 - - #define FAILURE 0xFFFFFFFFL - -typedef unsigned char UCHAR; -typedef unsigned short USHORT; -typedef unsigned int UINT; -typedef unsigned long ULONG; -typedef unsigned char * PUCHAR; -typedef unsigned short* PUSHORT; -typedef unsigned long * PULONG; -typedef void * PVOID; - - -typedef unsigned char * uchar_ptr; -typedef unsigned short * ushort_ptr; -typedef unsigned long * ulong_ptr; - - -#define s08bits char -#define s16bits short -#define s32bits long - -#define u08bits unsigned s08bits -#define u16bits unsigned s16bits -#define u32bits unsigned s32bits - -typedef u08bits * pu08bits; -typedef u16bits * pu16bits; -typedef u32bits * pu32bits; - - -#define BIT(x) ((UCHAR)(1<<(x))) /* single-bit mask in bit position x */ -#define BITW(x) ((USHORT)(1<<(x))) /* single-bit mask in bit position x */ - - - - -typedef struct _SCCB *PSCCB; -typedef void (*CALL_BK_FN)(PSCCB); - - -typedef struct SCCBMgr_info { - ULONG si_baseaddr; - UCHAR si_present; - UCHAR si_intvect; - UCHAR si_id; - UCHAR si_lun; - USHORT si_fw_revision; - USHORT si_per_targ_init_sync; - USHORT si_per_targ_fast_nego; - USHORT si_per_targ_ultra_nego; - USHORT si_per_targ_no_disc; - USHORT si_per_targ_wide_nego; - USHORT si_flags; - UCHAR si_card_family; - UCHAR si_bustype; - UCHAR si_card_model[3]; - UCHAR si_relative_cardnum; - UCHAR si_reserved[4]; - ULONG si_OS_reserved; - UCHAR si_XlatInfo[4]; - ULONG si_reserved2[5]; - ULONG si_secondary_range; -} SCCBMGR_INFO; - -typedef SCCBMGR_INFO * PSCCBMGR_INFO; - +#define BIT(x) ((unsigned char)(1<<(x))) /* single-bit mask in bit position x */ +#define BITW(x) ((unsigned short)(1<<(x))) /* single-bit mask in bit position x */ + +struct sccb; +typedef void (*CALL_BK_FN) (struct sccb *); + +struct sccb_mgr_info { + unsigned long si_baseaddr; + unsigned char si_present; + unsigned char si_intvect; + unsigned char si_id; + unsigned char si_lun; + unsigned short si_fw_revision; + unsigned short si_per_targ_init_sync; + unsigned short si_per_targ_fast_nego; + unsigned short si_per_targ_ultra_nego; + unsigned short si_per_targ_no_disc; + unsigned short si_per_targ_wide_nego; + unsigned short si_flags; + unsigned char si_card_family; + unsigned char si_bustype; + unsigned char si_card_model[3]; + unsigned char si_relative_cardnum; + unsigned char si_reserved[4]; + unsigned long si_OS_reserved; + unsigned char si_XlatInfo[4]; + unsigned long si_reserved2[5]; + unsigned long si_secondary_range; +}; #define SCSI_PARITY_ENA 0x0001 #define LOW_BYTE_TERM 0x0010 @@ -138,107 +68,81 @@ typedef SCCBMGR_INFO * PSCCBMGR_INFO; #define FLAG_SCAM_ENABLED 0x0080 #define FLAG_SCAM_LEVEL2 0x0100 - - - #define HARPOON_FAMILY 0x02 - -#define ISA_BUS_CARD 0x01 -#define EISA_BUS_CARD 0x02 -#define PCI_BUS_CARD 0x03 -#define VESA_BUS_CARD 0x04 - /* SCCB struct used for both SCCB and UCB manager compiles! * The UCB Manager treats the SCCB as it's 'native hardware structure' */ - #pragma pack(1) -typedef struct _SCCB { - UCHAR OperationCode; - UCHAR ControlByte; - UCHAR CdbLength; - UCHAR RequestSenseLength; - ULONG DataLength; - ULONG DataPointer; - UCHAR CcbRes[2]; - UCHAR HostStatus; - UCHAR TargetStatus; - UCHAR TargID; - UCHAR Lun; - UCHAR Cdb[12]; - UCHAR CcbRes1; - UCHAR Reserved1; - ULONG Reserved2; - ULONG SensePointer; - - - CALL_BK_FN SccbCallback; /* VOID (*SccbCallback)(); */ - ULONG SccbIOPort; /* Identifies board base port */ - UCHAR SccbStatus; - UCHAR SCCBRes2; - USHORT SccbOSFlags; - - - ULONG Sccb_XferCnt; /* actual transfer count */ - ULONG Sccb_ATC; - ULONG SccbVirtDataPtr; /* virtual addr for OS/2 */ - ULONG Sccb_res1; - USHORT Sccb_MGRFlags; - USHORT Sccb_sgseg; - UCHAR Sccb_scsimsg; /* identify msg for selection */ - UCHAR Sccb_tag; - UCHAR Sccb_scsistat; - UCHAR Sccb_idmsg; /* image of last msg in */ - PSCCB Sccb_forwardlink; - PSCCB Sccb_backlink; - ULONG Sccb_savedATC; - UCHAR Save_Cdb[6]; - UCHAR Save_CdbLen; - UCHAR Sccb_XferState; - ULONG Sccb_SGoffset; - } SCCB; - -#define SCCB_SIZE sizeof(SCCB) +struct sccb { + unsigned char OperationCode; + unsigned char ControlByte; + unsigned char CdbLength; + unsigned char RequestSenseLength; + unsigned long DataLength; + unsigned long DataPointer; + unsigned char CcbRes[2]; + unsigned char HostStatus; + unsigned char TargetStatus; + unsigned char TargID; + unsigned char Lun; + unsigned char Cdb[12]; + unsigned char CcbRes1; + unsigned char Reserved1; + unsigned long Reserved2; + unsigned long SensePointer; + + CALL_BK_FN SccbCallback; /* VOID (*SccbCallback)(); */ + unsigned long SccbIOPort; /* Identifies board base port */ + unsigned char SccbStatus; + unsigned char SCCBRes2; + unsigned short SccbOSFlags; + + unsigned long Sccb_XferCnt; /* actual transfer count */ + unsigned long Sccb_ATC; + unsigned long SccbVirtDataPtr; /* virtual addr for OS/2 */ + unsigned long Sccb_res1; + unsigned short Sccb_MGRFlags; + unsigned short Sccb_sgseg; + unsigned char Sccb_scsimsg; /* identify msg for selection */ + unsigned char Sccb_tag; + unsigned char Sccb_scsistat; + unsigned char Sccb_idmsg; /* image of last msg in */ + struct sccb *Sccb_forwardlink; + struct sccb *Sccb_backlink; + unsigned long Sccb_savedATC; + unsigned char Save_Cdb[6]; + unsigned char Save_CdbLen; + unsigned char Sccb_XferState; + unsigned long Sccb_SGoffset; +}; #pragma pack() - - -#define SCSI_INITIATOR_COMMAND 0x00 -#define TARGET_MODE_COMMAND 0x01 #define SCATTER_GATHER_COMMAND 0x02 #define RESIDUAL_COMMAND 0x03 #define RESIDUAL_SG_COMMAND 0x04 #define RESET_COMMAND 0x81 +#define F_USE_CMD_Q 0x20 /*Inidcates TAGGED command. */ +#define TAG_TYPE_MASK 0xC0 /*Type of tag msg to send. */ +#define SCCB_DATA_XFER_OUT 0x10 /* Write */ +#define SCCB_DATA_XFER_IN 0x08 /* Read */ -#define F_USE_CMD_Q 0x20 /*Inidcates TAGGED command. */ -#define TAG_TYPE_MASK 0xC0 /*Type of tag msg to send. */ -#define TAG_Q_MASK 0xE0 -#define SCCB_DATA_XFER_OUT 0x10 /* Write */ -#define SCCB_DATA_XFER_IN 0x08 /* Read */ +#define NO_AUTO_REQUEST_SENSE 0x01 /* No Request Sense Buffer */ - -#define FOURTEEN_BYTES 0x00 /* Request Sense Buffer size */ -#define NO_AUTO_REQUEST_SENSE 0x01 /* No Request Sense Buffer */ - - -#define BUS_FREE_ST 0 +#define BUS_FREE_ST 0 #define SELECT_ST 1 -#define SELECT_BDR_ST 2 /* Select w\ Bus Device Reset */ -#define SELECT_SN_ST 3 /* Select w\ Sync Nego */ -#define SELECT_WN_ST 4 /* Select w\ Wide Data Nego */ -#define SELECT_Q_ST 5 /* Select w\ Tagged Q'ing */ +#define SELECT_BDR_ST 2 /* Select w\ Bus Device Reset */ +#define SELECT_SN_ST 3 /* Select w\ Sync Nego */ +#define SELECT_WN_ST 4 /* Select w\ Wide Data Nego */ +#define SELECT_Q_ST 5 /* Select w\ Tagged Q'ing */ #define COMMAND_ST 6 #define DATA_OUT_ST 7 #define DATA_IN_ST 8 #define DISCONNECT_ST 9 -#define STATUS_ST 10 #define ABORT_ST 11 -#define MESSAGE_ST 12 - #define F_HOST_XFER_DIR 0x01 #define F_ALL_XFERRED 0x02 @@ -247,163 +151,115 @@ typedef struct _SCCB { #define F_ODD_BALL_CNT 0x10 #define F_NO_DATA_YET 0x80 - #define F_STATUSLOADED 0x01 -#define F_MSGLOADED 0x02 #define F_DEV_SELECTED 0x04 - -#define SCCB_COMPLETE 0x00 /* SCCB completed without error */ +#define SCCB_COMPLETE 0x00 /* SCCB completed without error */ #define SCCB_DATA_UNDER_RUN 0x0C -#define SCCB_SELECTION_TIMEOUT 0x11 /* Set SCSI selection timed out */ +#define SCCB_SELECTION_TIMEOUT 0x11 /* Set SCSI selection timed out */ #define SCCB_DATA_OVER_RUN 0x12 -#define SCCB_UNEXPECTED_BUS_FREE 0x13 /* Target dropped SCSI BSY */ -#define SCCB_PHASE_SEQUENCE_FAIL 0x14 /* Target bus phase sequence failure */ - -#define SCCB_INVALID_OP_CODE 0x16 /* SCCB invalid operation code */ -#define SCCB_INVALID_SCCB 0x1A /* Invalid SCCB - bad parameter */ -#define SCCB_GROSS_FW_ERR 0x27 /* Major problem! */ -#define SCCB_BM_ERR 0x30 /* BusMaster error. */ -#define SCCB_PARITY_ERR 0x34 /* SCSI parity error */ - - - -#define SCCB_INVALID_DIRECTION 0x18 /* Invalid target direction */ -#define SCCB_DUPLICATE_SCCB 0x19 /* Duplicate SCCB */ -#define SCCB_SCSI_RST 0x35 /* SCSI RESET detected. */ +#define SCCB_PHASE_SEQUENCE_FAIL 0x14 /* Target bus phase sequence failure */ +#define SCCB_GROSS_FW_ERR 0x27 /* Major problem! */ +#define SCCB_BM_ERR 0x30 /* BusMaster error. */ +#define SCCB_PARITY_ERR 0x34 /* SCSI parity error */ #define SCCB_IN_PROCESS 0x00 #define SCCB_SUCCESS 0x01 #define SCCB_ABORT 0x02 -#define SCCB_NOT_FOUND 0x03 #define SCCB_ERROR 0x04 -#define SCCB_INVALID 0x05 - -#define SCCB_SIZE sizeof(SCCB) - #define ORION_FW_REV 3110 -#define HARP_REVD 1 - - -#define QUEUE_DEPTH 254+1 /*1 for Normal disconnect 32 for Q'ing. */ +#define QUEUE_DEPTH 254+1 /*1 for Normal disconnect 32 for Q'ing. */ -#define MAX_MB_CARDS 4 /* Max. no of cards suppoerted on Mother Board */ - -#define WIDE_SCSI 1 +#define MAX_MB_CARDS 4 /* Max. no of cards suppoerted on Mother Board */ #define MAX_SCSI_TAR 16 #define MAX_LUN 32 #define LUN_MASK 0x1f -#if defined(HARP_REVA) -#define SG_BUF_CNT 15 /*Number of prefetched elements. */ -#else -#define SG_BUF_CNT 16 /*Number of prefetched elements. */ -#endif - -#define SG_ELEMENT_SIZE 8 /*Eight byte per element. */ -#define SG_LOCAL_MASK 0x00000000L -#define SG_ELEMENT_MASK 0xFFFFFFFFL - +#define SG_BUF_CNT 16 /*Number of prefetched elements. */ -#define RD_HARPOON(ioport) OS_InPortByte((u32bits)ioport) -#define RDW_HARPOON(ioport) OS_InPortWord((u32bits)ioport) -#define RD_HARP32(ioport,offset,data) (data = OS_InPortLong((u32bits)(ioport + offset))) -#define WR_HARPOON(ioport,val) OS_OutPortByte((u32bits)ioport,(u08bits) val) -#define WRW_HARPOON(ioport,val) OS_OutPortWord((u32bits)ioport,(u16bits)val) -#define WR_HARP32(ioport,offset,data) OS_OutPortLong((u32bits)(ioport + offset), data) +#define SG_ELEMENT_SIZE 8 /*Eight byte per element. */ +#define RD_HARPOON(ioport) inb((u32)ioport) +#define RDW_HARPOON(ioport) inw((u32)ioport) +#define RD_HARP32(ioport,offset,data) (data = inl((u32)(ioport + offset))) +#define WR_HARPOON(ioport,val) outb((u8) val, (u32)ioport) +#define WRW_HARPOON(ioport,val) outw((u16)val, (u32)ioport) +#define WR_HARP32(ioport,offset,data) outl(data, (u32)(ioport + offset)) #define TAR_SYNC_MASK (BIT(7)+BIT(6)) -#define SYNC_UNKNOWN 0x00 #define SYNC_TRYING BIT(6) #define SYNC_SUPPORTED (BIT(7)+BIT(6)) #define TAR_WIDE_MASK (BIT(5)+BIT(4)) -#define WIDE_DISABLED 0x00 #define WIDE_ENABLED BIT(4) #define WIDE_NEGOCIATED BIT(5) #define TAR_TAG_Q_MASK (BIT(3)+BIT(2)) -#define TAG_Q_UNKNOWN 0x00 #define TAG_Q_TRYING BIT(2) #define TAG_Q_REJECT BIT(3) -#define TAG_Q_SUPPORTED (BIT(3)+BIT(2)) #define TAR_ALLOW_DISC BIT(0) - #define EE_SYNC_MASK (BIT(0)+BIT(1)) -#define EE_SYNC_ASYNC 0x00 #define EE_SYNC_5MB BIT(0) #define EE_SYNC_10MB BIT(1) #define EE_SYNC_20MB (BIT(0)+BIT(1)) -#define EE_ALLOW_DISC BIT(6) #define EE_WIDE_SCSI BIT(7) - -typedef struct SCCBMgr_tar_info *PSCCBMgr_tar_info; - - -typedef struct SCCBMgr_tar_info { - - PSCCB TarSelQ_Head; - PSCCB TarSelQ_Tail; - UCHAR TarLUN_CA; /*Contingent Allgiance */ - UCHAR TarTagQ_Cnt; - UCHAR TarSelQ_Cnt; - UCHAR TarStatus; - UCHAR TarEEValue; - UCHAR TarSyncCtrl; - UCHAR TarReserved[2]; /* for alignment */ - UCHAR LunDiscQ_Idx[MAX_LUN]; - UCHAR TarLUNBusy[MAX_LUN]; -} SCCBMGR_TAR_INFO; - -typedef struct NVRAMInfo { - UCHAR niModel; /* Model No. of card */ - UCHAR niCardNo; /* Card no. */ - ULONG niBaseAddr; /* Port Address of card */ - UCHAR niSysConf; /* Adapter Configuration byte - Byte 16 of eeprom map */ - UCHAR niScsiConf; /* SCSI Configuration byte - Byte 17 of eeprom map */ - UCHAR niScamConf; /* SCAM Configuration byte - Byte 20 of eeprom map */ - UCHAR niAdapId; /* Host Adapter ID - Byte 24 of eerpom map */ - UCHAR niSyncTbl[MAX_SCSI_TAR / 2]; /* Sync/Wide byte of targets */ - UCHAR niScamTbl[MAX_SCSI_TAR][4]; /* Compressed Scam name string of Targets */ -}NVRAMINFO; - -typedef NVRAMINFO *PNVRamInfo; +struct sccb_mgr_tar_info { + + struct sccb *TarSelQ_Head; + struct sccb *TarSelQ_Tail; + unsigned char TarLUN_CA; /*Contingent Allgiance */ + unsigned char TarTagQ_Cnt; + unsigned char TarSelQ_Cnt; + unsigned char TarStatus; + unsigned char TarEEValue; + unsigned char TarSyncCtrl; + unsigned char TarReserved[2]; /* for alignment */ + unsigned char LunDiscQ_Idx[MAX_LUN]; + unsigned char TarLUNBusy[MAX_LUN]; +}; + +struct nvram_info { + unsigned char niModel; /* Model No. of card */ + unsigned char niCardNo; /* Card no. */ + unsigned long niBaseAddr; /* Port Address of card */ + unsigned char niSysConf; /* Adapter Configuration byte - Byte 16 of eeprom map */ + unsigned char niScsiConf; /* SCSI Configuration byte - Byte 17 of eeprom map */ + unsigned char niScamConf; /* SCAM Configuration byte - Byte 20 of eeprom map */ + unsigned char niAdapId; /* Host Adapter ID - Byte 24 of eerpom map */ + unsigned char niSyncTbl[MAX_SCSI_TAR / 2]; /* Sync/Wide byte of targets */ + unsigned char niScamTbl[MAX_SCSI_TAR][4]; /* Compressed Scam name string of Targets */ +}; #define MODEL_LT 1 #define MODEL_DL 2 #define MODEL_LW 3 #define MODEL_DW 4 +struct sccb_card { + struct sccb *currentSCCB; + struct sccb_mgr_info *cardInfo; -typedef struct SCCBcard { - PSCCB currentSCCB; - PSCCBMGR_INFO cardInfo; - - ULONG ioPort; - - USHORT cmdCounter; - UCHAR discQCount; - UCHAR tagQ_Lst; - UCHAR cardIndex; - UCHAR scanIndex; - UCHAR globalFlags; - UCHAR ourId; - PNVRamInfo pNvRamInfo; - PSCCB discQ_Tbl[QUEUE_DEPTH]; - -}SCCBCARD; + unsigned long ioPort; -typedef struct SCCBcard *PSCCBcard; + unsigned short cmdCounter; + unsigned char discQCount; + unsigned char tagQ_Lst; + unsigned char cardIndex; + unsigned char scanIndex; + unsigned char globalFlags; + unsigned char ourId; + struct nvram_info *pNvRamInfo; + struct sccb *discQ_Tbl[QUEUE_DEPTH]; +}; #define F_TAG_STARTED 0x01 #define F_CONLUN_IO 0x02 @@ -414,13 +270,10 @@ typedef struct SCCBcard *PSCCBcard; #define F_NEW_SCCB_CMD 0x40 #define F_UPDATE_EEPROM 0x80 - #define ID_STRING_LENGTH 32 -#define TYPE_CODE0 0x63 /*Level2 Mstr (bits 7-6), */ - -#define TYPE_CODE1 00 /*No ID yet */ +#define TYPE_CODE0 0x63 /*Level2 Mstr (bits 7-6), */ -#define SLV_TYPE_CODE0 0xA3 /*Priority Bit set (bits 7-6), */ +#define SLV_TYPE_CODE0 0xA3 /*Priority Bit set (bits 7-6), */ #define ASSIGN_ID 0x00 #define SET_P_FLAG 0x01 @@ -430,97 +283,42 @@ typedef struct SCCBcard *PSCCBcard; #define ID_0_7 0x18 #define ID_8_F 0x11 -#define ID_10_17 0x12 -#define ID_18_1F 0x0B #define MISC_CODE 0x14 #define CLR_P_FLAG 0x18 -#define LOCATE_ON 0x12 -#define LOCATE_OFF 0x0B - -#define LVL_1_MST 0x00 -#define LVL_2_MST 0x40 -#define DOM_LVL_2 0xC0 - #define INIT_SELTD 0x01 #define LEVEL2_TAR 0x02 - -enum scam_id_st { ID0,ID1,ID2,ID3,ID4,ID5,ID6,ID7,ID8,ID9,ID10,ID11,ID12, - ID13,ID14,ID15,ID_UNUSED,ID_UNASSIGNED,ID_ASSIGNED,LEGACY, - CLR_PRIORITY,NO_ID_AVAIL }; +enum scam_id_st { ID0, ID1, ID2, ID3, ID4, ID5, ID6, ID7, ID8, ID9, ID10, ID11, + ID12, + ID13, ID14, ID15, ID_UNUSED, ID_UNASSIGNED, ID_ASSIGNED, LEGACY, + CLR_PRIORITY, NO_ID_AVAIL +}; typedef struct SCCBscam_info { - UCHAR id_string[ID_STRING_LENGTH]; - enum scam_id_st state; - -} SCCBSCAM_INFO, *PSCCBSCAM_INFO; + unsigned char id_string[ID_STRING_LENGTH]; + enum scam_id_st state; +} SCCBSCAM_INFO; -#define SCSI_TEST_UNIT_READY 0x00 -#define SCSI_REZERO_UNIT 0x01 #define SCSI_REQUEST_SENSE 0x03 -#define SCSI_FORMAT_UNIT 0x04 -#define SCSI_REASSIGN 0x07 #define SCSI_READ 0x08 #define SCSI_WRITE 0x0A -#define SCSI_SEEK 0x0B -#define SCSI_INQUIRY 0x12 -#define SCSI_MODE_SELECT 0x15 -#define SCSI_RESERVE_UNIT 0x16 -#define SCSI_RELEASE_UNIT 0x17 -#define SCSI_MODE_SENSE 0x1A #define SCSI_START_STOP_UNIT 0x1B -#define SCSI_SEND_DIAGNOSTIC 0x1D -#define SCSI_READ_CAPACITY 0x25 #define SCSI_READ_EXTENDED 0x28 #define SCSI_WRITE_EXTENDED 0x2A -#define SCSI_SEEK_EXTENDED 0x2B #define SCSI_WRITE_AND_VERIFY 0x2E -#define SCSI_VERIFY 0x2F -#define SCSI_READ_DEFECT_DATA 0x37 -#define SCSI_WRITE_BUFFER 0x3B -#define SCSI_READ_BUFFER 0x3C -#define SCSI_RECV_DIAGNOSTIC 0x1C -#define SCSI_READ_LONG 0x3E -#define SCSI_WRITE_LONG 0x3F -#define SCSI_LAST_SCSI_CMND SCSI_WRITE_LONG -#define SCSI_INVALID_CMND 0xFF - - #define SSGOOD 0x00 #define SSCHECK 0x02 -#define SSCOND_MET 0x04 -#define SSBUSY 0x08 -#define SSRESERVATION_CONFLICT 0x18 -#define SSCMD_TERM 0x22 #define SSQ_FULL 0x28 - -#define SKNO_SEN 0x00 -#define SKRECOV_ERR 0x01 -#define SKNOT_RDY 0x02 -#define SKMED_ERR 0x03 -#define SKHW_ERR 0x04 -#define SKILL_REQ 0x05 -#define SKUNIT_ATTN 0x06 -#define SKDATA_PROTECT 0x07 -#define SKBLNK_CHK 0x08 -#define SKCPY_ABORT 0x0A -#define SKABORT_CMD 0x0B -#define SKEQUAL 0x0C -#define SKVOL_OVF 0x0D -#define SKMIS_CMP 0x0E - - #define SMCMD_COMP 0x00 #define SMEXT 0x01 #define SMSAVE_DATA_PTR 0x02 #define SMREST_DATA_PTR 0x03 #define SMDISC 0x04 -#define SMINIT_DETEC_ERR 0x05 #define SMABORT 0x06 #define SMREJECT 0x07 #define SMNO_OP 0x08 @@ -533,62 +331,31 @@ typedef struct SCCBscam_info { #define SMIDENT 0x80 #define DISC_PRIV 0x40 - #define SMSYNC 0x01 -#define SM10MBS 0x19 /* 100ns */ -#define SM5MBS 0x32 /* 200ns */ -#define SMOFFSET 0x0F /* Maxoffset value */ #define SMWDTR 0x03 #define SM8BIT 0x00 #define SM16BIT 0x01 -#define SM32BIT 0x02 -#define SMIGNORWR 0x23 /* Ignore Wide Residue */ - - -#define ARBITRATION_DELAY 0x01 /* 2.4us using a 40Mhz clock */ -#define BUS_SETTLE_DELAY 0x01 /* 400ns */ -#define BUS_CLEAR_DELAY 0x01 /* 800ns */ - - - -#define SPHASE_TO 0x0A /* 10 second timeout waiting for */ -#define SCMD_TO 0x0F /* Overall command timeout */ - - +#define SMIGNORWR 0x23 /* Ignore Wide Residue */ #define SIX_BYTE_CMD 0x06 -#define TEN_BYTE_CMD 0x0A #define TWELVE_BYTE_CMD 0x0C #define ASYNC 0x00 -#define PERI25NS 0x06 /* 25/4ns to next clock for xbow. */ -#define SYNC10MBS 0x19 -#define SYNC5MBS 0x32 -#define MAX_OFFSET 0x0F /* Maxbyteoffset for Sync Xfers */ - +#define MAX_OFFSET 0x0F /* Maxbyteoffset for Sync Xfers */ #define EEPROM_WD_CNT 256 #define EEPROM_CHECK_SUM 0 #define FW_SIGNATURE 2 #define MODEL_NUMB_0 4 -#define MODEL_NUMB_1 5 #define MODEL_NUMB_2 6 -#define MODEL_NUMB_3 7 #define MODEL_NUMB_4 8 -#define MODEL_NUMB_5 9 -#define IO_BASE_ADDR 10 -#define IRQ_NUMBER 12 -#define PCI_INT_PIN 13 -#define BUS_DELAY 14 /*On time in byte 14 off delay in 15 */ #define SYSTEM_CONFIG 16 #define SCSI_CONFIG 17 #define BIOS_CONFIG 18 -#define SPIN_UP_DELAY 19 #define SCAM_CONFIG 20 #define ADAPTER_SCSI_ID 24 - #define IGNORE_B_SCAN 32 #define SEND_START_ENA 34 #define DEVICE_ENABLE 36 @@ -603,717 +370,405 @@ typedef struct SCCBscam_info { #define SYNC_RATE_TBLcd 50 #define SYNC_RATE_TBLef 52 +#define EE_SCAMBASE 256 +#define SCAM_ENABLED BIT(2) +#define SCAM_LEVEL2 BIT(3) -#define EE_SCAMBASE 256 - - - - #define DOM_MASTER (BIT(0) + BIT(1)) - #define SCAM_ENABLED BIT(2) - #define SCAM_LEVEL2 BIT(3) - +#define RENEGO_ENA BITW(10) +#define CONNIO_ENA BITW(11) +#define GREEN_PC_ENA BITW(12) - #define RENEGO_ENA BITW(10) - #define CONNIO_ENA BITW(11) - #define GREEN_PC_ENA BITW(12) +#define AUTO_RATE_00 00 +#define AUTO_RATE_05 01 +#define AUTO_RATE_10 02 +#define AUTO_RATE_20 03 +#define WIDE_NEGO_BIT BIT(7) +#define DISC_ENABLE_BIT BIT(6) - #define AUTO_RATE_00 00 - #define AUTO_RATE_05 01 - #define AUTO_RATE_10 02 - #define AUTO_RATE_20 03 +#define hp_vendor_id_0 0x00 /* LSB */ +#define ORION_VEND_0 0x4B - #define WIDE_NEGO_BIT BIT(7) - #define DISC_ENABLE_BIT BIT(6) +#define hp_vendor_id_1 0x01 /* MSB */ +#define ORION_VEND_1 0x10 +#define hp_device_id_0 0x02 /* LSB */ +#define ORION_DEV_0 0x30 - - #define hp_vendor_id_0 0x00 /* LSB */ - #define ORION_VEND_0 0x4B - - #define hp_vendor_id_1 0x01 /* MSB */ - #define ORION_VEND_1 0x10 - - #define hp_device_id_0 0x02 /* LSB */ - #define ORION_DEV_0 0x30 - - #define hp_device_id_1 0x03 /* MSB */ - #define ORION_DEV_1 0x81 +#define hp_device_id_1 0x03 /* MSB */ +#define ORION_DEV_1 0x81 /* Sub Vendor ID and Sub Device ID only available in - Harpoon Version 2 and higher */ - - #define hp_sub_vendor_id_0 0x04 /* LSB */ - #define hp_sub_vendor_id_1 0x05 /* MSB */ - #define hp_sub_device_id_0 0x06 /* LSB */ - #define hp_sub_device_id_1 0x07 /* MSB */ - - - #define hp_dual_addr_lo 0x08 - #define hp_dual_addr_lmi 0x09 - #define hp_dual_addr_hmi 0x0A - #define hp_dual_addr_hi 0x0B - - #define hp_semaphore 0x0C - #define SCCB_MGR_ACTIVE BIT(0) - #define TICKLE_ME BIT(1) - #define SCCB_MGR_PRESENT BIT(3) - #define BIOS_IN_USE BIT(4) - - #define hp_user_defined_D 0x0D - - #define hp_reserved_E 0x0E - - #define hp_sys_ctrl 0x0F - - #define STOP_CLK BIT(0) /*Turn off BusMaster Clock */ - #define DRVR_RST BIT(1) /*Firmware Reset to 80C15 chip */ - #define HALT_MACH BIT(3) /*Halt State Machine */ - #define HARD_ABORT BIT(4) /*Hard Abort */ - #define DIAG_MODE BIT(5) /*Diagnostic Mode */ - - #define BM_ABORT_TMOUT 0x50 /*Halt State machine time out */ - - #define hp_sys_cfg 0x10 - - #define DONT_RST_FIFO BIT(7) /*Don't reset FIFO */ - - - #define hp_host_ctrl0 0x11 - - #define DUAL_ADDR_MODE BIT(0) /*Enable 64-bit addresses */ - #define IO_MEM_SPACE BIT(1) /*I/O Memory Space */ - #define RESOURCE_LOCK BIT(2) /*Enable Resource Lock */ - #define IGNOR_ACCESS_ERR BIT(3) /*Ignore Access Error */ - #define HOST_INT_EDGE BIT(4) /*Host interrupt level/edge mode sel */ - #define SIX_CLOCKS BIT(5) /*6 Clocks between Strobe */ - #define DMA_EVEN_PARITY BIT(6) /*Enable DMA Enen Parity */ - -/* - #define BURST_MODE BIT(0) -*/ - - #define hp_reserved_12 0x12 - - #define hp_host_blk_cnt 0x13 - - #define XFER_BLK1 0x00 /* 0 0 0 1 byte per block*/ - #define XFER_BLK2 0x01 /* 0 0 1 2 byte per block*/ - #define XFER_BLK4 0x02 /* 0 1 0 4 byte per block*/ - #define XFER_BLK8 0x03 /* 0 1 1 8 byte per block*/ - #define XFER_BLK16 0x04 /* 1 0 0 16 byte per block*/ - #define XFER_BLK32 0x05 /* 1 0 1 32 byte per block*/ - #define XFER_BLK64 0x06 /* 1 1 0 64 byte per block*/ - - #define BM_THRESHOLD 0x40 /* PCI mode can only xfer 16 bytes*/ + Harpoon Version 2 and higher */ +#define hp_sub_device_id_0 0x06 /* LSB */ - #define hp_reserved_14 0x14 - #define hp_reserved_15 0x15 - #define hp_reserved_16 0x16 +#define hp_semaphore 0x0C +#define SCCB_MGR_ACTIVE BIT(0) +#define TICKLE_ME BIT(1) +#define SCCB_MGR_PRESENT BIT(3) +#define BIOS_IN_USE BIT(4) - #define hp_int_mask 0x17 +#define hp_sys_ctrl 0x0F - #define INT_CMD_COMPL BIT(0) /* DMA command complete */ - #define INT_EXT_STATUS BIT(1) /* Extended Status Set */ - #define INT_SCSI BIT(2) /* Scsi block interrupt */ - #define INT_FIFO_RDY BIT(4) /* FIFO data ready */ +#define STOP_CLK BIT(0) /*Turn off BusMaster Clock */ +#define DRVR_RST BIT(1) /*Firmware Reset to 80C15 chip */ +#define HALT_MACH BIT(3) /*Halt State Machine */ +#define HARD_ABORT BIT(4) /*Hard Abort */ +#define hp_host_blk_cnt 0x13 - #define hp_xfer_cnt_lo 0x18 - #define hp_xfer_cnt_mi 0x19 - #define hp_xfer_cnt_hi 0x1A - #define hp_xfer_cmd 0x1B +#define XFER_BLK64 0x06 /* 1 1 0 64 byte per block */ - #define XFER_HOST_DMA 0x00 /* 0 0 0 Transfer Host -> DMA */ - #define XFER_DMA_HOST 0x01 /* 0 0 1 Transfer DMA -> Host */ - #define XFER_HOST_MPU 0x02 /* 0 1 0 Transfer Host -> MPU */ - #define XFER_MPU_HOST 0x03 /* 0 1 1 Transfer MPU -> Host */ - #define XFER_DMA_MPU 0x04 /* 1 0 0 Transfer DMA -> MPU */ - #define XFER_MPU_DMA 0x05 /* 1 0 1 Transfer MPU -> DMA */ - #define SET_SEMAPHORE 0x06 /* 1 1 0 Set Semaphore */ - #define XFER_NOP 0x07 /* 1 1 1 Transfer NOP */ - #define XFER_MB_MPU 0x06 /* 1 1 0 Transfer MB -> MPU */ - #define XFER_MB_DMA 0x07 /* 1 1 1 Transfer MB -> DMA */ +#define BM_THRESHOLD 0x40 /* PCI mode can only xfer 16 bytes */ +#define hp_int_mask 0x17 - #define XFER_HOST_AUTO 0x00 /* 0 0 Auto Transfer Size */ - #define XFER_HOST_8BIT 0x08 /* 0 1 8 BIT Transfer Size */ - #define XFER_HOST_16BIT 0x10 /* 1 0 16 BIT Transfer Size */ - #define XFER_HOST_32BIT 0x18 /* 1 1 32 BIT Transfer Size */ +#define INT_CMD_COMPL BIT(0) /* DMA command complete */ +#define INT_EXT_STATUS BIT(1) /* Extended Status Set */ - #define XFER_DMA_8BIT 0x20 /* 0 1 8 BIT Transfer Size */ - #define XFER_DMA_16BIT 0x40 /* 1 0 16 BIT Transfer Size */ +#define hp_xfer_cnt_lo 0x18 +#define hp_xfer_cnt_hi 0x1A +#define hp_xfer_cmd 0x1B - #define DISABLE_INT BIT(7) /*Do not interrupt at end of cmd. */ +#define XFER_HOST_DMA 0x00 /* 0 0 0 Transfer Host -> DMA */ +#define XFER_DMA_HOST 0x01 /* 0 0 1 Transfer DMA -> Host */ - #define HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_8BIT)) - #define HOST_RD_CMD ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_8BIT)) - #define WIDE_HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_16BIT)) - #define WIDE_HOST_RD_CMD ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_16BIT)) +#define XFER_HOST_AUTO 0x00 /* 0 0 Auto Transfer Size */ - #define hp_host_addr_lo 0x1C - #define hp_host_addr_lmi 0x1D - #define hp_host_addr_hmi 0x1E - #define hp_host_addr_hi 0x1F +#define XFER_DMA_8BIT 0x20 /* 0 1 8 BIT Transfer Size */ - #define hp_pio_data 0x20 - #define hp_reserved_21 0x21 - #define hp_ee_ctrl 0x22 +#define DISABLE_INT BIT(7) /*Do not interrupt at end of cmd. */ - #define EXT_ARB_ACK BIT(7) - #define SCSI_TERM_ENA_H BIT(6) /* SCSI high byte terminator */ - #define SEE_MS BIT(5) - #define SEE_CS BIT(3) - #define SEE_CLK BIT(2) - #define SEE_DO BIT(1) - #define SEE_DI BIT(0) +#define HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_8BIT)) +#define HOST_RD_CMD ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_8BIT)) - #define EE_READ 0x06 - #define EE_WRITE 0x05 - #define EWEN 0x04 - #define EWEN_ADDR 0x03C0 - #define EWDS 0x04 - #define EWDS_ADDR 0x0000 +#define hp_host_addr_lo 0x1C +#define hp_host_addr_hmi 0x1E - #define hp_brdctl 0x23 +#define hp_ee_ctrl 0x22 - #define DAT_7 BIT(7) - #define DAT_6 BIT(6) - #define DAT_5 BIT(5) - #define BRD_STB BIT(4) - #define BRD_CS BIT(3) - #define BRD_WR BIT(2) +#define EXT_ARB_ACK BIT(7) +#define SCSI_TERM_ENA_H BIT(6) /* SCSI high byte terminator */ +#define SEE_MS BIT(5) +#define SEE_CS BIT(3) +#define SEE_CLK BIT(2) +#define SEE_DO BIT(1) +#define SEE_DI BIT(0) - #define hp_reserved_24 0x24 - #define hp_reserved_25 0x25 +#define EE_READ 0x06 +#define EE_WRITE 0x05 +#define EWEN 0x04 +#define EWEN_ADDR 0x03C0 +#define EWDS 0x04 +#define EWDS_ADDR 0x0000 +#define hp_bm_ctrl 0x26 +#define SCSI_TERM_ENA_L BIT(0) /*Enable/Disable external terminators */ +#define FLUSH_XFER_CNTR BIT(1) /*Flush transfer counter */ +#define FORCE1_XFER BIT(5) /*Always xfer one byte in byte mode */ +#define FAST_SINGLE BIT(6) /*?? */ +#define BMCTRL_DEFAULT (FORCE1_XFER|FAST_SINGLE|SCSI_TERM_ENA_L) - #define hp_bm_ctrl 0x26 +#define hp_sg_addr 0x28 +#define hp_page_ctrl 0x29 - #define SCSI_TERM_ENA_L BIT(0) /*Enable/Disable external terminators */ - #define FLUSH_XFER_CNTR BIT(1) /*Flush transfer counter */ - #define BM_XFER_MIN_8 BIT(2) /*Enable bus master transfer of 9 */ - #define BIOS_ENA BIT(3) /*Enable BIOS/FLASH Enable */ - #define FORCE1_XFER BIT(5) /*Always xfer one byte in byte mode */ - #define FAST_SINGLE BIT(6) /*?? */ +#define SCATTER_EN BIT(0) +#define SGRAM_ARAM BIT(1) +#define G_INT_DISABLE BIT(3) /* Enable/Disable all Interrupts */ +#define NARROW_SCSI_CARD BIT(4) /* NARROW/WIDE SCSI config pin */ - #define BMCTRL_DEFAULT (FORCE1_XFER|FAST_SINGLE|SCSI_TERM_ENA_L) +#define hp_pci_stat_cfg 0x2D - #define hp_reserved_27 0x27 +#define REC_MASTER_ABORT BIT(5) /*received Master abort */ - #define hp_sg_addr 0x28 - #define hp_page_ctrl 0x29 +#define hp_rev_num 0x33 - #define SCATTER_EN BIT(0) - #define SGRAM_ARAM BIT(1) - #define BIOS_SHADOW BIT(2) - #define G_INT_DISABLE BIT(3) /* Enable/Disable all Interrupts */ - #define NARROW_SCSI_CARD BIT(4) /* NARROW/WIDE SCSI config pin */ +#define hp_stack_data 0x34 +#define hp_stack_addr 0x35 - #define hp_reserved_2A 0x2A - #define hp_pci_cmd_cfg 0x2B +#define hp_ext_status 0x36 - #define IO_SPACE_ENA BIT(0) /*enable I/O space */ - #define MEM_SPACE_ENA BIT(1) /*enable memory space */ - #define BUS_MSTR_ENA BIT(2) /*enable bus master operation */ - #define MEM_WI_ENA BIT(4) /*enable Write and Invalidate */ - #define PAR_ERR_RESP BIT(6) /*enable parity error responce. */ - - #define hp_reserved_2C 0x2C - - #define hp_pci_stat_cfg 0x2D - - #define DATA_PARITY_ERR BIT(0) - #define REC_TARGET_ABORT BIT(4) /*received Target abort */ - #define REC_MASTER_ABORT BIT(5) /*received Master abort */ - #define SIG_SYSTEM_ERR BIT(6) - #define DETECTED_PAR_ERR BIT(7) - - #define hp_reserved_2E 0x2E - - #define hp_sys_status 0x2F - - #define SLV_DATA_RDY BIT(0) /*Slave data ready */ - #define XFER_CNT_ZERO BIT(1) /*Transfer counter = 0 */ - #define BM_FIFO_EMPTY BIT(2) /*FIFO empty */ - #define BM_FIFO_FULL BIT(3) /*FIFO full */ - #define HOST_OP_DONE BIT(4) /*host operation done */ - #define DMA_OP_DONE BIT(5) /*DMA operation done */ - #define SLV_OP_DONE BIT(6) /*Slave operation done */ - #define PWR_ON_FLAG BIT(7) /*Power on flag */ - - #define hp_reserved_30 0x30 - - #define hp_host_status0 0x31 - - #define HOST_TERM BIT(5) /*Host Terminal Count */ - #define HOST_TRSHLD BIT(6) /*Host Threshold */ - #define CONNECTED_2_HOST BIT(7) /*Connected to Host */ - - #define hp_reserved_32 0x32 - - #define hp_rev_num 0x33 - - #define REV_A_CONST 0x0E - #define REV_B_CONST 0x0E - - #define hp_stack_data 0x34 - #define hp_stack_addr 0x35 - - #define hp_ext_status 0x36 - - #define BM_FORCE_OFF BIT(0) /*Bus Master is for |