diff options
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a7779.c')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 2624 |
1 files changed, 2624 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c new file mode 100644 index 00000000000..13feaa0c0eb --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -0,0 +1,2624 @@ +/* + * r8a7779 processor support - PFC hardware block + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/kernel.h> +#include <mach/r8a7779.h> + +#include "sh_pfc.h" + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_32_PORT6(fn, pfx, sfx) \ + PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ + PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ + PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ + PORT_1(fn, pfx##8, sfx) + +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_5_, sfx), \ + CPU_32_PORT6(fn, pfx##_6_, sfx) + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */ + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */ + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */ + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */ + + /* GPSR0 */ + FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17, + FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10, + FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19, + FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0, + FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11, + FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16, + FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9, + FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29, + + /* GPSR1 */ + FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8, + FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14, + FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20, + FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26, + FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0, + FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6, + FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11, + FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21, + + /* GPSR2 */ + FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23, + FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2, + FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7, + FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, + FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24, + FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3, + FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, + FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26, + + /* GPSR3 */ + FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, + FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18, + FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, + FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12, + FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27, + FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23, + FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23, + FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2, + + /* GPSR4 */ + FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9, + FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20, + FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0, + FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10, + FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12, + FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4, + FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1, + FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19, + + /* GPSR5 */ + FN_A1, FN_A2, FN_A3, FN_A4, + FN_A5, FN_A6, FN_A7, FN_A8, + FN_A9, FN_A10, FN_A11, FN_A12, + FN_A13, FN_A14, FN_A15, FN_A16, + FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0, + FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22, + FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26, + FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5, + + /* GPSR6 */ + FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15, + FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19, + FN_IP3_20, + + /* IPSR0 */ + FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7, + FN_HRTS1, FN_RX4_C, + FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, + FN_CS0, FN_HSPI_CS2_B, + FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, + FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5, + FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B, + FN_CTS0_B, + FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4, + FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, + FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1, + FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0, + FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, + FN_A20, FN_TX5_D, FN_HSPI_TX2_B, + FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3, + FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2, + FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C, + FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0, + FN_SCIF_CLK, FN_TCLK0_C, + + /* IPSR1 */ + FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, + FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7, + FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE, + FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, + FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B, + FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, + FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0, + FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1, + FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5, + FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0, + FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B, + FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4, + FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT, + FN_PWM4, FN_RX4, FN_HTX0, FN_TX1, + FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2, + FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34, + + /* IPSR2 */ + FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C, + FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19, + FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1, + FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B, + FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16, + FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1, + FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C, + FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0, + FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS, + FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25, + FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, + FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1, + FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B, + FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2, + FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4, + FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6, + FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8, + FN_DREQ1, FN_SCL2, FN_AUDATA2, + + /* IPSR3 */ + FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2, + FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3, + FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5, + FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7, + FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, + FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1, + FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B, + FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18, + FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20, + FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22, + FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS, + FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK, + FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B, + FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC, + FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, + FN_TX2_C, FN_SCL2_C, FN_REMOCON, + + /* IPSR4 */ + FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C, + FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C, + FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0, + FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E, + FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, + FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, + FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3, + FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5, + FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7, + FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, + FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D, + FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3, + FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2, + FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4, + FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6, + FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0, + FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5, + FN_SCK0_D, + + /* IPSR5 */ + FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1, + FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4, + FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6, + FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D, + FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB, + FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD, + FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, + FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B, + FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB, + FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, + FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B, + FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D, + FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, + FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, + FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, + FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2, + FN_CAN_DEBUGOUT0, FN_MOUT0, + + /* IPSR6 */ + FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129, + FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, + FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, + FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6, + FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34, + FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C, + FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B, + FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4, + FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK, + FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5, + FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5, + FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6, + FN_ADICHS0, FN_CAN0_TX, FN_IERX_B, + + /* IPSR7 */ + FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B, + FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B, + FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B, + FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, + FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, + FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8, + FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK, + FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11, + FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1, + FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1, + FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1, + FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1, + FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2, + FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B, + + /* IPSR8 */ + FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK, + FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28, + FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, + FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, + FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0, + FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14, + FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0, + FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7, + FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39, + FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK, + FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK, + FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, + FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, + FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D, + FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, + FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C, + + /* IPSR9 */ + FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1, + FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0, + FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2, + FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, + FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, + FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, + FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, + FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, + FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV, + FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4, + FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5, + FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6, + FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7, + FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9, + + /* IPSR10 */ + FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B, + FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C, + FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C, + FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2, + FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, + FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK, + FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK, + FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B, + FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6, + FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK, + FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO, + FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL, + FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3, + FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C, + FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, + FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, + + /* IPSR11 */ + FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK, + FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, + FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, + FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3, + FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B, + FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST, + FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, + FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B, + FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, + FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, + FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0, + FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2, + FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1, + FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, + + /* IPSR12 */ + FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1, + FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3, + FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B, + FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C, + FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5, + FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B, + FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB, + FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7, + FN_GPS_MAG, FN_FCE, FN_SCK4_B, + + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, + FN_SEL_SCIF3_3, FN_SEL_SCIF3_4, + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, + FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, + FN_SEL_VI0_0, FN_SEL_VI0_1, + FN_SEL_SD2_0, FN_SEL_SD2_1, + FN_SEL_INT3_0, FN_SEL_INT3_1, + FN_SEL_INT2_0, FN_SEL_INT2_1, + FN_SEL_INT1_0, FN_SEL_INT1_1, + FN_SEL_INT0_0, FN_SEL_INT0_1, + FN_SEL_IE_0, FN_SEL_IE_1, + FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, + FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1, + FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, + + FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, + FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3, + FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2, + FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, + FN_SEL_ADI_0, FN_SEL_ADI_1, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + FN_SEL_SIM_0, FN_SEL_SIM_1, + FN_SEL_HSPI2_0, FN_SEL_HSPI2_1, + FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3, + FN_SEL_I2C3_0, FN_SEL_I2C3_1, + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK, + A19_MARK, + + RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK, + HRTS1_MARK, RX4_C_MARK, + CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK, + CS0_MARK, HSPI_CS2_B_MARK, + CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK, + A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK, + HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK, + A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK, + HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK, + A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK, + A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK, + A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK, + A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK, + A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK, + BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK, + ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK, + USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, + SCIF_CLK_MARK, TCLK0_C_MARK, + + EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK, + FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK, + EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK, + ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK, + FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK, + HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK, + EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK, + ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK, + TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK, + SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK, + VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK, + SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK, + MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK, + PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK, + SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK, + CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK, + + HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK, + SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK, + CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK, + MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK, + SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK, + CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK, + STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK, + SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK, + RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK, + CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK, + CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK, + GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK, + LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK, + AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK, + DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK, + DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK, + DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK, + DREQ1_MARK, SCL2_MARK, AUDATA2_MARK, + + DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK, + AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK, + LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK, + LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK, + LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK, + SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK, + LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK, + AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK, + DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK, + DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK, + DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK, + TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK, + DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK, + SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, + QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK, + TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK, + + DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK, + DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK, + DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK, + VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK, + AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK, + PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK, + CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK, + VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK, + VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK, + VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK, + SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK, + DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK, + SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK, + VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK, + VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK, + VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK, + VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK, + SCK0_D_MARK, + + DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK, + RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK, + DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK, + DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK, + DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK, + HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK, + SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK, + VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK, + VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK, + TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK, + VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK, + GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK, + QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK, + GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK, + RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK, + VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK, + GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK, + USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK, + + SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK, + CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK, + MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK, + SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK, + CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK, + SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK, + SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK, + CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK, + SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK, + ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK, + SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK, + SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK, + SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK, + + SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK, + SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK, + SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK, + HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK, + SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK, + IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK, + VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK, + ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK, + TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK, + RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK, + SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK, + TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK, + RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK, + RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK, + + HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK, + CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK, + CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK, + AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK, + CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK, + CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK, + CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK, + CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK, + AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK, + CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK, + PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK, + VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK, + MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK, + VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK, + MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK, + RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK, + + VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK, + VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK, + VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK, + MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK, + VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK, + MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK, + MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK, + IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK, + IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK, + MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK, + ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK, + VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK, + VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK, + VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK, + VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK, + + VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK, + ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK, + DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK, + VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK, + ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK, + IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK, + SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK, + TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK, + HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK, + VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK, + TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK, + ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK, + TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK, + VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK, + PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK, + SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK, + + VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK, + ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK, + SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK, + SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK, + VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK, + ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK, + SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK, + VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK, + HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK, + MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK, + SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK, + VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK, + DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK, + VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK, + DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK, + + VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK, + SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK, + SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK, + VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK, + SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK, + GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK, + VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK, + RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK, + GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK, + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(AVS1_MARK, FN_AVS1), + PINMUX_DATA(AVS1_MARK, FN_AVS1), + PINMUX_DATA(A17_MARK, FN_A17), + PINMUX_DATA(A18_MARK, FN_A18), + PINMUX_DATA(A19_MARK, FN_A19), + + PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP0_2_0, PWM1), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2), + PINMUX_IPSR_DATA(IP0_5_3, BS), + PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2), + PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2), + PINMUX_IPSR_DATA(IP0_5_3, FD2), + PINMUX_IPSR_DATA(IP0_5_3, ATADIR0), + PINMUX_IPSR_DATA(IP0_5_3, SDSELF), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP0_5_3, TX4_C), + PINMUX_IPSR_DATA(IP0_7_6, A0), + PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3), + PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3), + PINMUX_IPSR_DATA(IP0_7_6, FD3), + PINMUX_IPSR_DATA(IP0_9_8, A20), + PINMUX_IPSR_DATA(IP0_9_8, TX5_D), + PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B), + PINMUX_IPSR_DATA(IP0_11_10, A21), + PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1), + PINMUX_IPSR_DATA(IP0_13_12, A22), + PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1), + PINMUX_IPSR_DATA(IP0_13_12, VI1_R0), + PINMUX_IPSR_DATA(IP0_15_14, A23), + PINMUX_IPSR_DATA(IP0_15_14, FCLE), + PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0), + PINMUX_IPSR_DATA(IP0_15_14, VI1_R1), + PINMUX_IPSR_DATA(IP0_18_16, A24), + PINMUX_IPSR_DATA(IP0_18_16, SD1_CD), + PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4), + PINMUX_IPSR_DATA(IP0_18_16, FD4), + PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0), + PINMUX_IPSR_DATA(IP0_18_16, VI1_R2), + PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP0_22_19, A25), + PINMUX_IPSR_DATA(IP0_22_19, SD1_WP), + PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5), + PINMUX_IPSR_DATA(IP0_22_19, FD5), + PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0), + PINMUX_IPSR_DATA(IP0_22_19, VI1_R3), + PINMUX_IPSR_DATA(IP0_22_19, TX5_B), + PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP0_24_23, CLKOUT), + PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C), + PINMUX_IPSR_DATA(IP0_24_23, PWM0_B), + PINMUX_IPSR_DATA(IP0_25, CS0), + PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1), + PINMUX_IPSR_DATA(IP0_27_26, CS1_A26), + PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2), + PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B), + PINMUX_IPSR_DATA(IP0_30_28, RD_WR), + PINMUX_IPSR_DATA(IP0_30_28, FWE), + PINMUX_IPSR_DATA(IP0_30_28, ATAG0), + PINMUX_IPSR_DATA(IP0_30_28, VI1_R7), + PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2), + + PINMUX_IPSR_DATA(IP1_1_0, EX_CS0), + PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2), + PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6), + PINMUX_IPSR_DATA(IP1_1_0, FD6), + PINMUX_IPSR_DATA(IP1_3_2, EX_CS1), + PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7), + PINMUX_IPSR_DATA(IP1_3_2, FD7), + PINMUX_IPSR_DATA(IP1_6_4, EX_CS2), + PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK), + PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK), + PINMUX_IPSR_DATA(IP1_6_4, FALE), + PINMUX_IPSR_DATA(IP1_6_4, ATACS00), + PINMUX_IPSR_DATA(IP1_10_7, EX_CS3), + PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD), + PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD), + PINMUX_IPSR_DATA(IP1_10_7, FRE), + PINMUX_IPSR_DATA(IP1_10_7, ATACS10), + PINMUX_IPSR_DATA(IP1_10_7, VI1_R4), + PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0), + PINMUX_IPSR_DATA(IP1_14_11, EX_CS4), + PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0), + PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0), + PINMUX_IPSR_DATA(IP1_14_11, FD0), + PINMUX_IPSR_DATA(IP1_14_11, ATARD0), + PINMUX_IPSR_DATA(IP1_14_11, VI1_R5), + PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1), + PINMUX_IPSR_DATA(IP1_14_11, HTX1), + PINMUX_IPSR_DATA(IP1_14_11, TX2_E), + PINMUX_IPSR_DATA(IP1_14_11, TX0_B), + PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0), + PINMUX_IPSR_DATA(IP1_18_15, EX_CS5), + PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1), + PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1), + PINMUX_IPSR_DATA(IP1_18_15, FD1), + PINMUX_IPSR_DATA(IP1_18_15, ATAWR0), + PINMUX_IPSR_DATA(IP1_18_15, VI1_R6), + PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4), + PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0), + PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK), + PINMUX_IPSR_DATA(IP1_20_19, PWM2), + PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG), + PINMUX_IPSR_DATA(IP1_22_21, PWM3), + PINMUX_IPSR_DATA(IP1_22_21, TX4), + PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT), + PINMUX_IPSR_DATA(IP1_24_23, PWM4), + PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP1_28_25, HTX0), + PINMUX_IPSR_DATA(IP1_28_25, TX1), + PINMUX_IPSR_DATA(IP1_28_25, SDATA), + PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK), + PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2), + PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10), + PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18), + PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26), + PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34), + + PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP2_3_0, SCKZ), + PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI), + PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3), + PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11), + PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19), + PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27), + PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35), + PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP2_7_4, MTS), + PINMUX_IPSR_DATA(IP2_7_4, PWM5), + PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO), + PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0), + PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8), + PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16), + PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24), + PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32), + PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP2_11_8, STM), + PINMUX_IPSR_DATA(IP2_11_8, PWM0_D), + PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2), + PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST), + PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1), + PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT), + PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP2_15_12, MDATA), + PINMUX_IPSR_DATA(IP2_15_12, TX0_C), + PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS), + PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1), + PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9), + PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17), + PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25), + PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33), + PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0), + PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0), + PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1), + PINMUX_IPSR_DATA(IP2_18_16, AUDATA0), + PINMUX_IPSR_DATA(IP2_18_16, TX5_C), + PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1), + PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1), + PINMUX_IPSR_DATA(IP2_21_19, DACK0), + PINMUX_IPSR_DATA(IP2_21_19, DRACK0), + PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1), + PINMUX_IPSR_DATA(IP2_21_19, AUDATA1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2), + PINMUX_IPSR_DATA(IP2_22, DU0_DR2), + PINMUX_IPSR_DATA(IP2_22, LCDOUT2), + PINMUX_IPSR_DATA(IP2_23, DU0_DR3), + PINMUX_IPSR_DATA(IP2_23, LCDOUT3), + PINMUX_IPSR_DATA(IP2_24, DU0_DR4), + PINMUX_IPSR_DATA(IP2_24, LCDOUT4), + PINMUX_IPSR_DATA(IP2_25, DU0_DR5), + PINMUX_IPSR_DATA(IP2_25, LCDOUT5), + PINMUX_IPSR_DATA(IP2_26, DU0_DR6), + PINMUX_IPSR_DATA(IP2_26, LCDOUT6), + PINMUX_IPSR_DATA(IP2_27, DU0_DR7), + PINMUX_IPSR_DATA(IP2_27, LCDOUT7), + PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0), + PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8), + PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0), + PINMUX_IPSR_DATA(IP2_30_28, AUDATA2), + + PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1), + PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9), + PINMUX_IPSR_DATA(IP3_2_0, DACK1), + PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0), + PINMUX_IPSR_DATA(IP3_2_0, AUDATA3), + PINMUX_IPSR_DATA(IP3_3, DU0_DG2), + PINMUX_IPSR_DATA(IP3_3, LCDOUT10), + PINMUX_IPSR_DATA(IP3_4, DU0_DG3), + PINMUX_IPSR_DATA(IP3_4, LCDOUT11), + PINMUX_IPSR_DATA(IP3_5, DU0_DG4), + PINMUX_IPSR_DATA(IP3_5, LCDOUT12), + PINMUX_IPSR_DATA(IP3_6, DU0_DG5), + PINMUX_IPSR_DATA(IP3_6, LCDOUT13), + PINMUX_IPSR_DATA(IP3_7, DU0_DG6), + PINMUX_IPSR_DATA(IP3_7, LCDOUT14), + PINMUX_IPSR_DATA(IP3_8, DU0_DG7), + PINMUX_IPSR_DATA(IP3_8, LCDOUT15), + PINMUX_IPSR_DATA( |